41 #define	SPI_MST_CTL_GO			(BIT(0))
43 #define SPI_PERI_ADDR_BASE		(0x160000)
44 #define SPI_SYSTEM_ADDR_BASE		(0x2000)
45 #define	SPI_MST1_ADDR_BASE		(0x800)
47 #define DEV_REV_REG			(SPI_SYSTEM_ADDR_BASE + 0x00)
48 #define SPI_SYSLOCK_REG			(SPI_SYSTEM_ADDR_BASE + 0xA0)
49 #define SPI_CONFIG_PERI_ENABLE_REG	(SPI_SYSTEM_ADDR_BASE + 0x108)
52 #define DEV_REV_MASK			(GENMASK(7, 0))
55 #define SPI0				(0)
59 #define SPI_DMA_ADDR_BASE		(0x1000)
60 #define SPI_DMA_GLOBAL_WR_ENGINE_EN	(SPI_DMA_ADDR_BASE + 0x0C)
61 #define SPI_DMA_WR_DOORBELL_REG		(SPI_DMA_ADDR_BASE + 0x10)
62 #define SPI_DMA_GLOBAL_RD_ENGINE_EN	(SPI_DMA_ADDR_BASE + 0x2C)
63 #define SPI_DMA_RD_DOORBELL_REG		(SPI_DMA_ADDR_BASE + 0x30)
64 #define SPI_DMA_INTR_WR_STS		(SPI_DMA_ADDR_BASE + 0x4C)
65 #define SPI_DMA_WR_INT_MASK		(SPI_DMA_ADDR_BASE + 0x54)
66 #define SPI_DMA_INTR_WR_CLR		(SPI_DMA_ADDR_BASE + 0x58)
67 #define SPI_DMA_ERR_WR_STS		(SPI_DMA_ADDR_BASE + 0x5C)
68 #define SPI_DMA_INTR_IMWR_WDONE_LOW	(SPI_DMA_ADDR_BASE + 0x60)
69 #define SPI_DMA_INTR_IMWR_WDONE_HIGH	(SPI_DMA_ADDR_BASE + 0x64)
70 #define SPI_DMA_INTR_IMWR_WABORT_LOW	(SPI_DMA_ADDR_BASE + 0x68)
71 #define SPI_DMA_INTR_IMWR_WABORT_HIGH	(SPI_DMA_ADDR_BASE + 0x6C)
72 #define SPI_DMA_INTR_WR_IMWR_DATA	(SPI_DMA_ADDR_BASE + 0x70)
73 #define SPI_DMA_INTR_RD_STS		(SPI_DMA_ADDR_BASE + 0xA0)
74 #define SPI_DMA_RD_INT_MASK		(SPI_DMA_ADDR_BASE + 0xA8)
75 #define SPI_DMA_INTR_RD_CLR		(SPI_DMA_ADDR_BASE + 0xAC)
76 #define SPI_DMA_ERR_RD_STS		(SPI_DMA_ADDR_BASE + 0xB8)
77 #define SPI_DMA_INTR_IMWR_RDONE_LOW	(SPI_DMA_ADDR_BASE + 0xCC)
78 #define SPI_DMA_INTR_IMWR_RDONE_HIGH	(SPI_DMA_ADDR_BASE + 0xD0)
79 #define SPI_DMA_INTR_IMWR_RABORT_LOW	(SPI_DMA_ADDR_BASE + 0xD4)
80 #define SPI_DMA_INTR_IMWR_RABORT_HIGH	(SPI_DMA_ADDR_BASE + 0xD8)
81 #define SPI_DMA_INTR_RD_IMWR_DATA	(SPI_DMA_ADDR_BASE + 0xDC)
83 #define SPI_DMA_CH0_WR_BASE		(SPI_DMA_ADDR_BASE + 0x200)
84 #define SPI_DMA_CH0_RD_BASE		(SPI_DMA_ADDR_BASE + 0x300)
85 #define SPI_DMA_CH1_WR_BASE		(SPI_DMA_ADDR_BASE + 0x400)
86 #define SPI_DMA_CH1_RD_BASE		(SPI_DMA_ADDR_BASE + 0x500)
88 #define SPI_DMA_CH_CTL1_OFFSET		(0x00)
89 #define SPI_DMA_CH_XFER_LEN_OFFSET	(0x08)
90 #define SPI_DMA_CH_SAR_LO_OFFSET	(0x0C)
91 #define SPI_DMA_CH_SAR_HI_OFFSET	(0x10)
92 #define SPI_DMA_CH_DAR_LO_OFFSET	(0x14)
93 #define SPI_DMA_CH_DAR_HI_OFFSET	(0x18)
95 #define SPI_DMA_CH0_DONE_INT		BIT(0)
105 /* x refers to SPI Host Controller HW instance id in the below macros - 0 or 1 */
107 #define	SPI_MST_CMD_BUF_OFFSET(x)		(((x) * SPI_MST1_ADDR_BASE) + 0x00)
108 #define	SPI_MST_RSP_BUF_OFFSET(x)		(((x) * SPI_MST1_ADDR_BASE) + 0x200)
109 #define	SPI_MST_CTL_REG_OFFSET(x)		(((x) * SPI_MST1_ADDR_BASE) + 0x400)
110 #define	SPI_MST_EVENT_REG_OFFSET(x)		(((x) * SPI_MST1_ADDR_BASE) + 0x420)
111 #define	SPI_MST_EVENT_MASK_REG_OFFSET(x)	(((x) * SPI_MST1_ADDR_BASE) + 0x424)
112 #define	SPI_MST_PAD_CTL_REG_OFFSET(x)		(((x) * SPI_MST1_ADDR_BASE) + 0x460)
113 #define	SPIALERT_MST_DB_REG_OFFSET(x)		(((x) * SPI_MST1_ADDR_BASE) + 0x464)
114 #define	SPIALERT_MST_VAL_REG_OFFSET(x)		(((x) * SPI_MST1_ADDR_BASE) + 0x468)
115 #define	SPI_PCI_CTRL_REG_OFFSET(x)		(((x) * SPI_MST1_ADDR_BASE) + 0x480)
122 #define SPI_DMA_ENGINE_EN			(0x1)
123 #define SPI_DMA_ENGINE_DIS			(0x0)
129 #define VENDOR_ID_MCHP 0x1055
131 #define SPI_SUSPEND_CONFIG 0x101
132 #define SPI_RESUME_CONFIG 0x203
170 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
171 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
172 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
173 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
174 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
175 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
176 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
177 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
178 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
179 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
180 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
181 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
182 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
183 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
184 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
185 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
186 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
187 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
188 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
189 	{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
190 	{ 0, }
212 	writel(0x0, par->reg_base + SPI_SYSLOCK_REG);  in pci1xxxx_release_sys_lock()
234 	if (spi_bus->dev_rev >= 0xC0) {  in pci1xxxx_check_spi_can_dma()
246 	if (spi_bus->dev_rev < 0xC0 || pf_num)  in pci1xxxx_check_spi_can_dma()
272 	return 0;  in pci1xxxx_check_spi_can_dma()
300 	return 0;  in pci1xxxx_spi_dma_init()
314 		regval |= (spi_get_chipselect(spi, 0) << 25);  in pci1xxxx_spi_set_cs()
323 	u8 val = 0;  in pci1xxxx_get_clock_div()
425 	p->bytes_recvd = 0;  in pci1xxxx_spi_transfer_with_io()
434 		bytes_transfered = 0;  in pci1xxxx_spi_transfer_with_io()
435 		bytes_recvd = 0;  in pci1xxxx_spi_transfer_with_io()
437 		if (transfer_len % SPI_MAX_DATA_LEN != 0)  in pci1xxxx_spi_transfer_with_io()
440 		for (loop_iter = 0; loop_iter < loop_count; loop_iter++) {  in pci1xxxx_spi_transfer_with_io()
442 			if ((transfer_len % SPI_MAX_DATA_LEN != 0) &&  in pci1xxxx_spi_transfer_with_io()
468 	return 0;  in pci1xxxx_spi_transfer_with_io()
477 	dma_addr_t rx_dma_addr = 0;  in pci1xxxx_spi_transfer_with_dma()
478 	dma_addr_t tx_dma_addr = 0;  in pci1xxxx_spi_transfer_with_dma()
479 	int ret = 0;  in pci1xxxx_spi_transfer_with_dma()
496 	p->bytes_recvd = 0;  in pci1xxxx_spi_transfer_with_dma()
526 						 (regval == 0x0), 0, USEC_PER_MSEC);  in pci1xxxx_spi_transfer_with_dma()
547 						 (regval == 0x0), 0, USEC_PER_MSEC);  in pci1xxxx_spi_transfer_with_dma()
560 	ret = 0;  in pci1xxxx_spi_transfer_with_dma()
600 	dma_addr_t tx_dma_addr = 0;  in pci1xxxx_spi_setup_next_dma_transfer()
601 	dma_addr_t rx_dma_addr = 0;  in pci1xxxx_spi_setup_next_dma_transfer()
708 	hw_inst_cnt = ent->driver_data & 0x0f;  in pci1xxxx_spi_probe()
709 	start = (ent->driver_data & 0xf0) >> 4;  in pci1xxxx_spi_probe()
713 		only_sec_inst = 0;  in pci1xxxx_spi_probe()
725 	for (iter = 0; iter < hw_inst_cnt; iter++) {  in pci1xxxx_spi_probe()
748 			spi_bus->reg_base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0));  in pci1xxxx_spi_probe()
756 			if (ret < 0) {  in pci1xxxx_spi_probe()
768 			spi_sub_ptr->irq = pci_irq_vector(pdev, 0);  in pci1xxxx_spi_probe()
773 			if (ret < 0) {  in pci1xxxx_spi_probe()
785 			regval = readl(spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0));  in pci1xxxx_spi_probe()
791 			writel(regval, spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0));  in pci1xxxx_spi_probe()
808 			if (ret < 0) {  in pci1xxxx_spi_probe()
835 	return 0;  in pci1xxxx_spi_probe()
875 	for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) {  in pci1xxxx_spi_resume()
882 		store_restore_config(spi_ptr, spi_sub_ptr, iter, 0);  in pci1xxxx_spi_resume()
885 	return 0;  in pci1xxxx_spi_resume()
895 	for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) {  in pci1xxxx_spi_suspend()
908 	return 0;  in pci1xxxx_spi_suspend()