Lines Matching +full:min +full:- +full:len
1 // SPDX-License-Identifier: GPL-2.0+
15 // Based on code from U-Boot bootloader by:
18 // Based on spi-stmp.c, which is:
28 #include <linux/dma-mapping.h>
40 #include <linux/spi/mxs-spi.h>
42 #include <linux/dma/mxs-dma.h>
44 #define DRIVER_NAME "mxs-spi"
56 #define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
67 struct mxs_spi *spi = spi_controller_get_devdata(dev->controller); in mxs_spi_setup_transfer()
68 struct mxs_ssp *ssp = &spi->ssp; in mxs_spi_setup_transfer()
69 const unsigned int hz = min(dev->max_speed_hz, t->speed_hz); in mxs_spi_setup_transfer()
72 dev_err(&dev->dev, "SPI clock rate of zero not allowed\n"); in mxs_spi_setup_transfer()
73 return -EINVAL; in mxs_spi_setup_transfer()
76 if (hz != spi->sck) { in mxs_spi_setup_transfer()
80 * ssp->clk_rate. Otherwise we would set the rate every transfer in mxs_spi_setup_transfer()
83 spi->sck = hz; in mxs_spi_setup_transfer()
91 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_setup_transfer()
95 ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) | in mxs_spi_setup_transfer()
96 ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0), in mxs_spi_setup_transfer()
97 ssp->base + HW_SSP_CTRL1(ssp)); in mxs_spi_setup_transfer()
99 writel(0x0, ssp->base + HW_SSP_CMD0); in mxs_spi_setup_transfer()
100 writel(0x0, ssp->base + HW_SSP_CMD1); in mxs_spi_setup_transfer()
115 * toggle the chip-select lines (nCS pins). in mxs_spi_cs_to_reg()
128 struct mxs_ssp *ssp = &spi->ssp; in mxs_ssp_wait()
132 reg = readl_relaxed(ssp->base + offset); in mxs_ssp_wait()
143 return -ETIMEDOUT; in mxs_ssp_wait()
150 complete(&spi->c); in mxs_ssp_dma_irq_callback()
157 dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n", in mxs_ssp_irq_handler()
159 readl(ssp->base + HW_SSP_CTRL1(ssp)), in mxs_ssp_irq_handler()
160 readl(ssp->base + HW_SSP_STATUS(ssp))); in mxs_ssp_irq_handler()
165 unsigned char *buf, int len, in mxs_spi_txrx_dma() argument
168 struct mxs_ssp *ssp = &spi->ssp; in mxs_spi_txrx_dma()
172 const int sgs = DIV_ROUND_UP(len, desc_len); in mxs_spi_txrx_dma()
174 int min, ret; in mxs_spi_txrx_dma() local
182 if (!len) in mxs_spi_txrx_dma()
183 return -EINVAL; in mxs_spi_txrx_dma()
187 return -ENOMEM; in mxs_spi_txrx_dma()
189 reinit_completion(&spi->c); in mxs_spi_txrx_dma()
192 ctrl0 = readl(ssp->base + HW_SSP_CTRL0); in mxs_spi_txrx_dma()
203 min = min(len, desc_len); in mxs_spi_txrx_dma()
206 * De-assert CS on last segment if flag is set (i.e., no more in mxs_spi_txrx_dma()
212 if (ssp->devid == IMX23_SSP) { in mxs_spi_txrx_dma()
214 ctrl0 |= min; in mxs_spi_txrx_dma()
218 dma_xfer[sg_count].pio[3] = min; in mxs_spi_txrx_dma()
223 ret = -ENOMEM; in mxs_spi_txrx_dma()
229 min, offset_in_page(buf)); in mxs_spi_txrx_dma()
231 sg_init_one(&dma_xfer[sg_count].sg, buf, min); in mxs_spi_txrx_dma()
234 ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1, in mxs_spi_txrx_dma()
237 len -= min; in mxs_spi_txrx_dma()
238 buf += min; in mxs_spi_txrx_dma()
241 desc = dmaengine_prep_slave_sg(ssp->dmach, in mxs_spi_txrx_dma()
243 (ssp->devid == IMX23_SSP) ? 1 : 4, in mxs_spi_txrx_dma()
247 dev_err(ssp->dev, in mxs_spi_txrx_dma()
249 ret = -EINVAL; in mxs_spi_txrx_dma()
253 desc = dmaengine_prep_slave_sg(ssp->dmach, in mxs_spi_txrx_dma()
259 dev_err(ssp->dev, in mxs_spi_txrx_dma()
261 ret = -EINVAL; in mxs_spi_txrx_dma()
270 desc->callback = mxs_ssp_dma_irq_callback; in mxs_spi_txrx_dma()
271 desc->callback_param = spi; in mxs_spi_txrx_dma()
275 dma_async_issue_pending(ssp->dmach); in mxs_spi_txrx_dma()
277 if (!wait_for_completion_timeout(&spi->c, in mxs_spi_txrx_dma()
279 dev_err(ssp->dev, "DMA transfer timeout\n"); in mxs_spi_txrx_dma()
280 ret = -ETIMEDOUT; in mxs_spi_txrx_dma()
281 dmaengine_terminate_all(ssp->dmach); in mxs_spi_txrx_dma()
288 while (--sg_count >= 0) { in mxs_spi_txrx_dma()
290 dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1, in mxs_spi_txrx_dma()
300 unsigned char *buf, int len, in mxs_spi_txrx_pio() argument
303 struct mxs_ssp *ssp = &spi->ssp; in mxs_spi_txrx_pio()
306 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_txrx_pio()
308 while (len--) { in mxs_spi_txrx_pio()
309 if (len == 0 && (flags & TXRX_DEASSERT_CS)) in mxs_spi_txrx_pio()
311 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()
313 if (ssp->devid == IMX23_SSP) { in mxs_spi_txrx_pio()
315 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_txrx_pio()
317 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()
319 writel(1, ssp->base + HW_SSP_XFER_SIZE); in mxs_spi_txrx_pio()
324 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_txrx_pio()
327 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()
330 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()
333 return -ETIMEDOUT; in mxs_spi_txrx_pio()
336 writel(*buf, ssp->base + HW_SSP_DATA(ssp)); in mxs_spi_txrx_pio()
339 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()
344 return -ETIMEDOUT; in mxs_spi_txrx_pio()
346 *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff); in mxs_spi_txrx_pio()
350 return -ETIMEDOUT; in mxs_spi_txrx_pio()
355 if (len <= 0) in mxs_spi_txrx_pio()
358 return -ETIMEDOUT; in mxs_spi_txrx_pio()
365 struct mxs_ssp *ssp = &spi->ssp; in mxs_spi_transfer_one()
372 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_transfer_one()
373 writel(mxs_spi_cs_to_reg(spi_get_chipselect(m->spi, 0)), in mxs_spi_transfer_one()
374 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_transfer_one()
376 list_for_each_entry(t, &m->transfers, transfer_list) { in mxs_spi_transfer_one()
380 status = mxs_spi_setup_transfer(m->spi, t); in mxs_spi_transfer_one()
384 t->effective_speed_hz = ssp->clk_rate; in mxs_spi_transfer_one()
386 /* De-assert on last transfer, inverted by cs_change flag */ in mxs_spi_transfer_one()
387 flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ? in mxs_spi_transfer_one()
399 if (t->len < 32) { in mxs_spi_transfer_one()
401 ssp->base + HW_SSP_CTRL1(ssp) + in mxs_spi_transfer_one()
404 if (t->tx_buf) in mxs_spi_transfer_one()
406 (void *)t->tx_buf, in mxs_spi_transfer_one()
407 t->len, flag | TXRX_WRITE); in mxs_spi_transfer_one()
408 if (t->rx_buf) in mxs_spi_transfer_one()
410 t->rx_buf, t->len, in mxs_spi_transfer_one()
414 ssp->base + HW_SSP_CTRL1(ssp) + in mxs_spi_transfer_one()
417 if (t->tx_buf) in mxs_spi_transfer_one()
419 (void *)t->tx_buf, t->len, in mxs_spi_transfer_one()
421 if (t->rx_buf) in mxs_spi_transfer_one()
423 t->rx_buf, t->len, in mxs_spi_transfer_one()
430 stmp_reset_block(ssp->base); in mxs_spi_transfer_one()
434 m->actual_length += t->len; in mxs_spi_transfer_one()
437 m->status = status; in mxs_spi_transfer_one()
447 struct mxs_ssp *ssp = &spi->ssp; in mxs_spi_runtime_suspend()
450 clk_disable_unprepare(ssp->clk); in mxs_spi_runtime_suspend()
454 int ret2 = clk_prepare_enable(ssp->clk); in mxs_spi_runtime_suspend()
468 struct mxs_ssp *ssp = &spi->ssp; in mxs_spi_runtime_resume()
475 ret = clk_prepare_enable(ssp->clk); in mxs_spi_runtime_resume()
522 { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
523 { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
531 of_match_device(mxs_spi_dt_ids, &pdev->dev); in mxs_spi_probe()
532 struct device_node *np = pdev->dev.of_node; in mxs_spi_probe()
544 * as a default. Override with "clock-frequency" DT prop. in mxs_spi_probe()
556 clk = devm_clk_get(&pdev->dev, NULL); in mxs_spi_probe()
560 devid = (enum mxs_ssp_id) of_id->data; in mxs_spi_probe()
561 ret = of_property_read_u32(np, "clock-frequency", in mxs_spi_probe()
566 host = spi_alloc_host(&pdev->dev, sizeof(*spi)); in mxs_spi_probe()
568 return -ENOMEM; in mxs_spi_probe()
572 host->transfer_one_message = mxs_spi_transfer_one; in mxs_spi_probe()
573 host->bits_per_word_mask = SPI_BPW_MASK(8); in mxs_spi_probe()
574 host->mode_bits = SPI_CPOL | SPI_CPHA; in mxs_spi_probe()
575 host->num_chipselect = 3; in mxs_spi_probe()
576 host->dev.of_node = np; in mxs_spi_probe()
577 host->flags = SPI_CONTROLLER_HALF_DUPLEX; in mxs_spi_probe()
578 host->auto_runtime_pm = true; in mxs_spi_probe()
581 ssp = &spi->ssp; in mxs_spi_probe()
582 ssp->dev = &pdev->dev; in mxs_spi_probe()
583 ssp->clk = clk; in mxs_spi_probe()
584 ssp->base = base; in mxs_spi_probe()
585 ssp->devid = devid; in mxs_spi_probe()
587 init_completion(&spi->c); in mxs_spi_probe()
589 ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0, in mxs_spi_probe()
590 dev_name(&pdev->dev), ssp); in mxs_spi_probe()
594 ssp->dmach = dma_request_chan(&pdev->dev, "rx-tx"); in mxs_spi_probe()
595 if (IS_ERR(ssp->dmach)) { in mxs_spi_probe()
596 dev_err(ssp->dev, "Failed to request DMA\n"); in mxs_spi_probe()
597 ret = PTR_ERR(ssp->dmach); in mxs_spi_probe()
601 pm_runtime_enable(ssp->dev); in mxs_spi_probe()
602 if (!pm_runtime_enabled(ssp->dev)) { in mxs_spi_probe()
603 ret = mxs_spi_runtime_resume(ssp->dev); in mxs_spi_probe()
605 dev_err(ssp->dev, "runtime resume failed\n"); in mxs_spi_probe()
610 ret = pm_runtime_resume_and_get(ssp->dev); in mxs_spi_probe()
612 dev_err(ssp->dev, "runtime_get_sync failed\n"); in mxs_spi_probe()
616 clk_set_rate(ssp->clk, clk_freq); in mxs_spi_probe()
618 ret = stmp_reset_block(ssp->base); in mxs_spi_probe()
622 ret = devm_spi_register_controller(&pdev->dev, host); in mxs_spi_probe()
624 dev_err(&pdev->dev, "Cannot register SPI host, %d\n", ret); in mxs_spi_probe()
628 pm_runtime_put(ssp->dev); in mxs_spi_probe()
633 pm_runtime_put(ssp->dev); in mxs_spi_probe()
635 pm_runtime_disable(ssp->dev); in mxs_spi_probe()
637 dma_release_channel(ssp->dmach); in mxs_spi_probe()
651 ssp = &spi->ssp; in mxs_spi_remove()
653 pm_runtime_disable(&pdev->dev); in mxs_spi_remove()
654 if (!pm_runtime_status_suspended(&pdev->dev)) in mxs_spi_remove()
655 mxs_spi_runtime_suspend(&pdev->dev); in mxs_spi_remove()
657 dma_release_channel(ssp->dmach); in mxs_spi_remove()
675 MODULE_ALIAS("platform:mxs-spi");