1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/mtd/nand.h>
16 #include <linux/mtd/nand-ecc-mxic.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/spi-mem.h>
74 #define OP_CMD_BYTES(x)		(((x) - 1) << 13)
195 	ret = clk_prepare_enable(mxic->send_clk);  in mxic_spi_clk_enable()
199 	ret = clk_prepare_enable(mxic->send_dly_clk);  in mxic_spi_clk_enable()
206 	clk_disable_unprepare(mxic->send_clk);  in mxic_spi_clk_enable()
213 	clk_disable_unprepare(mxic->send_clk);  in mxic_spi_clk_disable()
214 	clk_disable_unprepare(mxic->send_dly_clk);  in mxic_spi_clk_disable()
223 	       mxic->regs + IDLY_CODE(0));  in mxic_spi_set_input_delay_dqs()
228 	       mxic->regs + IDLY_CODE(1));  in mxic_spi_set_input_delay_dqs()
235 	ret = clk_set_rate(mxic->send_clk, freq);  in mxic_spi_clk_setup()
239 	ret = clk_set_rate(mxic->send_dly_clk, freq);  in mxic_spi_clk_setup()
250 	 * Phase degree = 360 * freq * output-delay  in mxic_spi_clk_setup()
251 	 * where output-delay is a constant value 1 ns in FPGA.  in mxic_spi_clk_setup()
257 	ret = clk_set_phase(mxic->send_dly_clk, 9 * freq / 25000000);  in mxic_spi_clk_setup()
268 	if (mxic->cur_speed_hz == freq)  in mxic_spi_set_freq()
280 	mxic->cur_speed_hz = freq;  in mxic_spi_set_freq()
287 	writel(0, mxic->regs + DATA_STROB);  in mxic_spi_hw_init()
288 	writel(INT_STS_ALL, mxic->regs + INT_STS_EN);  in mxic_spi_hw_init()
289 	writel(0, mxic->regs + HC_EN);  in mxic_spi_hw_init()
290 	writel(0, mxic->regs + LRD_CFG);  in mxic_spi_hw_init()
291 	writel(0, mxic->regs + LRD_CTRL);  in mxic_spi_hw_init()
294 	       mxic->regs + HC_CFG);  in mxic_spi_hw_init()
297 static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags,  in mxic_spi_prep_hc_cfg()  argument
302 	if (spi->mode & (SPI_TX_OCTAL | SPI_RX_OCTAL))  in mxic_spi_prep_hc_cfg()
304 	else if (spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))  in mxic_spi_prep_hc_cfg()
306 	else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))  in mxic_spi_prep_hc_cfg()
315 	       HC_CFG_TYPE(spi_get_chipselect(spi, 0), HC_CFG_TYPE_SPI_NOR) |  in mxic_spi_prep_hc_cfg()
316 	       HC_CFG_SLV_ACT(spi_get_chipselect(spi, 0)) | HC_CFG_IDLE_SIO_LVL(1);  in mxic_spi_prep_hc_cfg()
322 	u32 cfg = OP_CMD_BYTES(op->cmd.nbytes) |  in mxic_spi_mem_prep_op_cfg()
323 		  OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) |  in mxic_spi_mem_prep_op_cfg()
324 		  (op->cmd.dtr ? OP_CMD_DDR : 0);  in mxic_spi_mem_prep_op_cfg()
326 	if (op->addr.nbytes)  in mxic_spi_mem_prep_op_cfg()
327 		cfg |= OP_ADDR_BYTES(op->addr.nbytes) |  in mxic_spi_mem_prep_op_cfg()
328 		       OP_ADDR_BUSW(fls(op->addr.buswidth) - 1) |  in mxic_spi_mem_prep_op_cfg()
329 		       (op->addr.dtr ? OP_ADDR_DDR : 0);  in mxic_spi_mem_prep_op_cfg()
331 	if (op->dummy.nbytes)  in mxic_spi_mem_prep_op_cfg()
332 		cfg |= OP_DUMMY_CYC(op->dummy.nbytes);  in mxic_spi_mem_prep_op_cfg()
336 		cfg |= OP_DATA_BUSW(fls(op->data.buswidth) - 1) |  in mxic_spi_mem_prep_op_cfg()
337 		       (op->data.dtr ? OP_DATA_DDR : 0);  in mxic_spi_mem_prep_op_cfg()
338 		if (op->data.dir == SPI_MEM_DATA_IN) {  in mxic_spi_mem_prep_op_cfg()
340 			if (op->data.dtr)  in mxic_spi_mem_prep_op_cfg()
354 		unsigned int nbytes = len - pos;  in mxic_spi_data_xfer()
365 		ret = readl_poll_timeout(mxic->regs + INT_STS, sts,  in mxic_spi_data_xfer()
370 		writel(data, mxic->regs + TXD(nbytes % 4));  in mxic_spi_data_xfer()
372 		ret = readl_poll_timeout(mxic->regs + INT_STS, sts,  in mxic_spi_data_xfer()
377 		ret = readl_poll_timeout(mxic->regs + INT_STS, sts,  in mxic_spi_data_xfer()
383 		data = readl(mxic->regs + RXD);  in mxic_spi_data_xfer()
385 			data >>= (8 * (4 - nbytes));  in mxic_spi_data_xfer()
388 		WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);  in mxic_spi_data_xfer()
399 	struct mxic_spi *mxic = spi_controller_get_devdata(desc->mem->spi->controller);  in mxic_spi_mem_dirmap_read()
403 	if (WARN_ON(offs + desc->info.offset + len > U32_MAX))  in mxic_spi_mem_dirmap_read()
404 		return -EINVAL;  in mxic_spi_mem_dirmap_read()
406 	writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16),  in mxic_spi_mem_dirmap_read()
407 	       mxic->regs + HC_CFG);  in mxic_spi_mem_dirmap_read()
409 	writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),  in mxic_spi_mem_dirmap_read()
410 	       mxic->regs + LRD_CFG);  in mxic_spi_mem_dirmap_read()
411 	writel(desc->info.offset + offs, mxic->regs + LRD_ADDR);  in mxic_spi_mem_dirmap_read()
412 	len = min_t(size_t, len, mxic->linear.size);  in mxic_spi_mem_dirmap_read()
413 	writel(len, mxic->regs + LRD_RANGE);  in mxic_spi_mem_dirmap_read()
414 	writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |  in mxic_spi_mem_dirmap_read()
415 	       LMODE_SLV_ACT(spi_get_chipselect(desc->mem->spi, 0)) |  in mxic_spi_mem_dirmap_read()
417 	       mxic->regs + LRD_CTRL);  in mxic_spi_mem_dirmap_read()
419 	if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.data.ecc) {  in mxic_spi_mem_dirmap_read()
420 		ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine,  in mxic_spi_mem_dirmap_read()
422 						      mxic->linear.dma + offs);  in mxic_spi_mem_dirmap_read()
426 		memcpy_fromio(buf, mxic->linear.map, len);  in mxic_spi_mem_dirmap_read()
429 	writel(INT_LRD_DIS, mxic->regs + INT_STS);  in mxic_spi_mem_dirmap_read()
430 	writel(0, mxic->regs + LRD_CTRL);  in mxic_spi_mem_dirmap_read()
432 	ret = readl_poll_timeout(mxic->regs + INT_STS, sts,  in mxic_spi_mem_dirmap_read()
444 	struct mxic_spi *mxic = spi_controller_get_devdata(desc->mem->spi->controller);  in mxic_spi_mem_dirmap_write()
448 	if (WARN_ON(offs + desc->info.offset + len > U32_MAX))  in mxic_spi_mem_dirmap_write()
449 		return -EINVAL;  in mxic_spi_mem_dirmap_write()
451 	writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16),  in mxic_spi_mem_dirmap_write()
452 	       mxic->regs + HC_CFG);  in mxic_spi_mem_dirmap_write()
454 	writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),  in mxic_spi_mem_dirmap_write()
455 	       mxic->regs + LWR_CFG);  in mxic_spi_mem_dirmap_write()
456 	writel(desc->info.offset + offs, mxic->regs + LWR_ADDR);  in mxic_spi_mem_dirmap_write()
457 	len = min_t(size_t, len, mxic->linear.size);  in mxic_spi_mem_dirmap_write()
458 	writel(len, mxic->regs + LWR_RANGE);  in mxic_spi_mem_dirmap_write()
459 	writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |  in mxic_spi_mem_dirmap_write()
460 	       LMODE_SLV_ACT(spi_get_chipselect(desc->mem->spi, 0)) |  in mxic_spi_mem_dirmap_write()
462 	       mxic->regs + LWR_CTRL);  in mxic_spi_mem_dirmap_write()
464 	if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.data.ecc) {  in mxic_spi_mem_dirmap_write()
465 		ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine,  in mxic_spi_mem_dirmap_write()
467 						      mxic->linear.dma + offs);  in mxic_spi_mem_dirmap_write()
471 		memcpy_toio(mxic->linear.map, buf, len);  in mxic_spi_mem_dirmap_write()
474 	writel(INT_LWR_DIS, mxic->regs + INT_STS);  in mxic_spi_mem_dirmap_write()
475 	writel(0, mxic->regs + LWR_CTRL);  in mxic_spi_mem_dirmap_write()
477 	ret = readl_poll_timeout(mxic->regs + INT_STS, sts,  in mxic_spi_mem_dirmap_write()
488 	if (op->data.buswidth > 8 || op->addr.buswidth > 8 ||  in mxic_spi_mem_supports_op()
489 	    op->dummy.buswidth > 8 || op->cmd.buswidth > 8)  in mxic_spi_mem_supports_op()
492 	if (op->data.nbytes && op->dummy.nbytes &&  in mxic_spi_mem_supports_op()
493 	    op->data.buswidth != op->dummy.buswidth)  in mxic_spi_mem_supports_op()
496 	if (op->addr.nbytes > 7)  in mxic_spi_mem_supports_op()
504 	struct mxic_spi *mxic = spi_controller_get_devdata(desc->mem->spi->controller);  in mxic_spi_mem_dirmap_create()
506 	if (!mxic->linear.map)  in mxic_spi_mem_dirmap_create()
507 		return -EOPNOTSUPP;  in mxic_spi_mem_dirmap_create()
509 	if (desc->info.offset + desc->info.length > U32_MAX)  in mxic_spi_mem_dirmap_create()
510 		return -EINVAL;  in mxic_spi_mem_dirmap_create()
512 	if (!mxic_spi_mem_supports_op(desc->mem, &desc->info.op_tmpl))  in mxic_spi_mem_dirmap_create()
513 		return -EOPNOTSUPP;  in mxic_spi_mem_dirmap_create()
521 	struct mxic_spi *mxic = spi_controller_get_devdata(mem->spi->controller);  in mxic_spi_mem_exec_op()
525 	ret = mxic_spi_set_freq(mxic, op->max_freq);  in mxic_spi_mem_exec_op()
529 	writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN, op->data.swap16),  in mxic_spi_mem_exec_op()
530 	       mxic->regs + HC_CFG);  in mxic_spi_mem_exec_op()
532 	writel(HC_EN_BIT, mxic->regs + HC_EN);  in mxic_spi_mem_exec_op()
534 	writel(mxic_spi_mem_prep_op_cfg(op, op->data.nbytes),  in mxic_spi_mem_exec_op()
535 	       mxic->regs + SS_CTRL(spi_get_chipselect(mem->spi, 0)));  in mxic_spi_mem_exec_op()
537 	writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,  in mxic_spi_mem_exec_op()
538 	       mxic->regs + HC_CFG);  in mxic_spi_mem_exec_op()
540 	for (i = 0; i < op->cmd.nbytes; i++)  in mxic_spi_mem_exec_op()
541 		cmd[i] = op->cmd.opcode >> (8 * (op->cmd.nbytes - i - 1));  in mxic_spi_mem_exec_op()
543 	ret = mxic_spi_data_xfer(mxic, cmd, NULL, op->cmd.nbytes);  in mxic_spi_mem_exec_op()
547 	for (i = 0; i < op->addr.nbytes; i++)  in mxic_spi_mem_exec_op()
548 		addr[i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1));  in mxic_spi_mem_exec_op()
550 	ret = mxic_spi_data_xfer(mxic, addr, NULL, op->addr.nbytes);  in mxic_spi_mem_exec_op()
554 	ret = mxic_spi_data_xfer(mxic, NULL, NULL, op->dummy.nbytes);  in mxic_spi_mem_exec_op()
559 				 op->data.dir == SPI_MEM_DATA_OUT ?  in mxic_spi_mem_exec_op()
560 				 op->data.buf.out : NULL,  in mxic_spi_mem_exec_op()
561 				 op->data.dir == SPI_MEM_DATA_IN ?  in mxic_spi_mem_exec_op()
562 				 op->data.buf.in : NULL,  in mxic_spi_mem_exec_op()
563 				 op->data.nbytes);  in mxic_spi_mem_exec_op()
566 	writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,  in mxic_spi_mem_exec_op()
567 	       mxic->regs + HC_CFG);  in mxic_spi_mem_exec_op()
568 	writel(0, mxic->regs + HC_EN);  in mxic_spi_mem_exec_op()
588 static void mxic_spi_set_cs(struct spi_device *spi, bool lvl)  in mxic_spi_set_cs()  argument
590 	struct mxic_spi *mxic = spi_controller_get_devdata(spi->controller);  in mxic_spi_set_cs()
593 		writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_EN,  in mxic_spi_set_cs()
594 		       mxic->regs + HC_CFG);  in mxic_spi_set_cs()
595 		writel(HC_EN_BIT, mxic->regs + HC_EN);  in mxic_spi_set_cs()
596 		writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,  in mxic_spi_set_cs()
597 		       mxic->regs + HC_CFG);  in mxic_spi_set_cs()
599 		writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,  in mxic_spi_set_cs()
600 		       mxic->regs + HC_CFG);  in mxic_spi_set_cs()
601 		writel(0, mxic->regs + HC_EN);  in mxic_spi_set_cs()
606 				 struct spi_device *spi,  in mxic_spi_transfer_one()  argument
613 	if (t->rx_buf && t->tx_buf) {  in mxic_spi_transfer_one()
614 		if (((spi->mode & SPI_TX_QUAD) &&  in mxic_spi_transfer_one()
615 		     !(spi->mode & SPI_RX_QUAD)) ||  in mxic_spi_transfer_one()
616 		    ((spi->mode & SPI_TX_DUAL) &&  in mxic_spi_transfer_one()
617 		     !(spi->mode & SPI_RX_DUAL)))  in mxic_spi_transfer_one()
618 			return -ENOTSUPP;  in mxic_spi_transfer_one()
621 	ret = mxic_spi_set_freq(mxic, t->speed_hz);  in mxic_spi_transfer_one()
625 	if (t->tx_buf) {  in mxic_spi_transfer_one()
626 		if (spi->mode & SPI_TX_QUAD)  in mxic_spi_transfer_one()
628 		else if (spi->mode & SPI_TX_DUAL)  in mxic_spi_transfer_one()
630 	} else if (t->rx_buf) {  in mxic_spi_transfer_one()
631 		if (spi->mode & SPI_RX_QUAD)  in mxic_spi_transfer_one()
633 		else if (spi->mode & SPI_RX_DUAL)  in mxic_spi_transfer_one()
638 	       OP_DATA_BUSW(busw) | (t->rx_buf ? OP_READ : 0),  in mxic_spi_transfer_one()
639 	       mxic->regs + SS_CTRL(0));  in mxic_spi_transfer_one()
641 	ret = mxic_spi_data_xfer(mxic, t->tx_buf, t->rx_buf, t->len);  in mxic_spi_transfer_one()
651 static int mxic_spi_mem_ecc_init_ctx(struct nand_device *nand)  in mxic_spi_mem_ecc_init_ctx()  argument
654 	struct mxic_spi *mxic = nand->ecc.engine->priv;  in mxic_spi_mem_ecc_init_ctx()
656 	mxic->ecc.use_pipelined_conf = true;  in mxic_spi_mem_ecc_init_ctx()
658 	return ops->init_ctx(nand);  in mxic_spi_mem_ecc_init_ctx()
661 static void mxic_spi_mem_ecc_cleanup_ctx(struct nand_device *nand)  in mxic_spi_mem_ecc_cleanup_ctx()  argument
664 	struct mxic_spi *mxic = nand->ecc.engine->priv;  in mxic_spi_mem_ecc_cleanup_ctx()
666 	mxic->ecc.use_pipelined_conf = false;  in mxic_spi_mem_ecc_cleanup_ctx()
668 	ops->cleanup_ctx(nand);  in mxic_spi_mem_ecc_cleanup_ctx()
671 static int mxic_spi_mem_ecc_prepare_io_req(struct nand_device *nand,  in mxic_spi_mem_ecc_prepare_io_req()  argument
676 	return ops->prepare_io_req(nand, req);  in mxic_spi_mem_ecc_prepare_io_req()
679 static int mxic_spi_mem_ecc_finish_io_req(struct nand_device *nand,  in mxic_spi_mem_ecc_finish_io_req()  argument
684 	return ops->finish_io_req(nand, req);  in mxic_spi_mem_ecc_finish_io_req()
696 	if (mxic->ecc.pipelined_engine) {  in mxic_spi_mem_ecc_remove()
697 		mxic_ecc_put_pipelined_engine(mxic->ecc.pipelined_engine);  in mxic_spi_mem_ecc_remove()
698 		nand_ecc_unregister_on_host_hw_engine(mxic->ecc.pipelined_engine);  in mxic_spi_mem_ecc_remove()
708 		return -EOPNOTSUPP;  in mxic_spi_mem_ecc_probe()
714 	eng->dev = &pdev->dev;  in mxic_spi_mem_ecc_probe()
715 	eng->integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;  in mxic_spi_mem_ecc_probe()
716 	eng->ops = &mxic_spi_mem_ecc_engine_pipelined_ops;  in mxic_spi_mem_ecc_probe()
717 	eng->priv = mxic;  in mxic_spi_mem_ecc_probe()
718 	mxic->ecc.pipelined_engine = eng;  in mxic_spi_mem_ecc_probe()
730 	clk_disable_unprepare(mxic->ps_clk);  in mxic_spi_runtime_suspend()
741 	ret = clk_prepare_enable(mxic->ps_clk);  in mxic_spi_runtime_resume()
762 	host = devm_spi_alloc_host(&pdev->dev, sizeof(struct mxic_spi));  in mxic_spi_probe()
764 		return -ENOMEM;  in mxic_spi_probe()
769 	mxic->dev = &pdev->dev;  in mxic_spi_probe()
771 	host->dev.of_node = pdev->dev.of_node;  in mxic_spi_probe()
773 	mxic->ps_clk = devm_clk_get(&pdev->dev, "ps_clk");  in mxic_spi_probe()
774 	if (IS_ERR(mxic->ps_clk))  in mxic_spi_probe()
775 		return PTR_ERR(mxic->ps_clk);  in mxic_spi_probe()
777 	mxic->send_clk = devm_clk_get(&pdev->dev, "send_clk");  in mxic_spi_probe()
778 	if (IS_ERR(mxic->send_clk))  in mxic_spi_probe()
779 		return PTR_ERR(mxic->send_clk);  in mxic_spi_probe()
781 	mxic->send_dly_clk = devm_clk_get(&pdev->dev, "send_dly_clk");  in mxic_spi_probe()
782 	if (IS_ERR(mxic->send_dly_clk))  in mxic_spi_probe()
783 		return PTR_ERR(mxic->send_dly_clk);  in mxic_spi_probe()
785 	mxic->regs = devm_platform_ioremap_resource_byname(pdev, "regs");  in mxic_spi_probe()
786 	if (IS_ERR(mxic->regs))  in mxic_spi_probe()
787 		return PTR_ERR(mxic->regs);  in mxic_spi_probe()
790 	mxic->linear.map = devm_ioremap_resource(&pdev->dev, res);  in mxic_spi_probe()
791 	if (!IS_ERR(mxic->linear.map)) {  in mxic_spi_probe()
792 		mxic->linear.dma = res->start;  in mxic_spi_probe()
793 		mxic->linear.size = resource_size(res);  in mxic_spi_probe()
795 		mxic->linear.map = NULL;  in mxic_spi_probe()
798 	pm_runtime_enable(&pdev->dev);  in mxic_spi_probe()
799 	host->auto_runtime_pm = true;  in mxic_spi_probe()
801 	host->num_chipselect = 1;  in mxic_spi_probe()
802 	host->mem_ops = &mxic_spi_mem_ops;  in mxic_spi_probe()
803 	host->mem_caps = &mxic_spi_mem_caps;  in mxic_spi_probe()
805 	host->set_cs = mxic_spi_set_cs;  in mxic_spi_probe()
806 	host->transfer_one = mxic_spi_transfer_one;  in mxic_spi_probe()
807 	host->bits_per_word_mask = SPI_BPW_MASK(8);  in mxic_spi_probe()
808 	host->mode_bits = SPI_CPOL | SPI_CPHA |  in mxic_spi_probe()
816 	if (ret == -EPROBE_DEFER) {  in mxic_spi_probe()
817 		pm_runtime_disable(&pdev->dev);  in mxic_spi_probe()
823 		dev_err(&pdev->dev, "spi_register_controller failed\n");  in mxic_spi_probe()
824 		pm_runtime_disable(&pdev->dev);  in mxic_spi_probe()
836 	pm_runtime_disable(&pdev->dev);  in mxic_spi_remove()
842 	{ .compatible = "mxicy,mx25f0a-spi", },
851 		.name = "mxic-spi",
859 MODULE_DESCRIPTION("MX25F0A SPI controller driver");