Lines Matching full:mxic
6 // Mason Yang <masonccyang@mxic.com.tw>
7 // zhengxunli <zhengxunli@mxic.com.tw>
16 #include <linux/mtd/nand-ecc-mxic.h>
191 static int mxic_spi_clk_enable(struct mxic_spi *mxic) in mxic_spi_clk_enable() argument
195 ret = clk_prepare_enable(mxic->send_clk); in mxic_spi_clk_enable()
199 ret = clk_prepare_enable(mxic->send_dly_clk); in mxic_spi_clk_enable()
206 clk_disable_unprepare(mxic->send_clk); in mxic_spi_clk_enable()
211 static void mxic_spi_clk_disable(struct mxic_spi *mxic) in mxic_spi_clk_disable() argument
213 clk_disable_unprepare(mxic->send_clk); in mxic_spi_clk_disable()
214 clk_disable_unprepare(mxic->send_dly_clk); in mxic_spi_clk_disable()
217 static void mxic_spi_set_input_delay_dqs(struct mxic_spi *mxic, u8 idly_code) in mxic_spi_set_input_delay_dqs() argument
223 mxic->regs + IDLY_CODE(0)); in mxic_spi_set_input_delay_dqs()
228 mxic->regs + IDLY_CODE(1)); in mxic_spi_set_input_delay_dqs()
231 static int mxic_spi_clk_setup(struct mxic_spi *mxic, unsigned long freq) in mxic_spi_clk_setup() argument
235 ret = clk_set_rate(mxic->send_clk, freq); in mxic_spi_clk_setup()
239 ret = clk_set_rate(mxic->send_dly_clk, freq); in mxic_spi_clk_setup()
247 mxic_spi_set_input_delay_dqs(mxic, 0xf); in mxic_spi_clk_setup()
257 ret = clk_set_phase(mxic->send_dly_clk, 9 * freq / 25000000); in mxic_spi_clk_setup()
264 static int mxic_spi_set_freq(struct mxic_spi *mxic, unsigned long freq) in mxic_spi_set_freq() argument
268 if (mxic->cur_speed_hz == freq) in mxic_spi_set_freq()
271 mxic_spi_clk_disable(mxic); in mxic_spi_set_freq()
272 ret = mxic_spi_clk_setup(mxic, freq); in mxic_spi_set_freq()
276 ret = mxic_spi_clk_enable(mxic); in mxic_spi_set_freq()
280 mxic->cur_speed_hz = freq; in mxic_spi_set_freq()
285 static void mxic_spi_hw_init(struct mxic_spi *mxic) in mxic_spi_hw_init() argument
287 writel(0, mxic->regs + DATA_STROB); in mxic_spi_hw_init()
288 writel(INT_STS_ALL, mxic->regs + INT_STS_EN); in mxic_spi_hw_init()
289 writel(0, mxic->regs + HC_EN); in mxic_spi_hw_init()
290 writel(0, mxic->regs + LRD_CFG); in mxic_spi_hw_init()
291 writel(0, mxic->regs + LRD_CTRL); in mxic_spi_hw_init()
294 mxic->regs + HC_CFG); in mxic_spi_hw_init()
348 static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, in mxic_spi_data_xfer() argument
365 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, in mxic_spi_data_xfer()
370 writel(data, mxic->regs + TXD(nbytes % 4)); in mxic_spi_data_xfer()
372 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, in mxic_spi_data_xfer()
377 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, in mxic_spi_data_xfer()
383 data = readl(mxic->regs + RXD); in mxic_spi_data_xfer()
388 WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY); in mxic_spi_data_xfer()
399 struct mxic_spi *mxic = spi_controller_get_devdata(desc->mem->spi->controller); in mxic_spi_mem_dirmap_read() local
407 mxic->regs + HC_CFG); in mxic_spi_mem_dirmap_read()
410 mxic->regs + LRD_CFG); in mxic_spi_mem_dirmap_read()
411 writel(desc->info.offset + offs, mxic->regs + LRD_ADDR); in mxic_spi_mem_dirmap_read()
412 len = min_t(size_t, len, mxic->linear.size); in mxic_spi_mem_dirmap_read()
413 writel(len, mxic->regs + LRD_RANGE); in mxic_spi_mem_dirmap_read()
417 mxic->regs + LRD_CTRL); in mxic_spi_mem_dirmap_read()
419 if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.data.ecc) { in mxic_spi_mem_dirmap_read()
420 ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine, in mxic_spi_mem_dirmap_read()
422 mxic->linear.dma + offs); in mxic_spi_mem_dirmap_read()
426 memcpy_fromio(buf, mxic->linear.map, len); in mxic_spi_mem_dirmap_read()
429 writel(INT_LRD_DIS, mxic->regs + INT_STS); in mxic_spi_mem_dirmap_read()
430 writel(0, mxic->regs + LRD_CTRL); in mxic_spi_mem_dirmap_read()
432 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, in mxic_spi_mem_dirmap_read()
444 struct mxic_spi *mxic = spi_controller_get_devdata(desc->mem->spi->controller); in mxic_spi_mem_dirmap_write() local
452 mxic->regs + HC_CFG); in mxic_spi_mem_dirmap_write()
455 mxic->regs + LWR_CFG); in mxic_spi_mem_dirmap_write()
456 writel(desc->info.offset + offs, mxic->regs + LWR_ADDR); in mxic_spi_mem_dirmap_write()
457 len = min_t(size_t, len, mxic->linear.size); in mxic_spi_mem_dirmap_write()
458 writel(len, mxic->regs + LWR_RANGE); in mxic_spi_mem_dirmap_write()
462 mxic->regs + LWR_CTRL); in mxic_spi_mem_dirmap_write()
464 if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.data.ecc) { in mxic_spi_mem_dirmap_write()
465 ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine, in mxic_spi_mem_dirmap_write()
467 mxic->linear.dma + offs); in mxic_spi_mem_dirmap_write()
471 memcpy_toio(mxic->linear.map, buf, len); in mxic_spi_mem_dirmap_write()
474 writel(INT_LWR_DIS, mxic->regs + INT_STS); in mxic_spi_mem_dirmap_write()
475 writel(0, mxic->regs + LWR_CTRL); in mxic_spi_mem_dirmap_write()
477 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, in mxic_spi_mem_dirmap_write()
504 struct mxic_spi *mxic = spi_controller_get_devdata(desc->mem->spi->controller); in mxic_spi_mem_dirmap_create() local
506 if (!mxic->linear.map) in mxic_spi_mem_dirmap_create()
521 struct mxic_spi *mxic = spi_controller_get_devdata(mem->spi->controller); in mxic_spi_mem_exec_op() local
525 ret = mxic_spi_set_freq(mxic, op->max_freq); in mxic_spi_mem_exec_op()
530 mxic->regs + HC_CFG); in mxic_spi_mem_exec_op()
532 writel(HC_EN_BIT, mxic->regs + HC_EN); in mxic_spi_mem_exec_op()
535 mxic->regs + SS_CTRL(spi_get_chipselect(mem->spi, 0))); in mxic_spi_mem_exec_op()
537 writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, in mxic_spi_mem_exec_op()
538 mxic->regs + HC_CFG); in mxic_spi_mem_exec_op()
543 ret = mxic_spi_data_xfer(mxic, cmd, NULL, op->cmd.nbytes); in mxic_spi_mem_exec_op()
550 ret = mxic_spi_data_xfer(mxic, addr, NULL, op->addr.nbytes); in mxic_spi_mem_exec_op()
554 ret = mxic_spi_data_xfer(mxic, NULL, NULL, op->dummy.nbytes); in mxic_spi_mem_exec_op()
558 ret = mxic_spi_data_xfer(mxic, in mxic_spi_mem_exec_op()
566 writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT, in mxic_spi_mem_exec_op()
567 mxic->regs + HC_CFG); in mxic_spi_mem_exec_op()
568 writel(0, mxic->regs + HC_EN); in mxic_spi_mem_exec_op()
590 struct mxic_spi *mxic = spi_controller_get_devdata(spi->controller); in mxic_spi_set_cs() local
593 writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_EN, in mxic_spi_set_cs()
594 mxic->regs + HC_CFG); in mxic_spi_set_cs()
595 writel(HC_EN_BIT, mxic->regs + HC_EN); in mxic_spi_set_cs()
596 writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, in mxic_spi_set_cs()
597 mxic->regs + HC_CFG); in mxic_spi_set_cs()
599 writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT, in mxic_spi_set_cs()
600 mxic->regs + HC_CFG); in mxic_spi_set_cs()
601 writel(0, mxic->regs + HC_EN); in mxic_spi_set_cs()
609 struct mxic_spi *mxic = spi_controller_get_devdata(host); in mxic_spi_transfer_one() local
621 ret = mxic_spi_set_freq(mxic, t->speed_hz); in mxic_spi_transfer_one()
639 mxic->regs + SS_CTRL(0)); in mxic_spi_transfer_one()
641 ret = mxic_spi_data_xfer(mxic, t->tx_buf, t->rx_buf, t->len); in mxic_spi_transfer_one()
654 struct mxic_spi *mxic = nand->ecc.engine->priv; in mxic_spi_mem_ecc_init_ctx() local
656 mxic->ecc.use_pipelined_conf = true; in mxic_spi_mem_ecc_init_ctx()
664 struct mxic_spi *mxic = nand->ecc.engine->priv; in mxic_spi_mem_ecc_cleanup_ctx() local
666 mxic->ecc.use_pipelined_conf = false; in mxic_spi_mem_ecc_cleanup_ctx()
694 static void mxic_spi_mem_ecc_remove(struct mxic_spi *mxic) in mxic_spi_mem_ecc_remove() argument
696 if (mxic->ecc.pipelined_engine) { in mxic_spi_mem_ecc_remove()
697 mxic_ecc_put_pipelined_engine(mxic->ecc.pipelined_engine); in mxic_spi_mem_ecc_remove()
698 nand_ecc_unregister_on_host_hw_engine(mxic->ecc.pipelined_engine); in mxic_spi_mem_ecc_remove()
703 struct mxic_spi *mxic) in mxic_spi_mem_ecc_probe() argument
717 eng->priv = mxic; in mxic_spi_mem_ecc_probe()
718 mxic->ecc.pipelined_engine = eng; in mxic_spi_mem_ecc_probe()
727 struct mxic_spi *mxic = spi_controller_get_devdata(host); in mxic_spi_runtime_suspend() local
729 mxic_spi_clk_disable(mxic); in mxic_spi_runtime_suspend()
730 clk_disable_unprepare(mxic->ps_clk); in mxic_spi_runtime_suspend()
738 struct mxic_spi *mxic = spi_controller_get_devdata(host); in mxic_spi_runtime_resume() local
741 ret = clk_prepare_enable(mxic->ps_clk); in mxic_spi_runtime_resume()
747 return mxic_spi_clk_enable(mxic); in mxic_spi_runtime_resume()
759 struct mxic_spi *mxic; in mxic_spi_probe() local
768 mxic = spi_controller_get_devdata(host); in mxic_spi_probe()
769 mxic->dev = &pdev->dev; in mxic_spi_probe()
773 mxic->ps_clk = devm_clk_get(&pdev->dev, "ps_clk"); in mxic_spi_probe()
774 if (IS_ERR(mxic->ps_clk)) in mxic_spi_probe()
775 return PTR_ERR(mxic->ps_clk); in mxic_spi_probe()
777 mxic->send_clk = devm_clk_get(&pdev->dev, "send_clk"); in mxic_spi_probe()
778 if (IS_ERR(mxic->send_clk)) in mxic_spi_probe()
779 return PTR_ERR(mxic->send_clk); in mxic_spi_probe()
781 mxic->send_dly_clk = devm_clk_get(&pdev->dev, "send_dly_clk"); in mxic_spi_probe()
782 if (IS_ERR(mxic->send_dly_clk)) in mxic_spi_probe()
783 return PTR_ERR(mxic->send_dly_clk); in mxic_spi_probe()
785 mxic->regs = devm_platform_ioremap_resource_byname(pdev, "regs"); in mxic_spi_probe()
786 if (IS_ERR(mxic->regs)) in mxic_spi_probe()
787 return PTR_ERR(mxic->regs); in mxic_spi_probe()
790 mxic->linear.map = devm_ioremap_resource(&pdev->dev, res); in mxic_spi_probe()
791 if (!IS_ERR(mxic->linear.map)) { in mxic_spi_probe()
792 mxic->linear.dma = res->start; in mxic_spi_probe()
793 mxic->linear.size = resource_size(res); in mxic_spi_probe()
795 mxic->linear.map = NULL; in mxic_spi_probe()
813 mxic_spi_hw_init(mxic); in mxic_spi_probe()
815 ret = mxic_spi_mem_ecc_probe(pdev, mxic); in mxic_spi_probe()
825 mxic_spi_mem_ecc_remove(mxic); in mxic_spi_probe()
834 struct mxic_spi *mxic = spi_controller_get_devdata(host); in mxic_spi_remove() local
837 mxic_spi_mem_ecc_remove(mxic); in mxic_spi_remove()
851 .name = "mxic-spi",
858 MODULE_AUTHOR("Mason Yang <masonccyang@mxic.com.tw>");