1 // SPDX-License-Identifier: GPL-2.0-only
3 // Driver for Cadence QSPI Controller
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
30 #include <linux/spi/spi-mem.h>
33 #define CQSPI_NAME			"cadence-qspi"
40 #define CQSPI_DISABLE_DAC_MODE		BIT(1)
52 #define CQSPI_SUPPORTS_QUAD		BIT(1)
184 #define CQSPI_REG_READCAPTURE_DELAY_LSB		1
221 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK	BIT(1)
230 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK	BIT(1)
246 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK	BIT(1)
279 #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK	BIT(1)
288 #define CQSPI_REG_IRQ_UNDERFLOW			BIT(1)
321 		if (ret != -ETIMEDOUT)  in cqspi_wait_for_bit()
324 		timeout_us -= CQSPI_BUSYWAIT_TIMEOUT_US;  in cqspi_wait_for_bit()
334 	u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_is_idle()
336 	return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB);  in cqspi_is_idle()
341 	u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);  in cqspi_get_rd_sram_level()
351 	dma_status = readl(cqspi->iobase +  in cqspi_get_versal_dma_status()
353 	writel(dma_status, cqspi->iobase +  in cqspi_get_versal_dma_status()
362 	const struct cqspi_driver_platdata *ddata = cqspi->ddata;  in cqspi_irq_handler()
366 	irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);  in cqspi_irq_handler()
369 	writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);  in cqspi_irq_handler()
371 	if (cqspi->use_dma_read && ddata && ddata->get_dma_status) {  in cqspi_irq_handler()
372 		if (ddata->get_dma_status(cqspi)) {  in cqspi_irq_handler()
373 			complete(&cqspi->transfer_complete);  in cqspi_irq_handler()
378 	else if (!cqspi->slow_sram)  in cqspi_irq_handler()
384 		complete(&cqspi->transfer_complete);  in cqspi_irq_handler()
393 	rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;  in cqspi_calc_rdreg()
394 	rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;  in cqspi_calc_rdreg()
395 	rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;  in cqspi_calc_rdreg()
404 	if (!op->dummy.nbytes)  in cqspi_calc_dummy()
407 	dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);  in cqspi_calc_dummy()
408 	if (op->cmd.dtr)  in cqspi_calc_dummy()
421 	while (1) {  in cqspi_wait_idle()
437 			dev_err(&cqspi->pdev->dev,  in cqspi_wait_idle()
438 				"QSPI is still busy after %dms timeout.\n",  in cqspi_wait_idle()
440 			return -ETIMEDOUT;  in cqspi_wait_idle()
449 	void __iomem *reg_base = cqspi->iobase;  in cqspi_exec_flash_cmd()
459 	ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_CMDCTRL,  in cqspi_exec_flash_cmd()
460 				 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1, true);  in cqspi_exec_flash_cmd()
462 		dev_err(&cqspi->pdev->dev,  in cqspi_exec_flash_cmd()
467 	/* Polling QSPI idle status. */  in cqspi_exec_flash_cmd()
475 	struct cqspi_st *cqspi = f_pdata->cqspi;  in cqspi_setup_opcode_ext()
476 	void __iomem *reg_base = cqspi->iobase;  in cqspi_setup_opcode_ext()
480 	if (op->cmd.nbytes != 2)  in cqspi_setup_opcode_ext()
481 		return -EINVAL;  in cqspi_setup_opcode_ext()
484 	ext = op->cmd.opcode & 0xff;  in cqspi_setup_opcode_ext()
497 	struct cqspi_st *cqspi = f_pdata->cqspi;  in cqspi_enable_dtr()
498 	void __iomem *reg_base = cqspi->iobase;  in cqspi_enable_dtr()
508 	if (op->cmd.dtr) {  in cqspi_enable_dtr()
532 	struct cqspi_st *cqspi = f_pdata->cqspi;  in cqspi_command_read()
533 	void __iomem *reg_base = cqspi->iobase;  in cqspi_command_read()
534 	u8 *rxbuf = op->data.buf.in;  in cqspi_command_read()
536 	size_t n_rx = op->data.nbytes;  in cqspi_command_read()
548 		dev_err(&cqspi->pdev->dev,  in cqspi_command_read()
551 		return -EINVAL;  in cqspi_command_read()
554 	if (op->cmd.dtr)  in cqspi_command_read()
555 		opcode = op->cmd.opcode >> 8;  in cqspi_command_read()
557 		opcode = op->cmd.opcode;  in cqspi_command_read()
566 		return -EOPNOTSUPP;  in cqspi_command_read()
574 	/* 0 means 1 byte. */  in cqspi_command_read()
575 	reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)  in cqspi_command_read()
579 	if (op->addr.nbytes) {  in cqspi_command_read()
581 		reg |= ((op->addr.nbytes - 1) &  in cqspi_command_read()
585 		writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);  in cqspi_command_read()
602 		read_len = n_rx - read_len;  in cqspi_command_read()
615 	struct cqspi_st *cqspi = f_pdata->cqspi;  in cqspi_command_write()
616 	void __iomem *reg_base = cqspi->iobase;  in cqspi_command_write()
618 	const u8 *txbuf = op->data.buf.out;  in cqspi_command_write()
619 	size_t n_tx = op->data.nbytes;  in cqspi_command_write()
630 		dev_err(&cqspi->pdev->dev,  in cqspi_command_write()
633 		return -EINVAL;  in cqspi_command_write()
639 	if (op->cmd.dtr)  in cqspi_command_write()
640 		opcode = op->cmd.opcode >> 8;  in cqspi_command_write()
642 		opcode = op->cmd.opcode;  in cqspi_command_write()
646 	if (op->addr.nbytes) {  in cqspi_command_write()
648 		reg |= ((op->addr.nbytes - 1) &  in cqspi_command_write()
652 		writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);  in cqspi_command_write()
657 		reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)  in cqspi_command_write()
667 			write_len = n_tx - 4;  in cqspi_command_write()
684 	struct cqspi_st *cqspi = f_pdata->cqspi;  in cqspi_read_setup()
685 	void __iomem *reg_base = cqspi->iobase;  in cqspi_read_setup()
695 	if (op->cmd.dtr)  in cqspi_read_setup()
696 		opcode = op->cmd.opcode >> 8;  in cqspi_read_setup()
698 		opcode = op->cmd.opcode;  in cqspi_read_setup()
707 		return -EOPNOTSUPP;  in cqspi_read_setup()
718 	reg |= (op->addr.nbytes - 1);  in cqspi_read_setup()
727 	struct cqspi_st *cqspi = f_pdata->cqspi;  in cqspi_indirect_read_execute()
728 	bool use_irq = !(cqspi->ddata && cqspi->ddata->quirks & CQSPI_RD_NO_IRQ);  in cqspi_indirect_read_execute()
729 	struct device *dev = &cqspi->pdev->dev;  in cqspi_indirect_read_execute()
730 	void __iomem *reg_base = cqspi->iobase;  in cqspi_indirect_read_execute()
731 	void __iomem *ahb_base = cqspi->ahb_base;  in cqspi_indirect_read_execute()
752 	if (use_irq && cqspi->slow_sram)  in cqspi_indirect_read_execute()
759 	reinit_completion(&cqspi->transfer_complete);  in cqspi_indirect_read_execute()
765 		    !wait_for_completion_timeout(&cqspi->transfer_complete,  in cqspi_indirect_read_execute()
767 			ret = -ETIMEDOUT;  in cqspi_indirect_read_execute()
773 		if (cqspi->slow_sram)  in cqspi_indirect_read_execute()
786 			bytes_to_read *= cqspi->fifo_width;  in cqspi_indirect_read_execute()
799 							 (rxbuf_end - rxbuf),  in cqspi_indirect_read_execute()
803 			remaining -= bytes_to_read;  in cqspi_indirect_read_execute()
808 			reinit_completion(&cqspi->transfer_complete);  in cqspi_indirect_read_execute()
809 			if (cqspi->slow_sram)  in cqspi_indirect_read_execute()
815 	ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTRD,  in cqspi_indirect_read_execute()
844 	reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_device_reset()
846 	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_device_reset()
851 	writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_device_reset()
852 	usleep_range(1, 5);  in cqspi_device_reset()
853 	writel(reg | CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_device_reset()
855 	writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_device_reset()
861 	void __iomem *reg_base = cqspi->iobase;  in cqspi_controller_enable()
878 	struct cqspi_st *cqspi = f_pdata->cqspi;  in cqspi_versal_indirect_read_dma()
879 	struct device *dev = &cqspi->pdev->dev;  in cqspi_versal_indirect_read_dma()
880 	void __iomem *reg_base = cqspi->iobase;  in cqspi_versal_indirect_read_dma()
889 	bytes_to_dma = (n_rx - bytes_rem);  in cqspi_versal_indirect_read_dma()
894 	ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA);  in cqspi_versal_indirect_read_dma()
900 	reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_versal_indirect_read_dma()
902 	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_versal_indirect_read_dma()
904 	cqspi_controller_enable(cqspi, 1);  in cqspi_versal_indirect_read_dma()
909 		return -ENOMEM;  in cqspi_versal_indirect_read_dma()
934 	writel(cqspi->trigger_address, reg_base +  in cqspi_versal_indirect_read_dma()
947 	reinit_completion(&cqspi->transfer_complete);  in cqspi_versal_indirect_read_dma()
949 	if (!wait_for_completion_timeout(&cqspi->transfer_complete,  in cqspi_versal_indirect_read_dma()
951 		ret = -ETIMEDOUT;  in cqspi_versal_indirect_read_dma()
956 	writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS);  in cqspi_versal_indirect_read_dma()
960 	       cqspi->iobase + CQSPI_REG_INDIRECTRD);  in cqspi_versal_indirect_read_dma()
965 	reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_versal_indirect_read_dma()
967 	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_versal_indirect_read_dma()
969 	cqspi_controller_enable(cqspi, 1);  in cqspi_versal_indirect_read_dma()
971 	ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id,  in cqspi_versal_indirect_read_dma()
998 	reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_versal_indirect_read_dma()
1000 	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_versal_indirect_read_dma()
1002 	zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR);  in cqspi_versal_indirect_read_dma()
1012 	struct cqspi_st *cqspi = f_pdata->cqspi;  in cqspi_write_setup()
1013 	void __iomem *reg_base = cqspi->iobase;  in cqspi_write_setup()
1020 	if (op->cmd.dtr)  in cqspi_write_setup()
1021 		opcode = op->cmd.opcode >> 8;  in cqspi_write_setup()
1023 		opcode = op->cmd.opcode;  in cqspi_write_setup()
1027 	reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;  in cqspi_write_setup()
1028 	reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;  in cqspi_write_setup()
1036 	 * cypress Semper flash expect a 4-byte dummy address in the Read SR  in cqspi_write_setup()
1040 	 * command when doing auto-HW polling. So, disable write completion  in cqspi_write_setup()
1041 	 * polling on the controller's side. spinand and spi-nor will take  in cqspi_write_setup()
1044 	if (cqspi->wr_completion) {  in cqspi_write_setup()
1053 		cqspi->use_direct_mode_wr = false;  in cqspi_write_setup()
1058 	reg |= (op->addr.nbytes - 1);  in cqspi_write_setup()
1067 	struct cqspi_st *cqspi = f_pdata->cqspi;  in cqspi_indirect_write_execute()
1068 	struct device *dev = &cqspi->pdev->dev;  in cqspi_indirect_write_execute()
1069 	void __iomem *reg_base = cqspi->iobase;  in cqspi_indirect_write_execute()
1082 	reinit_completion(&cqspi->transfer_complete);  in cqspi_indirect_write_execute()
1089 	 * be internally synchronized by the QSPI module. Provide 5  in cqspi_indirect_write_execute()
1092 	if (cqspi->wr_delay)  in cqspi_indirect_write_execute()
1093 		ndelay(cqspi->wr_delay);  in cqspi_indirect_write_execute()
1099 	if (cqspi->apb_ahb_hazard)  in cqspi_indirect_write_execute()
1110 			iowrite32_rep(cqspi->ahb_base, txbuf, write_words);  in cqspi_indirect_write_execute()
1117 			iowrite32(temp, cqspi->ahb_base);  in cqspi_indirect_write_execute()
1121 		if (!wait_for_completion_timeout(&cqspi->transfer_complete,  in cqspi_indirect_write_execute()
1124 			ret = -ETIMEDOUT;  in cqspi_indirect_write_execute()
1128 		remaining -= write_bytes;  in cqspi_indirect_write_execute()
1131 			reinit_completion(&cqspi->transfer_complete);  in cqspi_indirect_write_execute()
1135 	ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTWR,  in cqspi_indirect_write_execute()
1164 	struct cqspi_st *cqspi = f_pdata->cqspi;  in cqspi_chipselect()
1165 	void __iomem *reg_base = cqspi->iobase;  in cqspi_chipselect()
1166 	unsigned int chip_select = f_pdata->cs;  in cqspi_chipselect()
1170 	if (cqspi->is_decoded_cs) {  in cqspi_chipselect()
1181 		chip_select = 0xF & ~(1 << chip_select);  in cqspi_chipselect()
1204 	struct cqspi_st *cqspi = f_pdata->cqspi;  in cqspi_delay()
1205 	void __iomem *iobase = cqspi->iobase;  in cqspi_delay()
1206 	const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;  in cqspi_delay()
1212 	tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);  in cqspi_delay()
1214 	tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);  in cqspi_delay()
1219 	tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);  in cqspi_delay()
1220 	tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);  in cqspi_delay()
1221 	tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);  in cqspi_delay()
1236 	const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;  in cqspi_config_baudrate_div()
1237 	void __iomem *reg_base = cqspi->iobase;  in cqspi_config_baudrate_div()
1240 	/* Recalculate the baudrate divisor based on QSPI specification. */  in cqspi_config_baudrate_div()
1241 	div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;  in cqspi_config_baudrate_div()
1246 		dev_warn(&cqspi->pdev->dev,  in cqspi_config_baudrate_div()
1248 			cqspi->sclk, ref_clk_hz/((div+1)*2));  in cqspi_config_baudrate_div()
1261 	void __iomem *reg_base = cqspi->iobase;  in cqspi_readdata_capture()
1267 		reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);  in cqspi_readdata_capture()
1269 		reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);  in cqspi_readdata_capture()
1283 	struct cqspi_st *cqspi = f_pdata->cqspi;  in cqspi_configure()
1284 	int switch_cs = (cqspi->current_cs != f_pdata->cs);  in cqspi_configure()
1285 	int switch_ck = (cqspi->sclk != sclk);  in cqspi_configure()
1292 		cqspi->current_cs = f_pdata->cs;  in cqspi_configure()
1298 		cqspi->sclk = sclk;  in cqspi_configure()
1301 		cqspi_readdata_capture(cqspi, !cqspi->rclk_en,  in cqspi_configure()
1302 				       f_pdata->read_delay);  in cqspi_configure()
1306 		cqspi_controller_enable(cqspi, 1);  in cqspi_configure()
1312 	struct cqspi_st *cqspi = f_pdata->cqspi;  in cqspi_write()
1313 	loff_t to = op->addr.val;  in cqspi_write()
1314 	size_t len = op->data.nbytes;  in cqspi_write()
1315 	const u_char *buf = op->data.buf.out;  in cqspi_write()
1323 	 * Some flashes like the Cypress Semper flash expect a dummy 4-byte  in cqspi_write()
1330 	if (!op->cmd.dtr && cqspi->use_direct_mode &&  in cqspi_write()
1331 	    cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) {  in cqspi_write()
1332 		memcpy_toio(cqspi->ahb_base + to, buf, len);  in cqspi_write()
1343 	complete(&cqspi->rx_dma_complete);  in cqspi_rx_dma_callback()
1349 	struct cqspi_st *cqspi = f_pdata->cqspi;  in cqspi_direct_read_execute()
1350 	struct device *dev = &cqspi->pdev->dev;  in cqspi_direct_read_execute()
1352 	dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;  in cqspi_direct_read_execute()
1359 	if (!cqspi->rx_chan || !virt_addr_valid(buf)) {  in cqspi_direct_read_execute()
1360 		memcpy_fromio(buf, cqspi->ahb_base + from, len);  in cqspi_direct_read_execute()
1364 	ddev = cqspi->rx_chan->device->dev;  in cqspi_direct_read_execute()
1368 		return -ENOMEM;  in cqspi_direct_read_execute()
1370 	tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,  in cqspi_direct_read_execute()
1374 		ret = -EIO;  in cqspi_direct_read_execute()
1378 	tx->callback = cqspi_rx_dma_callback;  in cqspi_direct_read_execute()
1379 	tx->callback_param = cqspi;  in cqspi_direct_read_execute()
1380 	cookie = tx->tx_submit(tx);  in cqspi_direct_read_execute()
1381 	reinit_completion(&cqspi->rx_dma_complete);  in cqspi_direct_read_execute()
1386 		ret = -EIO;  in cqspi_direct_read_execute()
1390 	dma_async_issue_pending(cqspi->rx_chan);  in cqspi_direct_read_execute()
1391 	if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,  in cqspi_direct_read_execute()
1393 		dmaengine_terminate_sync(cqspi->rx_chan);  in cqspi_direct_read_execute()
1395 		ret = -ETIMEDOUT;  in cqspi_direct_read_execute()
1408 	struct cqspi_st *cqspi = f_pdata->cqspi;  in cqspi_read()
1409 	const struct cqspi_driver_platdata *ddata = cqspi->ddata;  in cqspi_read()
1410 	loff_t from = op->addr.val;  in cqspi_read()
1411 	size_t len = op->data.nbytes;  in cqspi_read()
1412 	u_char *buf = op->data.buf.in;  in cqspi_read()
1420 	if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))  in cqspi_read()
1423 	if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma &&  in cqspi_read()
1425 		return ddata->indirect_read_dma(f_pdata, buf, from, len);  in cqspi_read()
1432 	struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);  in cqspi_mem_process()
1435 	f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)];  in cqspi_mem_process()
1436 	cqspi_configure(f_pdata, op->max_freq);  in cqspi_mem_process()
1438 	if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {  in cqspi_mem_process()
1444 		if (!op->addr.nbytes ||  in cqspi_mem_process()
1445 		    (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX &&  in cqspi_mem_process()
1446 		     !cqspi->disable_stig_mode))  in cqspi_mem_process()
1452 	if (!op->addr.nbytes || !op->data.buf.out)  in cqspi_mem_process()
1461 	struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);  in cqspi_exec_mem_op()
1462 	struct device *dev = &cqspi->pdev->dev;  in cqspi_exec_mem_op()
1466 		dev_err(&mem->spi->dev, "resume failed with %d\n", ret);  in cqspi_exec_mem_op()
1476 		dev_err(&mem->spi->dev, "operation failed with %d\n", ret);  in cqspi_exec_mem_op()
1487 	 * op->dummy.dtr is required for converting nbytes into ncycles.  in cqspi_supports_mem_op()
1490 	all_true = op->cmd.dtr &&  in cqspi_supports_mem_op()
1491 		   (!op->addr.nbytes || op->addr.dtr) &&  in cqspi_supports_mem_op()
1492 		   (!op->dummy.nbytes || op->dummy.dtr) &&  in cqspi_supports_mem_op()
1493 		   (!op->data.nbytes || op->data.dtr);  in cqspi_supports_mem_op()
1495 	all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&  in cqspi_supports_mem_op()
1496 		    !op->data.dtr;  in cqspi_supports_mem_op()
1499 		/* Right now we only support 8-8-8 DTR mode. */  in cqspi_supports_mem_op()
1500 		if (op->cmd.nbytes && op->cmd.buswidth != 8)  in cqspi_supports_mem_op()
1502 		if (op->addr.nbytes && op->addr.buswidth != 8)  in cqspi_supports_mem_op()
1504 		if (op->data.nbytes && op->data.buswidth != 8)  in cqspi_supports_mem_op()
1518 	if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {  in cqspi_of_get_flash_pdata()
1519 		dev_err(&pdev->dev, "couldn't determine read-delay\n");  in cqspi_of_get_flash_pdata()
1520 		return -ENXIO;  in cqspi_of_get_flash_pdata()
1523 	if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {  in cqspi_of_get_flash_pdata()
1524 		dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");  in cqspi_of_get_flash_pdata()
1525 		return -ENXIO;  in cqspi_of_get_flash_pdata()
1528 	if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {  in cqspi_of_get_flash_pdata()
1529 		dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");  in cqspi_of_get_flash_pdata()
1530 		return -ENXIO;  in cqspi_of_get_flash_pdata()
1533 	if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {  in cqspi_of_get_flash_pdata()
1534 		dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");  in cqspi_of_get_flash_pdata()
1535 		return -ENXIO;  in cqspi_of_get_flash_pdata()
1538 	if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {  in cqspi_of_get_flash_pdata()
1539 		dev_err(&pdev->dev, "couldn't determine tslch-ns\n");  in cqspi_of_get_flash_pdata()
1540 		return -ENXIO;  in cqspi_of_get_flash_pdata()
1543 	if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {  in cqspi_of_get_flash_pdata()
1544 		dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");  in cqspi_of_get_flash_pdata()
1545 		return -ENXIO;  in cqspi_of_get_flash_pdata()
1553 	struct device *dev = &cqspi->pdev->dev;  in cqspi_of_get_pdata()
1554 	struct device_node *np = dev->of_node;  in cqspi_of_get_pdata()
1557 	cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");  in cqspi_of_get_pdata()
1559 	if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {  in cqspi_of_get_pdata()
1561 		cqspi->fifo_depth = 0;  in cqspi_of_get_pdata()
1564 	if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {  in cqspi_of_get_pdata()
1565 		dev_err(dev, "couldn't determine fifo-width\n");  in cqspi_of_get_pdata()
1566 		return -ENXIO;  in cqspi_of_get_pdata()
1569 	if (of_property_read_u32(np, "cdns,trigger-address",  in cqspi_of_get_pdata()
1570 				 &cqspi->trigger_address)) {  in cqspi_of_get_pdata()
1571 		dev_err(dev, "couldn't determine trigger-address\n");  in cqspi_of_get_pdata()
1572 		return -ENXIO;  in cqspi_of_get_pdata()
1575 	if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))  in cqspi_of_get_pdata()
1576 		cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;  in cqspi_of_get_pdata()
1578 	cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");  in cqspi_of_get_pdata()
1580 	if (!of_property_read_u32_array(np, "power-domains", id,  in cqspi_of_get_pdata()
1582 		cqspi->pd_dev_id = id[1];  in cqspi_of_get_pdata()
1592 	writel(0, cqspi->iobase + CQSPI_REG_REMAP);  in cqspi_controller_init()
1595 	writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);  in cqspi_controller_init()
1597 	/* Configure the SRAM split to 1:1 . */  in cqspi_controller_init()
1598 	writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);  in cqspi_controller_init()
1601 	writel(cqspi->trigger_address,  in cqspi_controller_init()
1602 	       cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);  in cqspi_controller_init()
1604 	/* Program read watermark -- 1/2 of the FIFO. */  in cqspi_controller_init()
1605 	writel(cqspi->fifo_depth * cqspi->fifo_width / 2,  in cqspi_controller_init()
1606 	       cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);  in cqspi_controller_init()
1607 	/* Program write watermark -- 1/8 of the FIFO. */  in cqspi_controller_init()
1608 	writel(cqspi->fifo_depth * cqspi->fifo_width / 8,  in cqspi_controller_init()
1609 	       cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);  in cqspi_controller_init()
1612 	if (!cqspi->use_direct_mode) {  in cqspi_controller_init()
1613 		reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_controller_init()
1615 		writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_controller_init()
1619 	if (cqspi->use_dma_read) {  in cqspi_controller_init()
1620 		reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_controller_init()
1622 		writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_controller_init()
1628 	struct device *dev = &cqspi->pdev->dev;  in cqspi_controller_detect_fifo_depth()
1632 	 * Bits N-1:0 are writable while bits 31:N are read as zero, with 2^N  in cqspi_controller_detect_fifo_depth()
1635 	writel(U32_MAX, cqspi->iobase + CQSPI_REG_SRAMPARTITION);  in cqspi_controller_detect_fifo_depth()
1636 	reg = readl(cqspi->iobase + CQSPI_REG_SRAMPARTITION);  in cqspi_controller_detect_fifo_depth()
1637 	fifo_depth = reg + 1;  in cqspi_controller_detect_fifo_depth()
1640 	if (cqspi->fifo_depth == 0) {  in cqspi_controller_detect_fifo_depth()
1641 		cqspi->fifo_depth = fifo_depth;  in cqspi_controller_detect_fifo_depth()
1643 	} else if (fifo_depth != cqspi->fifo_depth) {  in cqspi_controller_detect_fifo_depth()
1645 			 fifo_depth, cqspi->fifo_depth);  in cqspi_controller_detect_fifo_depth()
1656 	cqspi->rx_chan = dma_request_chan_by_mask(&mask);  in cqspi_request_mmap_dma()
1657 	if (IS_ERR(cqspi->rx_chan)) {  in cqspi_request_mmap_dma()
1658 		int ret = PTR_ERR(cqspi->rx_chan);  in cqspi_request_mmap_dma()
1660 		cqspi->rx_chan = NULL;  in cqspi_request_mmap_dma()
1661 		if (ret == -ENODEV) {  in cqspi_request_mmap_dma()
1663 			dev_info(&cqspi->pdev->dev, "No Rx DMA available\n");  in cqspi_request_mmap_dma()
1667 		return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");  in cqspi_request_mmap_dma()
1669 	init_completion(&cqspi->rx_dma_complete);  in cqspi_request_mmap_dma()
1676 	struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);  in cqspi_get_name()
1677 	struct device *dev = &cqspi->pdev->dev;  in cqspi_get_name()
1680 			      spi_get_chipselect(mem->spi, 0));  in cqspi_get_name()
1696 	unsigned int max_cs = cqspi->num_chipselect - 1;  in cqspi_setup_flash()
1697 	struct platform_device *pdev = cqspi->pdev;  in cqspi_setup_flash()
1698 	struct device *dev = &pdev->dev;  in cqspi_setup_flash()
1704 	for_each_available_child_of_node_scoped(dev->of_node, np) {  in cqspi_setup_flash()
1711 		if (cs >= cqspi->num_chipselect) {  in cqspi_setup_flash()
1713 			return -EINVAL;  in cqspi_setup_flash()
1718 		f_pdata = &cqspi->f_pdata[cs];  in cqspi_setup_flash()
1719 		f_pdata->cqspi = cqspi;  in cqspi_setup_flash()
1720 		f_pdata->cs = cs;  in cqspi_setup_flash()
1727 	cqspi->num_chipselect = max_cs + 1;  in cqspi_setup_flash()
1740 	ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk);  in cqspi_jh7110_clk_init()
1742 		dev_err(&pdev->dev, "%s: failed to get qspi clocks\n", __func__);  in cqspi_jh7110_clk_init()
1746 	cqspi->clks[CLK_QSPI_APB] = qspiclk[0].clk;  in cqspi_jh7110_clk_init()
1747 	cqspi->clks[CLK_QSPI_AHB] = qspiclk[1].clk;  in cqspi_jh7110_clk_init()
1749 	ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]);  in cqspi_jh7110_clk_init()
1751 		dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n", __func__);  in cqspi_jh7110_clk_init()
1755 	ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]);  in cqspi_jh7110_clk_init()
1757 		dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n", __func__);  in cqspi_jh7110_clk_init()
1761 	cqspi->is_jh7110 = true;  in cqspi_jh7110_clk_init()
1766 	clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]);  in cqspi_jh7110_clk_init()
1773 	clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]);  in cqspi_jh7110_disable_clk()
1774 	clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]);  in cqspi_jh7110_disable_clk()
1780 	struct device *dev = &pdev->dev;  in cqspi_probe()
1787 	host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi));  in cqspi_probe()
1789 		return -ENOMEM;  in cqspi_probe()
1791 	host->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;  in cqspi_probe()
1792 	host->mem_ops = &cqspi_mem_ops;  in cqspi_probe()
1793 	host->mem_caps = &cqspi_mem_caps;  in cqspi_probe()
1794 	host->dev.of_node = pdev->dev.of_node;  in cqspi_probe()
1798 	cqspi->pdev = pdev;  in cqspi_probe()
1799 	cqspi->host = host;  in cqspi_probe()
1800 	cqspi->is_jh7110 = false;  in cqspi_probe()
1801 	cqspi->ddata = ddata = of_device_get_match_data(dev);  in cqspi_probe()
1808 		return -ENODEV;  in cqspi_probe()
1811 	/* Obtain QSPI clock. */  in cqspi_probe()
1812 	cqspi->clk = devm_clk_get(dev, NULL);  in cqspi_probe()
1813 	if (IS_ERR(cqspi->clk)) {  in cqspi_probe()
1814 		dev_err(dev, "Cannot claim QSPI clock.\n");  in cqspi_probe()
1815 		ret = PTR_ERR(cqspi->clk);  in cqspi_probe()
1820 	cqspi->iobase = devm_platform_ioremap_resource(pdev, 0);  in cqspi_probe()
1821 	if (IS_ERR(cqspi->iobase)) {  in cqspi_probe()
1823 		ret = PTR_ERR(cqspi->iobase);  in cqspi_probe()
1828 	cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb);  in cqspi_probe()
1829 	if (IS_ERR(cqspi->ahb_base)) {  in cqspi_probe()
1831 		ret = PTR_ERR(cqspi->ahb_base);  in cqspi_probe()
1834 	cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;  in cqspi_probe()
1835 	cqspi->ahb_size = resource_size(res_ahb);  in cqspi_probe()
1837 	init_completion(&cqspi->transfer_complete);  in cqspi_probe()
1842 		return -ENXIO;  in cqspi_probe()
1849 	ret = clk_prepare_enable(cqspi->clk);  in cqspi_probe()
1851 		dev_err(dev, "Cannot enable QSPI clock.\n");  in cqspi_probe()
1855 	/* Obtain QSPI reset control */  in cqspi_probe()
1856 	rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");  in cqspi_probe()
1859 		dev_err(dev, "Cannot get QSPI reset.\n");  in cqspi_probe()
1863 	rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");  in cqspi_probe()
1866 		dev_err(dev, "Cannot get QSPI OCP reset.\n");  in cqspi_probe()
1870 	if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {  in cqspi_probe()
1874 			dev_err(dev, "Cannot get QSPI REF reset.\n");  in cqspi_probe()
1887 	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);  in cqspi_probe()
1888 	host->max_speed_hz = cqspi->master_ref_clk_hz;  in cqspi_probe()
1891 	cqspi->wr_completion = true;  in cqspi_probe()
1894 		if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)  in cqspi_probe()
1895 			cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,  in cqspi_probe()
1896 						cqspi->master_ref_clk_hz);  in cqspi_probe()
1897 		if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)  in cqspi_probe()
1898 			host->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;  in cqspi_probe()
1899 		if (ddata->hwcaps_mask & CQSPI_SUPPORTS_QUAD)  in cqspi_probe()
1900 			host->mode_bits |= SPI_TX_QUAD;  in cqspi_probe()
1901 		if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) {  in cqspi_probe()
1902 			cqspi->use_direct_mode = true;  in cqspi_probe()
1903 			cqspi->use_direct_mode_wr = true;  in cqspi_probe()
1905 		if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA)  in cqspi_probe()
1906 			cqspi->use_dma_read = true;  in cqspi_probe()
1907 		if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION)  in cqspi_probe()
1908 			cqspi->wr_completion = false;  in cqspi_probe()
1909 		if (ddata->quirks & CQSPI_SLOW_SRAM)  in cqspi_probe()
1910 			cqspi->slow_sram = true;  in cqspi_probe()
1911 		if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR)  in cqspi_probe()
1912 			cqspi->apb_ahb_hazard = true;  in cqspi_probe()
1914 		if (ddata->jh7110_clk_init) {  in cqspi_probe()
1919 		if (ddata->quirks & CQSPI_DISABLE_STIG_MODE)  in cqspi_probe()
1920 			cqspi->disable_stig_mode = true;  in cqspi_probe()
1922 		if (ddata->quirks & CQSPI_DMA_SET_MASK) {  in cqspi_probe()
1923 			ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));  in cqspi_probe()
1930 			       pdev->name, cqspi);  in cqspi_probe()
1940 	cqspi_controller_enable(cqspi, 1);  in cqspi_probe()
1941 	cqspi->current_cs = -1;  in cqspi_probe()
1942 	cqspi->sclk = 0;  in cqspi_probe()
1950 	host->num_chipselect = cqspi->num_chipselect;  in cqspi_probe()
1952 	if (ddata->quirks & CQSPI_SUPPORT_DEVICE_RESET)  in cqspi_probe()
1955 	if (cqspi->use_direct_mode) {  in cqspi_probe()
1957 		if (ret == -EPROBE_DEFER)  in cqspi_probe()
1963 		if (cqspi->rx_chan)  in cqspi_probe()
1964 			dma_release_channel(cqspi->rx_chan);  in cqspi_probe()
1974 		dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);  in cqspi_probe()
1985 	if (cqspi->is_jh7110)  in cqspi_probe()
1987 	clk_disable_unprepare(cqspi->clk);  in cqspi_probe()
1996 	spi_unregister_controller(cqspi->host);  in cqspi_remove()
1999 	if (cqspi->rx_chan)  in cqspi_remove()
2000 		dma_release_channel(cqspi->rx_chan);  in cqspi_remove()
2002 	clk_disable_unprepare(cqspi->clk);  in cqspi_remove()
2004 	if (cqspi->is_jh7110)  in cqspi_remove()
2007 	pm_runtime_put_sync(&pdev->dev);  in cqspi_remove()
2008 	pm_runtime_disable(&pdev->dev);  in cqspi_remove()
2016 	clk_disable_unprepare(cqspi->clk);  in cqspi_runtime_suspend()
2024 	clk_prepare_enable(cqspi->clk);  in cqspi_runtime_resume()
2028 	cqspi_controller_enable(cqspi, 1);  in cqspi_runtime_resume()
2030 	cqspi->current_cs = -1;  in cqspi_runtime_resume()
2031 	cqspi->sclk = 0;  in cqspi_runtime_resume()
2040 	ret = spi_controller_suspend(cqspi->host);  in cqspi_suspend()
2058 	return spi_controller_resume(cqspi->host);  in cqspi_resume()
2124 		.compatible = "cdns,qspi-nor",
2128 		.compatible = "ti,k2g-qspi",
2132 		.compatible = "ti,am654-ospi",
2136 		.compatible = "intel,lgm-qspi",
2140 		.compatible = "xlnx,versal-ospi-1.0",
2144 		.compatible = "intel,socfpga-qspi",
2148 		.compatible = "starfive,jh7110-qspi",
2152 		.compatible = "amd,pensando-elba-qspi",
2156 		.compatible = "mobileye,eyeq5-ospi",
2160 		.compatible = "amd,versal2-ospi",
2180 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");