109 struct spi_engine {  struct
363 static bool spi_engine_write_cmd_fifo(struct spi_engine *spi_engine,  in spi_engine_write_cmd_fifo()  argument
366 	void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_CMD_FIFO;  in spi_engine_write_cmd_fifo()
371 	n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_CMD_FIFO_ROOM);  in spi_engine_write_cmd_fifo()
385 static bool spi_engine_write_tx_fifo(struct spi_engine *spi_engine,  in spi_engine_write_tx_fifo()  argument
388 	void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDO_DATA_FIFO;  in spi_engine_write_tx_fifo()
392 	n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDO_FIFO_ROOM);  in spi_engine_write_tx_fifo()
427 static bool spi_engine_read_rx_fifo(struct spi_engine *spi_engine,  in spi_engine_read_rx_fifo()  argument
430 	void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDI_DATA_FIFO;  in spi_engine_read_rx_fifo()
434 	n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDI_FIFO_LEVEL);  in spi_engine_read_rx_fifo()
473 	struct spi_engine *spi_engine = spi_controller_get_devdata(host);  in spi_engine_irq()  local
478 	pending = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_INT_PENDING);  in spi_engine_irq()
482 			spi_engine->base + SPI_ENGINE_REG_INT_PENDING);  in spi_engine_irq()
484 			spi_engine->base + SPI_ENGINE_REG_SYNC_ID);  in spi_engine_irq()
487 	spin_lock(&spi_engine->lock);  in spi_engine_irq()
490 		if (!spi_engine_write_cmd_fifo(spi_engine, msg))  in spi_engine_irq()
495 		if (!spi_engine_write_tx_fifo(spi_engine, msg))  in spi_engine_irq()
500 		if (!spi_engine_read_rx_fifo(spi_engine, msg))  in spi_engine_irq()
508 			complete(&spi_engine->msg_complete);  in spi_engine_irq()
514 		spi_engine->int_enable &= ~disable_int;  in spi_engine_irq()
515 		writel_relaxed(spi_engine->int_enable,  in spi_engine_irq()
516 			spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);  in spi_engine_irq()
519 	spin_unlock(&spi_engine->lock);  in spi_engine_irq()
557 	struct spi_engine *spi_engine = spi_controller_get_devdata(host);  in spi_engine_setup()  local
560 		spi_engine->cs_inv |= BIT(spi_get_chipselect(device, 0));  in spi_engine_setup()
562 		spi_engine->cs_inv &= ~BIT(spi_get_chipselect(device, 0));  in spi_engine_setup()
564 	writel_relaxed(SPI_ENGINE_CMD_CS_INV(spi_engine->cs_inv),  in spi_engine_setup()
565 		       spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);  in spi_engine_setup()
572 		       spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);  in spi_engine_setup()
580 	struct spi_engine *spi_engine = spi_controller_get_devdata(host);  in spi_engine_transfer_one_message()  local
581 	struct spi_engine_message_state *st = &spi_engine->msg_state;  in spi_engine_transfer_one_message()
592 	reinit_completion(&spi_engine->msg_complete);  in spi_engine_transfer_one_message()
601 	spin_lock_irqsave(&spi_engine->lock, flags);  in spi_engine_transfer_one_message()
603 	if (spi_engine_write_cmd_fifo(spi_engine, msg))  in spi_engine_transfer_one_message()
607 	if (spi_engine_write_tx_fifo(spi_engine, msg))  in spi_engine_transfer_one_message()
617 		spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);  in spi_engine_transfer_one_message()
618 	spi_engine->int_enable = int_enable;  in spi_engine_transfer_one_message()
619 	spin_unlock_irqrestore(&spi_engine->lock, flags);  in spi_engine_transfer_one_message()
621 	if (!wait_for_completion_timeout(&spi_engine->msg_complete,  in spi_engine_transfer_one_message()
642 	struct spi_engine *spi_engine = p;  in spi_engine_release_hw()  local
644 	writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);  in spi_engine_release_hw()
645 	writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);  in spi_engine_release_hw()
646 	writel_relaxed(0x01, spi_engine->base + SPI_ENGINE_REG_RESET);  in spi_engine_release_hw()
651 	struct spi_engine *spi_engine;  in spi_engine_probe()  local
661 	host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi_engine));  in spi_engine_probe()
665 	spi_engine = spi_controller_get_devdata(host);  in spi_engine_probe()
667 	spin_lock_init(&spi_engine->lock);  in spi_engine_probe()
668 	init_completion(&spi_engine->msg_complete);  in spi_engine_probe()
670 	spi_engine->clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk");  in spi_engine_probe()
671 	if (IS_ERR(spi_engine->clk))  in spi_engine_probe()
672 		return PTR_ERR(spi_engine->clk);  in spi_engine_probe()
674 	spi_engine->ref_clk = devm_clk_get_enabled(&pdev->dev, "spi_clk");  in spi_engine_probe()
675 	if (IS_ERR(spi_engine->ref_clk))  in spi_engine_probe()
676 		return PTR_ERR(spi_engine->ref_clk);  in spi_engine_probe()
678 	spi_engine->base = devm_platform_ioremap_resource(pdev, 0);  in spi_engine_probe()
679 	if (IS_ERR(spi_engine->base))  in spi_engine_probe()
680 		return PTR_ERR(spi_engine->base);  in spi_engine_probe()
682 	version = readl(spi_engine->base + ADI_AXI_REG_VERSION);  in spi_engine_probe()
691 	writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_RESET);  in spi_engine_probe()
692 	writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);  in spi_engine_probe()
693 	writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);  in spi_engine_probe()
696 				       spi_engine);  in spi_engine_probe()
708 	host->max_speed_hz = clk_get_rate(spi_engine->ref_clk) / 2;  in spi_engine_probe()