29 #define REG_SPI_CTRL_BASE			0x1FA10000
31 #define REG_SPI_CTRL_READ_MODE			0x0000
32 #define REG_SPI_CTRL_READ_IDLE_EN		0x0004
33 #define REG_SPI_CTRL_SIDLY			0x0008
34 #define REG_SPI_CTRL_CSHEXT			0x000c
35 #define REG_SPI_CTRL_CSLEXT			0x0010
37 #define REG_SPI_CTRL_MTX_MODE_TOG		0x0014
38 #define SPI_CTRL_MTX_MODE_TOG			GENMASK(3, 0)
40 #define REG_SPI_CTRL_RDCTL_FSM			0x0018
41 #define SPI_CTRL_RDCTL_FSM			GENMASK(3, 0)
43 #define REG_SPI_CTRL_MACMUX_SEL			0x001c
45 #define REG_SPI_CTRL_MANUAL_EN			0x0020
46 #define SPI_CTRL_MANUAL_EN			BIT(0)
48 #define REG_SPI_CTRL_OPFIFO_EMPTY		0x0024
49 #define SPI_CTRL_OPFIFO_EMPTY			BIT(0)
51 #define REG_SPI_CTRL_OPFIFO_WDATA		0x0028
52 #define SPI_CTRL_OPFIFO_LEN			GENMASK(8, 0)
55 #define REG_SPI_CTRL_OPFIFO_FULL		0x002c
56 #define SPI_CTRL_OPFIFO_FULL			BIT(0)
58 #define REG_SPI_CTRL_OPFIFO_WR			0x0030
59 #define SPI_CTRL_OPFIFO_WR			BIT(0)
61 #define REG_SPI_CTRL_DFIFO_FULL			0x0034
62 #define SPI_CTRL_DFIFO_FULL			BIT(0)
64 #define REG_SPI_CTRL_DFIFO_WDATA		0x0038
65 #define SPI_CTRL_DFIFO_WDATA			GENMASK(7, 0)
67 #define REG_SPI_CTRL_DFIFO_EMPTY		0x003c
68 #define SPI_CTRL_DFIFO_EMPTY			BIT(0)
70 #define REG_SPI_CTRL_DFIFO_RD			0x0040
71 #define SPI_CTRL_DFIFO_RD			BIT(0)
73 #define REG_SPI_CTRL_DFIFO_RDATA		0x0044
74 #define SPI_CTRL_DFIFO_RDATA			GENMASK(7, 0)
76 #define REG_SPI_CTRL_DUMMY			0x0080
77 #define SPI_CTRL_CTRL_DUMMY			GENMASK(3, 0)
79 #define REG_SPI_CTRL_PROBE_SEL			0x0088
80 #define REG_SPI_CTRL_INTERRUPT			0x0090
81 #define REG_SPI_CTRL_INTERRUPT_EN		0x0094
82 #define REG_SPI_CTRL_SI_CK_SEL			0x009c
83 #define REG_SPI_CTRL_SW_CFGNANDADDR_VAL		0x010c
84 #define REG_SPI_CTRL_SW_CFGNANDADDR_EN		0x0110
85 #define REG_SPI_CTRL_SFC_STRAP			0x0114
87 #define REG_SPI_CTRL_NFI2SPI_EN			0x0130
88 #define SPI_CTRL_NFI2SPI_EN			BIT(0)
91 #define REG_SPI_NFI_CNFG			0x0000
92 #define SPI_NFI_DMA_MODE			BIT(0)
99 #define REG_SPI_NFI_PAGEFMT			0x0004
100 #define SPI_NFI_PAGE_SIZE			GENMASK(1, 0)
103 #define REG_SPI_NFI_CON				0x0008
104 #define SPI_NFI_FIFO_FLUSH			BIT(0)
110 #define REG_SPI_NFI_INTR_EN			0x0010
111 #define SPI_NFI_RD_DONE_EN			BIT(0)
124 #define REG_SPI_NFI_INTR			0x0014
127 #define REG_SPI_NFI_CMD				0x0020
129 #define REG_SPI_NFI_ADDR_NOB			0x0030
132 #define REG_SPI_NFI_STA				0x0060
133 #define REG_SPI_NFI_FIFOSTA			0x0064
134 #define REG_SPI_NFI_STRADDR			0x0080
135 #define REG_SPI_NFI_FDM0L			0x00a0
136 #define REG_SPI_NFI_FDM0M			0x00a4
137 #define REG_SPI_NFI_FDM7L			0x00d8
138 #define REG_SPI_NFI_FDM7M			0x00dc
139 #define REG_SPI_NFI_FIFODATA0			0x0190
140 #define REG_SPI_NFI_FIFODATA1			0x0194
141 #define REG_SPI_NFI_FIFODATA2			0x0198
142 #define REG_SPI_NFI_FIFODATA3			0x019c
143 #define REG_SPI_NFI_MASTERSTA			0x0224
145 #define REG_SPI_NFI_SECCUS_SIZE			0x022c
146 #define SPI_NFI_CUS_SEC_SIZE			GENMASK(12, 0)
149 #define REG_SPI_NFI_RD_CTL2			0x0510
150 #define REG_SPI_NFI_RD_CTL3			0x0514
152 #define REG_SPI_NFI_PG_CTL1			0x0524
155 #define REG_SPI_NFI_PG_CTL2			0x0528
156 #define REG_SPI_NFI_NOR_PROG_ADDR		0x052c
157 #define REG_SPI_NFI_NOR_RD_ADDR			0x0534
159 #define REG_SPI_NFI_SNF_MISC_CTL		0x0538
162 #define REG_SPI_NFI_SNF_MISC_CTL2		0x053c
163 #define SPI_NFI_READ_DATA_BYTE_NUM		GENMASK(12, 0)
166 #define REG_SPI_NFI_SNF_STA_CTL1		0x0550
170 #define REG_SPI_NFI_SNF_STA_CTL2		0x0554
172 #define REG_SPI_NFI_SNF_NFI_CNFG		0x055c
173 #define SPI_NFI_SPI_MODE			BIT(0)
176 #define SPI_NAND_OP_GET_FEATURE			0x0f
177 #define SPI_NAND_OP_SET_FEATURE			0x1f
178 #define SPI_NAND_OP_PAGE_READ			0x13
179 #define SPI_NAND_OP_READ_FROM_CACHE_SINGLE	0x03
180 #define SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST	0x0b
181 #define SPI_NAND_OP_READ_FROM_CACHE_DUAL	0x3b
182 #define SPI_NAND_OP_READ_FROM_CACHE_QUAD	0x6b
183 #define SPI_NAND_OP_WRITE_ENABLE		0x06
184 #define SPI_NAND_OP_WRITE_DISABLE		0x04
185 #define SPI_NAND_OP_PROGRAM_LOAD_SINGLE		0x02
186 #define SPI_NAND_OP_PROGRAM_LOAD_QUAD		0x32
187 #define SPI_NAND_OP_PROGRAM_LOAD_RAMDOM_SINGLE	0x84
188 #define SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD	0x34
189 #define SPI_NAND_OP_PROGRAM_EXECUTE		0x10
190 #define SPI_NAND_OP_READ_ID			0x9f
191 #define SPI_NAND_OP_BLOCK_ERASE			0xd8
192 #define SPI_NAND_OP_RESET			0xff
193 #define SPI_NAND_OP_DIE_SELECT			0xc2
238 				       0, 250 * USEC_PER_MSEC);  in airoha_snand_set_fifo_op()
250 					0, 250 * USEC_PER_MSEC);  in airoha_snand_set_fifo_op()
263 	for (i = 0; i < len; i++) {  in airoha_snand_write_data_to_fifo()
271 					       0, 250 * USEC_PER_MSEC);  in airoha_snand_write_data_to_fifo()
286 					       0, 250 * USEC_PER_MSEC);  in airoha_snand_write_data_to_fifo()
291 	return 0;  in airoha_snand_write_data_to_fifo()
299 	for (i = 0; i < len; i++) {  in airoha_snand_read_data_from_fifo()
307 					       0, 250 * USEC_PER_MSEC);  in airoha_snand_read_data_from_fifo()
325 	return 0;  in airoha_snand_read_data_from_fifo()
338 				   REG_SPI_CTRL_NFI2SPI_EN, 0);  in airoha_snand_set_mode()
343 				   REG_SPI_CTRL_READ_IDLE_EN, 0);  in airoha_snand_set_mode()
350 					       0, 250 * USEC_PER_MSEC);  in airoha_snand_set_mode()
369 		if (err < 0)  in airoha_snand_set_mode()
373 				   REG_SPI_CTRL_MTX_MODE_TOG, 0x0);  in airoha_snand_set_mode()
374 		if (err < 0)  in airoha_snand_set_mode()
378 				   REG_SPI_CTRL_MANUAL_EN, 0x0);  in airoha_snand_set_mode()
379 		if (err < 0)  in airoha_snand_set_mode()
387 	return regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_DUMMY, 0);  in airoha_snand_set_mode()
395 	for (i = 0; i < len; i += data_len) {  in airoha_snand_write_data()
405 		if (err < 0)  in airoha_snand_write_data()
409 	return 0;  in airoha_snand_write_data()
417 	for (i = 0; i < len; i += data_len) {  in airoha_snand_read_data()
421 		err = airoha_snand_set_fifo_op(as_ctrl, 0xc, data_len);  in airoha_snand_read_data()
427 		if (err < 0)  in airoha_snand_read_data()
431 	return 0;  in airoha_snand_read_data()
480 		val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x1);  in airoha_snand_nfi_config()
483 		val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x2);  in airoha_snand_nfi_config()
486 		val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x3);  in airoha_snand_nfi_config()
489 		val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x0);  in airoha_snand_nfi_config()
500 		val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x1);  in airoha_snand_nfi_config()
503 		val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x2);  in airoha_snand_nfi_config()
506 		val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x0);  in airoha_snand_nfi_config()
546 		if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > 0xf)  in airoha_snand_is_page_ops()
591 	return 0;  in airoha_snand_adjust_op_size()
624 	return 0;  in airoha_snand_dirmap_create()
646 		rd_mode = 0;  in airoha_snand_dirmap_read()
652 	if (err < 0)  in airoha_snand_dirmap_read()
693 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL3, 0x0);  in airoha_snand_dirmap_read()
709 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x0);  in airoha_snand_dirmap_read()
727 				       0, 1 * USEC_PER_SEC);  in airoha_snand_dirmap_read()
742 				       val, (val & SPI_NFI_AHB_DONE), 0,  in airoha_snand_dirmap_read()
753 	if (err < 0)  in airoha_snand_dirmap_read()
779 	if (err < 0)  in airoha_snand_dirmap_write()
790 	if (err < 0)  in airoha_snand_dirmap_write()
801 		wr_mode = 0;  in airoha_snand_dirmap_write()
827 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL2, 0x0);  in airoha_snand_dirmap_write()
847 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x80);  in airoha_snand_dirmap_write()
862 				       val, (val & SPI_NFI_AHB_DONE), 0,  in airoha_snand_dirmap_write()
870 				       0, 1 * USEC_PER_SEC);  in airoha_snand_dirmap_write()
887 	if (err < 0)  in airoha_snand_dirmap_write()
909 	if (err < 0)  in airoha_snand_exec_op()
913 	if (err < 0)  in airoha_snand_exec_op()
917 	err = airoha_snand_write_data(as_ctrl, 0x8, &opcode, sizeof(opcode));  in airoha_snand_exec_op()
922 	cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8;  in airoha_snand_exec_op()
928 					      sizeof(data[0]));  in airoha_snand_exec_op()
934 	data[0] = 0xff;  in airoha_snand_exec_op()
935 	for (i = 0; i < op->dummy.nbytes; i++) {  in airoha_snand_exec_op()
936 		err = airoha_snand_write_data(as_ctrl, 0x8, &data[0],  in airoha_snand_exec_op()
937 					      sizeof(data[0]));  in airoha_snand_exec_op()
949 		err = airoha_snand_write_data(as_ctrl, 0x8, op->data.buf.out,  in airoha_snand_exec_op()
981 	return 0;  in airoha_snand_setup()
1051 	base = devm_platform_ioremap_resource(pdev, 0);  in airoha_snand_probe()