Lines Matching full:pmc
3 * drivers/soc/tegra/pmc.c
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
54 #include <soc/tegra/pmc.h>
61 #include <dt-bindings/soc/tegra-pmc.h>
197 /* for secure PMC */
269 struct tegra_pmc *pmc; member
357 void (*init)(struct tegra_pmc *pmc);
358 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
361 void (*set_wake_filters)(struct tegra_pmc *pmc);
364 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,
391 * struct tegra_pmc - NVIDIA Tegra PMC
392 * @dev: pointer to PMC device structure
399 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
415 * @pctl_dev: pin controller exposed by the PMC
416 * @domain: IRQ domain provided by the PMC
473 static struct tegra_pmc *pmc = &(struct tegra_pmc) { variable
484 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) in tegra_pmc_readl() argument
488 if (pmc->tz_only) { in tegra_pmc_readl()
492 if (pmc->dev) in tegra_pmc_readl()
493 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_readl()
503 return readl(pmc->base + offset); in tegra_pmc_readl()
506 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, in tegra_pmc_writel() argument
511 if (pmc->tz_only) { in tegra_pmc_writel()
515 if (pmc->dev) in tegra_pmc_writel()
516 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_writel()
523 writel(value, pmc->base + offset); in tegra_pmc_writel()
527 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) in tegra_pmc_scratch_readl() argument
529 if (pmc->tz_only) in tegra_pmc_scratch_readl()
530 return tegra_pmc_readl(pmc, offset); in tegra_pmc_scratch_readl()
532 return readl(pmc->scratch + offset); in tegra_pmc_scratch_readl()
535 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, in tegra_pmc_scratch_writel() argument
538 if (pmc->tz_only) in tegra_pmc_scratch_writel()
539 tegra_pmc_writel(pmc, value, offset); in tegra_pmc_scratch_writel()
541 writel(value, pmc->scratch + offset); in tegra_pmc_scratch_writel()
551 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_state()
552 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; in tegra_powergate_state()
554 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; in tegra_powergate_state()
557 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) in tegra_powergate_is_valid() argument
559 return (pmc->soc && pmc->soc->powergates[id]); in tegra_powergate_is_valid()
562 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) in tegra_powergate_is_available() argument
564 return test_bit(id, pmc->powergates_available); in tegra_powergate_is_available()
567 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) in tegra_powergate_lookup() argument
571 if (!pmc || !pmc->soc || !name) in tegra_powergate_lookup()
574 for (i = 0; i < pmc->soc->num_powergates; i++) { in tegra_powergate_lookup()
575 if (!tegra_powergate_is_valid(pmc, i)) in tegra_powergate_lookup()
578 if (!strcmp(name, pmc->soc->powergates[i])) in tegra_powergate_lookup()
585 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id, in tegra20_powergate_set() argument
593 * As per TRM documentation, the toggle command will be dropped by PMC in tegra20_powergate_set()
598 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); in tegra20_powergate_set()
600 /* wait for PMC to execute the command */ in tegra20_powergate_set()
608 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc) in tegra_powergate_toggle_ready() argument
610 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START); in tegra_powergate_toggle_ready()
613 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id, in tegra114_powergate_set() argument
619 /* wait while PMC power gating is contended */ in tegra114_powergate_set()
620 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, in tegra114_powergate_set()
625 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); in tegra114_powergate_set()
627 /* wait for PMC to accept the command */ in tegra114_powergate_set()
628 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, in tegra114_powergate_set()
633 /* wait for PMC to execute the command */ in tegra114_powergate_set()
644 * @pmc: power management controller
648 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, in tegra_powergate_set() argument
653 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_set()
656 mutex_lock(&pmc->powergates_lock); in tegra_powergate_set()
659 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
663 err = pmc->soc->powergate_set(pmc, id, new_state); in tegra_powergate_set()
665 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
670 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, in __tegra_powergate_remove_clamping() argument
675 mutex_lock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
682 if (pmc->soc->has_gpu_clamps) { in __tegra_powergate_remove_clamping()
683 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); in __tegra_powergate_remove_clamping()
699 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); in __tegra_powergate_remove_clamping()
702 mutex_unlock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
797 err = tegra_powergate_set(pg->pmc, pg->id, true); in tegra_powergate_power_up()
813 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); in tegra_powergate_power_up()
825 if (pg->pmc->soc->needs_mbist_war) in tegra_powergate_power_up()
847 tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_up()
876 err = tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_down()
904 struct device *dev = pg->pmc->dev; in tegra_genpd_power_on()
923 struct device *dev = pg->pmc->dev; in tegra_genpd_power_off()
949 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_power_on()
952 return tegra_powergate_set(pmc, id, true); in tegra_powergate_power_on()
962 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_power_off()
965 return tegra_powergate_set(pmc, id, false); in tegra_powergate_power_off()
971 * @pmc: power management controller
974 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) in tegra_powergate_is_powered() argument
976 if (!tegra_powergate_is_valid(pmc, id)) in tegra_powergate_is_powered()
988 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_remove_clamping()
991 return __tegra_powergate_remove_clamping(pmc, id); in tegra_powergate_remove_clamping()
1009 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_sequence_power_up()
1026 pg->pmc = pmc; in tegra_powergate_sequence_power_up()
1030 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, in tegra_powergate_sequence_power_up()
1042 * @pmc: power management controller
1048 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, in tegra_get_cpu_powergate_id() argument
1051 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) in tegra_get_cpu_powergate_id()
1052 return pmc->soc->cpu_powergates[cpuid]; in tegra_get_cpu_powergate_id()
1065 id = tegra_get_cpu_powergate_id(pmc, cpuid); in tegra_pmc_cpu_is_powered()
1069 return tegra_powergate_is_powered(pmc, id); in tegra_pmc_cpu_is_powered()
1080 id = tegra_get_cpu_powergate_id(pmc, cpuid); in tegra_pmc_cpu_power_on()
1084 return tegra_powergate_set(pmc, id, true); in tegra_pmc_cpu_power_on()
1095 id = tegra_get_cpu_powergate_id(pmc, cpuid); in tegra_pmc_cpu_remove_clamping()
1106 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); in tegra_pmc_program_reboot_reason()
1120 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); in tegra_pmc_program_reboot_reason()
1141 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra_pmc_restart()
1143 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra_pmc_restart()
1163 tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37); in tegra_pmc_power_off_handler()
1178 for (i = 0; i < pmc->soc->num_powergates; i++) { in powergate_show()
1179 status = tegra_powergate_is_powered(pmc, i); in powergate_show()
1183 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], in powergate_show()
1238 struct device *dev = pg->pmc->dev; in tegra_powergate_of_get_resets()
1273 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) in tegra_powergate_add() argument
1275 struct device *dev = pmc->dev; in tegra_powergate_add()
1284 id = tegra_powergate_lookup(pmc, np->name); in tegra_powergate_add()
1295 clear_bit(id, pmc->powergates_available); in tegra_powergate_add()
1301 pg->pmc = pmc; in tegra_powergate_add()
1303 off = !tegra_powergate_is_powered(pmc, pg->id); in tegra_powergate_add()
1355 set_bit(id, pmc->powergates_available); in tegra_powergate_add()
1365 return pmc->core_domain_state_synced; in tegra_pmc_core_domain_state_synced()
1382 mutex_lock(&pmc->powergates_lock); in tegra_pmc_core_pd_set_performance_state()
1383 err = dev_pm_opp_set_opp(pmc->dev, opp); in tegra_pmc_core_pd_set_performance_state()
1384 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_core_pd_set_performance_state()
1397 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np) in tegra_pmc_core_pd_add() argument
1403 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL); in tegra_pmc_core_pd_add()
1410 err = devm_pm_opp_set_regulators(pmc->dev, rname); in tegra_pmc_core_pd_add()
1412 return dev_err_probe(pmc->dev, err, in tegra_pmc_core_pd_add()
1417 dev_err(pmc->dev, "failed to init core genpd: %d\n", err); in tegra_pmc_core_pd_add()
1423 dev_err(pmc->dev, "failed to add core genpd: %d\n", err); in tegra_pmc_core_pd_add()
1427 pmc->core_domain_registered = true; in tegra_pmc_core_pd_add()
1437 static int tegra_powergate_init(struct tegra_pmc *pmc, in tegra_powergate_init() argument
1450 err = tegra_pmc_core_pd_add(pmc, np); in tegra_powergate_init()
1461 err = tegra_powergate_add(pmc, child); in tegra_powergate_init()
1495 set_bit(pg->id, pmc->powergates_available); in tegra_powergate_remove()
1529 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) in tegra_io_pad_find() argument
1533 for (i = 0; i < pmc->soc->num_io_pads; i++) in tegra_io_pad_find()
1534 if (pmc->soc->io_pads[i].id == id) in tegra_io_pad_find()
1535 return &pmc->soc->io_pads[i]; in tegra_io_pad_find()
1540 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, in tegra_io_pad_prepare() argument
1555 if (pmc->clk) { in tegra_io_pad_prepare()
1556 rate = pmc->rate; in tegra_io_pad_prepare()
1558 dev_err(pmc->dev, "failed to get clock rate\n"); in tegra_io_pad_prepare()
1562 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); in tegra_io_pad_prepare()
1567 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); in tegra_io_pad_prepare()
1573 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, in tegra_io_pad_poll() argument
1581 value = tegra_pmc_readl(pmc, offset); in tegra_io_pad_poll()
1591 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) in tegra_io_pad_unprepare() argument
1593 if (pmc->clk) in tegra_io_pad_unprepare()
1594 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); in tegra_io_pad_unprepare()
1610 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_power_enable()
1612 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_power_enable()
1616 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1618 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); in tegra_io_pad_power_enable()
1620 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1624 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); in tegra_io_pad_power_enable()
1626 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); in tegra_io_pad_power_enable()
1628 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1632 tegra_io_pad_unprepare(pmc); in tegra_io_pad_power_enable()
1635 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1653 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_power_disable()
1655 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_power_disable()
1659 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1661 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); in tegra_io_pad_power_disable()
1663 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1667 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); in tegra_io_pad_power_disable()
1669 err = tegra_io_pad_poll(pmc, status, mask, mask, 250); in tegra_io_pad_power_disable()
1671 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1675 tegra_io_pad_unprepare(pmc); in tegra_io_pad_power_disable()
1678 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1683 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) in tegra_io_pad_is_powered() argument
1689 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_is_powered()
1691 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_is_powered()
1701 value = tegra_pmc_readl(pmc, status); in tegra_io_pad_is_powered()
1706 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, in tegra_io_pad_set_voltage() argument
1712 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_set_voltage()
1719 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1721 if (pmc->soc->has_impl_33v_pwr) { in tegra_io_pad_set_voltage()
1722 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); in tegra_io_pad_set_voltage()
1729 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR); in tegra_io_pad_set_voltage()
1732 value = tegra_pmc_readl(pmc, PMC_PWR_DET); in tegra_io_pad_set_voltage()
1734 tegra_pmc_writel(pmc, value, PMC_PWR_DET); in tegra_io_pad_set_voltage()
1737 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); in tegra_io_pad_set_voltage()
1744 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE); in tegra_io_pad_set_voltage()
1747 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1754 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) in tegra_io_pad_get_voltage() argument
1759 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_get_voltage()
1766 if (pmc->soc->has_impl_33v_pwr) in tegra_io_pad_get_voltage()
1767 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); in tegra_io_pad_get_voltage()
1769 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); in tegra_io_pad_get_voltage()
1780 return pmc->suspend_mode; in tegra_pmc_get_suspend_mode()
1788 pmc->suspend_mode = mode; in tegra_pmc_set_suspend_mode()
1803 rate = pmc->rate; in tegra_pmc_enter_suspend_mode()
1813 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1815 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); in tegra_pmc_enter_suspend_mode()
1817 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1819 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); in tegra_pmc_enter_suspend_mode()
1821 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra_pmc_enter_suspend_mode()
1824 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra_pmc_enter_suspend_mode()
1828 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) in tegra_pmc_parse_dt() argument
1833 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1837 pmc->suspend_mode = TEGRA_SUSPEND_LP0; in tegra_pmc_parse_dt()
1841 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1845 pmc->suspend_mode = TEGRA_SUSPEND_LP2; in tegra_pmc_parse_dt()
1849 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1854 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); in tegra_pmc_parse_dt()
1857 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1859 pmc->cpu_good_time = value; in tegra_pmc_parse_dt()
1862 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1864 pmc->cpu_off_time = value; in tegra_pmc_parse_dt()
1868 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1870 pmc->core_osc_time = values[0]; in tegra_pmc_parse_dt()
1871 pmc->core_pmu_time = values[1]; in tegra_pmc_parse_dt()
1874 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1876 pmc->core_off_time = value; in tegra_pmc_parse_dt()
1878 pmc->corereq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1881 pmc->sysclkreq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1884 pmc->combined_req = of_property_read_bool(np, in tegra_pmc_parse_dt()
1887 pmc->cpu_pwr_good_en = of_property_read_bool(np, in tegra_pmc_parse_dt()
1892 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) in tegra_pmc_parse_dt()
1893 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1895 pmc->lp0_vec_phys = values[0]; in tegra_pmc_parse_dt()
1896 pmc->lp0_vec_size = values[1]; in tegra_pmc_parse_dt()
1901 static int tegra_pmc_init(struct tegra_pmc *pmc) in tegra_pmc_init() argument
1903 if (pmc->soc->max_wake_events > 0) { in tegra_pmc_init()
1904 pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1905 if (!pmc->wake_type_level_map) in tegra_pmc_init()
1908 pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1909 if (!pmc->wake_type_dual_edge_map) in tegra_pmc_init()
1912 pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1913 if (!pmc->wake_sw_status_map) in tegra_pmc_init()
1916 pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1917 if (!pmc->wake_cntrl_level_map) in tegra_pmc_init()
1921 if (pmc->soc->init) in tegra_pmc_init()
1922 pmc->soc->init(pmc); in tegra_pmc_init()
1927 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) in tegra_pmc_init_tsense_reset() argument
1931 struct device *dev = pmc->dev; in tegra_pmc_init_tsense_reset()
1935 if (!pmc->soc->has_tsense_reset) in tegra_pmc_init_tsense_reset()
1938 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); in tegra_pmc_init_tsense_reset()
1967 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
1969 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
1973 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); in tegra_pmc_init_tsense_reset()
1991 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); in tegra_pmc_init_tsense_reset()
1993 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
1995 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
1997 dev_info(pmc->dev, "emergency thermal reset enabled\n"); in tegra_pmc_init_tsense_reset()
2005 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinctrl_get_groups_count() local
2007 return pmc->soc->num_io_pads; in tegra_io_pad_pinctrl_get_groups_count()
2013 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); in tegra_io_pad_pinctrl_get_group_name() local
2015 return pmc->soc->io_pads[group].name; in tegra_io_pad_pinctrl_get_group_name()
2023 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinctrl_get_group_pins() local
2025 *pins = &pmc->soc->io_pads[group].id; in tegra_io_pad_pinctrl_get_group_pins()
2043 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinconf_get() local
2048 pad = tegra_io_pad_find(pmc, pin); in tegra_io_pad_pinconf_get()
2054 ret = tegra_io_pad_get_voltage(pmc, pad->id); in tegra_io_pad_pinconf_get()
2062 ret = tegra_io_pad_is_powered(pmc, pad->id); in tegra_io_pad_pinconf_get()
2082 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinconf_set() local
2089 pad = tegra_io_pad_find(pmc, pin); in tegra_io_pad_pinconf_set()
2110 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); in tegra_io_pad_pinconf_set()
2133 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) in tegra_pmc_pinctrl_init() argument
2137 if (!pmc->soc->num_pin_descs) in tegra_pmc_pinctrl_init()
2140 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); in tegra_pmc_pinctrl_init()
2141 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; in tegra_pmc_pinctrl_init()
2142 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; in tegra_pmc_pinctrl_init()
2144 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, in tegra_pmc_pinctrl_init()
2145 pmc); in tegra_pmc_pinctrl_init()
2146 if (IS_ERR(pmc->pctl_dev)) { in tegra_pmc_pinctrl_init()
2147 err = PTR_ERR(pmc->pctl_dev); in tegra_pmc_pinctrl_init()
2148 dev_err(pmc->dev, "failed to register pin controller: %d\n", in tegra_pmc_pinctrl_init()
2161 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_reason_show()
2162 value &= pmc->soc->regs->rst_source_mask; in reset_reason_show()
2163 value >>= pmc->soc->regs->rst_source_shift; in reset_reason_show()
2165 if (WARN_ON(value >= pmc->soc->num_reset_sources)) in reset_reason_show()
2168 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); in reset_reason_show()
2178 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_level_show()
2179 value &= pmc->soc->regs->rst_level_mask; in reset_level_show()
2180 value >>= pmc->soc->regs->rst_level_shift; in reset_level_show()
2182 if (WARN_ON(value >= pmc->soc->num_reset_levels)) in reset_level_show()
2185 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); in reset_level_show()
2190 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) in tegra_pmc_reset_sysfs_init() argument
2192 struct device *dev = pmc->dev; in tegra_pmc_reset_sysfs_init()
2195 if (pmc->soc->reset_sources) { in tegra_pmc_reset_sysfs_init()
2203 if (pmc->soc->reset_levels) { in tegra_pmc_reset_sysfs_init()
2229 struct tegra_pmc *pmc = domain->host_data; in tegra_pmc_irq_alloc() local
2230 const struct tegra_pmc_soc *soc = pmc->soc; in tegra_pmc_irq_alloc()
2250 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
2254 /* simple hierarchies stop at the PMC level */ in tegra_pmc_irq_alloc()
2260 spec.fwnode = &pmc->dev->of_node->fwnode; in tegra_pmc_irq_alloc()
2280 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
2282 /* GPIO hierarchies stop at the PMC level */ in tegra_pmc_irq_alloc()
2290 /* If there is no wake-up event, there is no PMC mapping */ in tegra_pmc_irq_alloc()
2304 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra210_pmc_irq_set_wake() local
2312 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); in tegra210_pmc_irq_set_wake()
2313 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); in tegra210_pmc_irq_set_wake()
2315 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); in tegra210_pmc_irq_set_wake()
2316 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); in tegra210_pmc_irq_set_wake()
2318 /* enable PMC wake */ in tegra210_pmc_irq_set_wake()
2324 value = tegra_pmc_readl(pmc, offset); in tegra210_pmc_irq_set_wake()
2331 tegra_pmc_writel(pmc, value, offset); in tegra210_pmc_irq_set_wake()
2338 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra210_pmc_irq_set_type() local
2350 value = tegra_pmc_readl(pmc, offset); in tegra210_pmc_irq_set_type()
2371 tegra_pmc_writel(pmc, value, offset); in tegra210_pmc_irq_set_type()
2376 static void tegra186_pmc_set_wake_filters(struct tegra_pmc *pmc) in tegra186_pmc_set_wake_filters() argument
2381 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); in tegra186_pmc_set_wake_filters()
2383 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); in tegra186_pmc_set_wake_filters()
2384 dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value); in tegra186_pmc_set_wake_filters()
2389 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra186_pmc_irq_set_wake() local
2397 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2400 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2407 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2410 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2417 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra186_pmc_irq_set_type() local
2420 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2426 set_bit(data->hwirq, pmc->wake_type_level_map); in tegra186_pmc_irq_set_type()
2427 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); in tegra186_pmc_irq_set_type()
2433 clear_bit(data->hwirq, pmc->wake_type_level_map); in tegra186_pmc_irq_set_type()
2434 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); in tegra186_pmc_irq_set_type()
2439 clear_bit(data->hwirq, pmc->wake_type_level_map); in tegra186_pmc_irq_set_type()
2440 set_bit(data->hwirq, pmc->wake_type_dual_edge_map); in tegra186_pmc_irq_set_type()
2447 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2480 static int tegra_pmc_irq_init(struct tegra_pmc *pmc) in tegra_pmc_irq_init() argument
2485 np = of_irq_find_parent(pmc->dev->of_node); in tegra_pmc_irq_init()
2494 pmc->irq.name = dev_name(pmc->dev); in tegra_pmc_irq_init()
2495 pmc->irq.irq_mask = tegra_irq_mask_parent; in tegra_pmc_irq_init()
2496 pmc->irq.irq_unmask = tegra_irq_unmask_parent; in tegra_pmc_irq_init()
2497 pmc->irq.irq_eoi = tegra_irq_eoi_parent; in tegra_pmc_irq_init()
2498 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; in tegra_pmc_irq_init()
2499 pmc->irq.irq_set_type = pmc->soc->irq_set_type; in tegra_pmc_irq_init()
2500 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; in tegra_pmc_irq_init()
2502 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, in tegra_pmc_irq_init()
2503 &tegra_pmc_irq_domain_ops, pmc); in tegra_pmc_irq_init()
2504 if (!pmc->domain) { in tegra_pmc_irq_init()
2505 dev_err(pmc->dev, "failed to allocate domain\n"); in tegra_pmc_irq_init()
2515 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb); in tegra_pmc_clk_notify_cb() local
2520 mutex_lock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2524 pmc->rate = data->new_rate; in tegra_pmc_clk_notify_cb()
2528 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2541 tegra_pmc_readl(pmc, offset); in pmc_clk_fence_udelay()
2542 /* pmc clk propagation delay 2 us */ in pmc_clk_fence_udelay()
2551 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; in pmc_clk_mux_get_parent()
2562 val = tegra_pmc_readl(pmc, clk->offs); in pmc_clk_mux_set_parent()
2565 tegra_pmc_writel(pmc, val, clk->offs); in pmc_clk_mux_set_parent()
2576 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); in pmc_clk_is_enabled()
2585 val = tegra_pmc_readl(pmc, offs); in pmc_clk_set_state()
2587 tegra_pmc_writel(pmc, val, offs); in pmc_clk_set_state()
2617 tegra_pmc_clk_out_register(struct tegra_pmc *pmc, in tegra_pmc_clk_out_register() argument
2624 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); in tegra_pmc_clk_out_register()
2647 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; in pmc_clk_gate_is_enabled()
2673 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name, in tegra_pmc_clk_gate_register() argument
2680 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); in tegra_pmc_clk_gate_register()
2697 static void tegra_pmc_clock_register(struct tegra_pmc *pmc, in tegra_pmc_clock_register() argument
2705 num_clks = pmc->soc->num_pmc_clks; in tegra_pmc_clock_register()
2706 if (pmc->soc->has_blink_output) in tegra_pmc_clock_register()
2712 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); in tegra_pmc_clock_register()
2716 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, in tegra_pmc_clock_register()
2726 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { in tegra_pmc_clock_register()
2729 data = pmc->soc->pmc_clks_data + i; in tegra_pmc_clock_register()
2731 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL); in tegra_pmc_clock_register()
2733 dev_warn(pmc->dev, "unable to register clock %s: %d\n", in tegra_pmc_clock_register()
2740 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2749 if (pmc->soc->has_blink_output) { in tegra_pmc_clock_register()
2750 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); in tegra_pmc_clock_register()
2751 clk = tegra_pmc_clk_gate_register(pmc, in tegra_pmc_clock_register()
2757 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2763 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink", in tegra_pmc_clock_register()
2768 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2776 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2787 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", in tegra_pmc_clock_register()
2809 struct tegra_pmc *pmc = context; in tegra_pmc_regmap_readl() local
2811 *value = tegra_pmc_readl(pmc, offset); in tegra_pmc_regmap_readl()
2817 struct tegra_pmc *pmc = context; in tegra_pmc_regmap_writel() local
2819 tegra_pmc_writel(pmc, value, offset); in tegra_pmc_regmap_writel()
2835 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc) in tegra_pmc_regmap_init() argument
2840 if (pmc->soc->has_usb_sleepwalk) { in tegra_pmc_regmap_init()
2841 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config); in tegra_pmc_regmap_init()
2844 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err); in tegra_pmc_regmap_init()
2854 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; in tegra_pmc_reset_suspend_mode()
2868 if (WARN_ON(!pmc->base || !pmc->soc)) in tegra_pmc_probe()
2871 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2885 if (pmc->soc->has_single_mmio_aperture) { in tegra_pmc_probe()
2886 pmc->wake = base; in tegra_pmc_probe()
2887 pmc->aotag = base; in tegra_pmc_probe()
2888 pmc->scratch = base; in tegra_pmc_probe()
2890 pmc->wake = devm_platform_ioremap_resource_byname(pdev, "wake"); in tegra_pmc_probe()
2891 if (IS_ERR(pmc->wake)) in tegra_pmc_probe()
2892 return PTR_ERR(pmc->wake); in tegra_pmc_probe()
2894 pmc->aotag = devm_platform_ioremap_resource_byname(pdev, "aotag"); in tegra_pmc_probe()
2895 if (IS_ERR(pmc->aotag)) in tegra_pmc_probe()
2896 return PTR_ERR(pmc->aotag); in tegra_pmc_probe()
2902 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2903 if (IS_ERR(pmc->scratch)) in tegra_pmc_probe()
2904 return PTR_ERR(pmc->scratch); in tegra_pmc_probe()
2906 pmc->scratch = NULL; in tegra_pmc_probe()
2910 pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk"); in tegra_pmc_probe()
2911 if (IS_ERR(pmc->clk)) in tegra_pmc_probe()
2912 return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk), in tegra_pmc_probe()
2916 * PMC should be last resort for restarting since it soft-resets in tegra_pmc_probe()
2919 if (pmc->scratch) { in tegra_pmc_probe()
2941 * PMC should be primary power-off method if it soft-resets CPU, in tegra_pmc_probe()
2959 if (pmc->clk) { in tegra_pmc_probe()
2960 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; in tegra_pmc_probe()
2961 err = devm_clk_notifier_register(&pdev->dev, pmc->clk, in tegra_pmc_probe()
2962 &pmc->clk_nb); in tegra_pmc_probe()
2969 pmc->rate = clk_get_rate(pmc->clk); in tegra_pmc_probe()
2972 pmc->dev = &pdev->dev; in tegra_pmc_probe()
2974 err = tegra_pmc_init(pmc); in tegra_pmc_probe()
2976 dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err); in tegra_pmc_probe()
2980 tegra_pmc_init_tsense_reset(pmc); in tegra_pmc_probe()
2982 tegra_pmc_reset_sysfs_init(pmc); in tegra_pmc_probe()
2984 err = tegra_pmc_pinctrl_init(pmc); in tegra_pmc_probe()
2988 err = tegra_pmc_regmap_init(pmc); in tegra_pmc_probe()
2992 err = tegra_powergate_init(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2996 err = tegra_pmc_irq_init(pmc); in tegra_pmc_probe()
3000 mutex_lock(&pmc->powergates_lock); in tegra_pmc_probe()
3001 iounmap(pmc->base); in tegra_pmc_probe()
3002 pmc->base = base; in tegra_pmc_probe()
3003 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_probe()
3005 tegra_pmc_clock_register(pmc, pdev->dev.of_node); in tegra_pmc_probe()
3006 platform_set_drvdata(pdev, pmc); in tegra_pmc_probe()
3010 if (pmc->soc->set_wake_filters) in tegra_pmc_probe()
3011 pmc->soc->set_wake_filters(pmc); in tegra_pmc_probe()
3030 static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset) in wke_32kwritel() argument
3032 writel(value, pmc->wake + offset); in wke_32kwritel()
3036 static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level) in wke_write_wake_level() argument
3041 value = readl(pmc->wake + offset); in wke_write_wake_level()
3047 writel(value, pmc->wake + offset); in wke_write_wake_level()
3050 static void wke_write_wake_levels(struct tegra_pmc *pmc) in wke_write_wake_levels() argument
3054 for (i = 0; i < pmc->soc->max_wake_events; i++) in wke_write_wake_levels()
3055 wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map)); in wke_write_wake_levels()
3058 static void wke_clear_sw_wake_status(struct tegra_pmc *pmc) in wke_clear_sw_wake_status() argument
3060 wke_32kwritel(pmc, 1, WAKE_AOWAKE_SW_STATUS_W_0); in wke_clear_sw_wake_status()
3063 static void wke_read_sw_wake_status(struct tegra_pmc *pmc) in wke_read_sw_wake_status() argument
3068 for (i = 0; i < pmc->soc->max_wake_events; i++) in wke_read_sw_wake_status()
3069 wke_write_wake_level(pmc, i, 0); in wke_read_sw_wake_status()
3071 wke_clear_sw_wake_status(pmc); in wke_read_sw_wake_status()
3073 wke_32kwritel(pmc, 1, WAKE_LATCH_SW); in wke_read_sw_wake_status()
3081 for (i = 0; i < pmc->soc->max_wake_events; i++) in wke_read_sw_wake_status()
3082 wke_write_wake_level(pmc, i, 1); in wke_read_sw_wake_status()
3091 wke_32kwritel(pmc, 0, WAKE_LATCH_SW); in wke_read_sw_wake_status()
3093 bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events); in wke_read_sw_wake_status()
3095 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { in wke_read_sw_wake_status()
3096 status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i)); in wke_read_sw_wake_status()
3099 set_bit(wake + (i * 32), pmc->wake_sw_status_map); in wke_read_sw_wake_status()
3103 static void wke_clear_wake_status(struct tegra_pmc *pmc) in wke_clear_wake_status() argument
3109 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { in wke_clear_wake_status()
3110 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); in wke_clear_wake_status()
3111 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; in wke_clear_wake_status()
3114 wke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W((i * 32) + wake)); in wke_clear_wake_status()
3119 static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int index, in tegra186_pmc_process_wake_events() argument
3124 dev_dbg(pmc->dev, "Wake[%d:%d] status=%#lx\n", (index * 32) + 31, index * 32, status); in tegra186_pmc_process_wake_events()
3131 irq = irq_find_mapping(pmc->domain, hwirq); in tegra186_pmc_process_wake_events()
3135 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, IRQ %d\n", hwirq, irq); in tegra186_pmc_process_wake_events()
3139 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, %s\n", hwirq, desc->action->name); in tegra186_pmc_process_wake_events()
3149 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { in tegra186_pmc_wake_syscore_resume()
3150 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); in tegra186_pmc_wake_syscore_resume()
3151 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; in tegra186_pmc_wake_syscore_resume()
3153 tegra186_pmc_process_wake_events(pmc, i, status); in tegra186_pmc_wake_syscore_resume()
3159 wke_read_sw_wake_status(pmc); in tegra186_pmc_wake_syscore_suspend()
3164 bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map, in tegra186_pmc_wake_syscore_suspend()
3165 pmc->wake_sw_status_map, pmc->soc->max_wake_events); in tegra186_pmc_wake_syscore_suspend()
3166 bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map, in tegra186_pmc_wake_syscore_suspend()
3167 pmc->wake_type_level_map, pmc->soc->max_wake_events); in tegra186_pmc_wake_syscore_suspend()
3169 /* Clear PMC Wake Status registers while going to suspend */ in tegra186_pmc_wake_syscore_suspend()
3170 wke_clear_wake_status(pmc); in tegra186_pmc_wake_syscore_suspend()
3171 wke_write_wake_levels(pmc); in tegra186_pmc_wake_syscore_suspend()
3179 struct tegra_pmc *pmc = dev_get_drvdata(dev); in tegra_pmc_suspend() local
3181 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); in tegra_pmc_suspend()
3188 struct tegra_pmc *pmc = dev_get_drvdata(dev); in tegra_pmc_resume() local
3190 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); in tegra_pmc_resume()
3218 static void tegra20_pmc_init(struct tegra_pmc *pmc) in tegra20_pmc_init() argument
3223 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_init()
3225 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_init()
3227 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_init()
3229 if (pmc->sysclkreq_high) in tegra20_pmc_init()
3234 if (pmc->corereq_high) in tegra20_pmc_init()
3240 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_init()
3243 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_init()
3245 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_init()
3248 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { in tegra20_pmc_init()
3249 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); in tegra20_pmc_init()
3250 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); in tegra20_pmc_init()
3251 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); in tegra20_pmc_init()
3252 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), in tegra20_pmc_init()
3254 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); in tegra20_pmc_init()
3258 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, in tegra20_pmc_setup_irq_polarity() argument
3264 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_setup_irq_polarity()
3271 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_setup_irq_polarity()
3824 static void tegra186_pmc_init(struct tegra_pmc *pmc) in tegra186_pmc_init() argument
3826 pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend; in tegra186_pmc_init()
3827 pmc->syscore.resume = tegra186_pmc_wake_syscore_resume; in tegra186_pmc_init()
3829 register_syscore_ops(&pmc->syscore); in tegra186_pmc_init()
3832 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, in tegra186_pmc_setup_irq_polarity() argument
3843 dev_err(pmc->dev, "failed to find PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3851 dev_err(pmc->dev, "failed to map PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
4250 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
4251 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
4252 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
4253 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
4254 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
4255 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
4256 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
4257 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
4258 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
4271 if (!pmc->soc->supports_core_domain) in tegra_pmc_sync_state()
4279 if (!pmc->core_domain_registered) in tegra_pmc_sync_state()
4282 pmc->core_domain_state_synced = true; in tegra_pmc_sync_state()
4285 mutex_lock(&pmc->powergates_lock); in tegra_pmc_sync_state()
4287 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_sync_state()
4295 .name = "tegra-pmc",
4307 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) in tegra_pmc_detect_tz_only() argument
4311 saved = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4318 writel(value, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4319 value = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4323 pr_info("access to PMC is restricted to TZ\n"); in tegra_pmc_detect_tz_only()
4328 writel(saved, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4345 mutex_init(&pmc->powergates_lock); in tegra_pmc_early_init()
4352 * a PMC node. in tegra_pmc_early_init()
4355 * that didn't contain a PMC node. Note that in this case the in tegra_pmc_early_init()
4380 pr_err("failed to get PMC registers\n"); in tegra_pmc_early_init()
4386 pmc->base = ioremap(regs.start, resource_size(®s)); in tegra_pmc_early_init()
4387 if (!pmc->base) { in tegra_pmc_early_init()
4388 pr_err("failed to map PMC registers\n"); in tegra_pmc_early_init()
4394 pmc->soc = match->data; in tegra_pmc_early_init()
4396 if (pmc->soc->maybe_tz_only) in tegra_pmc_early_init()
4397 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); in tegra_pmc_early_init()
4400 for (i = 0; i < pmc->soc->num_powergates; i++) in tegra_pmc_early_init()
4401 if (pmc->soc->powergates[i]) in tegra_pmc_early_init()
4402 set_bit(i, pmc->powergates_available); in tegra_pmc_early_init()
4405 * Invert the interrupt polarity if a PMC device tree node in tegra_pmc_early_init()
4410 pmc->soc->setup_irq_polarity(pmc, np, invert); in tegra_pmc_early_init()