Lines Matching +full:0 +full:xf08
9 #define MT8188_VDO0_SW0_RST_B 0x190
10 #define MT8188_VDO0_OVL_MOUT_EN 0xf14
11 #define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
18 #define MT8188_VDO0_SEL_IN 0xf34
19 #define MT8188_VDO0_SEL_OUT 0xf38
21 #define MT8188_VDO0_DISP_RDMA_SEL 0xf40
22 #define MT8188_SOUT_DISP_RDMA0_TO_MASK GENMASK(2, 0)
23 #define MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0 (0 << 0)
24 #define MT8188_SOUT_DISP_RDMA0_TO_DISP_DSI0 (1 << 0)
25 #define MT8188_SOUT_DISP_RDMA0_TO_DISP_DP_INTF0 (5 << 0)
27 #define MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0 (0 << 8)
31 #define MT8188_VDO0_DSI0_SEL_IN 0xf44
32 #define MT8188_SEL_IN_DSI0_FROM_MASK BIT(0)
33 #define MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 0)
34 #define MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 0)
36 #define MT8188_VDO0_DP_INTF0_SEL_IN 0xf4C
37 #define MT8188_SEL_IN_DP_INTF0_FROM_MASK GENMASK(2, 0)
38 #define MT8188_SEL_IN_DP_INTF0_FROM_DSC_WRAP0C1_OUT (0 << 0)
39 #define MT8188_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 0)
40 #define MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0 (3 << 0)
42 #define MT8188_VDO0_DISP_DITHER0_SEL_OUT 0xf58
43 #define MT8188_SOUT_DISP_DITHER0_TO_MASK GENMASK(2, 0)
44 #define MT8188_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
45 #define MT8188_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
46 #define MT8188_SOUT_DISP_DITHER0_TO_VPP_MERGE0 (6 << 0)
47 #define MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0 (7 << 0)
49 #define MT8188_VDO0_VPP_MERGE_SEL 0xf60
50 #define MT8188_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
51 #define MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
52 #define MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT (3 << 0)
55 #define MT8188_SOUT_VPP_MERGE_TO_DSI1 (0 << 4)
62 #define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
64 #define MT8188_VDO0_DSC_WARP_SEL 0xf64
65 #define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK GENMASK(0, 0)
66 #define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0 (0 << 0)
67 #define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_VPP_MERGE (1 << 0)
74 #define MT8188_VDO1_SW0_RST_B 0x1d0
75 #define MT8188_VDO1_HDR_TOP_CFG 0xd00
76 #define MT8188_VDO1_MIXER_IN1_ALPHA 0xd30
77 #define MT8188_VDO1_MIXER_IN1_PAD 0xd40
78 #define MT8188_VDO1_MIXER_VSYNC_LEN 0xd5c
79 #define MT8188_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
80 #define MT8188_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
81 #define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
83 #define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
85 #define MT8188_VDO1_DISP_DPI1_SEL_IN 0xf10
86 #define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0
87 #define MT8188_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
88 #define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0
89 #define MT8188_VDO1_MERGE4_SOUT_SEL 0xf18
92 #define MT8188_VDO1_MIXER_IN1_SEL_IN 0xf24
94 #define MT8188_VDO1_MIXER_IN2_SEL_IN 0xf28
96 #define MT8188_VDO1_MIXER_IN3_SEL_IN 0xf2c
98 #define MT8188_VDO1_MIXER_IN4_SEL_IN 0xf30
100 #define MT8188_VDO1_MIXER_OUT_SOUT_SEL 0xf34
102 #define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
104 #define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
106 #define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
108 #define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
110 #define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
112 #define MT8188_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
114 #define MT8188_VDO1_MIXER_IN1_SOUT_SEL 0xf58
115 #define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER 0
116 #define MT8188_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
117 #define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER 0
118 #define MT8188_VDO1_MIXER_IN3_SOUT_SEL 0xf60
119 #define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER 0
120 #define MT8188_VDO1_MIXER_IN4_SOUT_SEL 0xf64
121 #define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER 0
122 #define MT8188_VDO1_MIXER_SOUT_SEL_IN 0xf68
123 #define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0
126 [MT8188_VDO0_RST_DISP_OVL0] = MMSYS_RST_NR(0, 0),
127 [MT8188_VDO0_RST_FAKE_ENG0] = MMSYS_RST_NR(0, 2),
128 [MT8188_VDO0_RST_DISP_CCORR0] = MMSYS_RST_NR(0, 4),
129 [MT8188_VDO0_RST_DISP_MUTEX0] = MMSYS_RST_NR(0, 6),
130 [MT8188_VDO0_RST_DISP_GAMMA0] = MMSYS_RST_NR(0, 8),
131 [MT8188_VDO0_RST_DISP_DITHER0] = MMSYS_RST_NR(0, 10),
132 [MT8188_VDO0_RST_DISP_WDMA0] = MMSYS_RST_NR(0, 17),
133 [MT8188_VDO0_RST_DISP_RDMA0] = MMSYS_RST_NR(0, 19),
134 [MT8188_VDO0_RST_DSI0] = MMSYS_RST_NR(0, 21),
135 [MT8188_VDO0_RST_DSI1] = MMSYS_RST_NR(0, 22),
136 [MT8188_VDO0_RST_DSC_WRAP0] = MMSYS_RST_NR(0, 23),
137 [MT8188_VDO0_RST_VPP_MERGE0] = MMSYS_RST_NR(0, 24),
138 [MT8188_VDO0_RST_DP_INTF0] = MMSYS_RST_NR(0, 25),
139 [MT8188_VDO0_RST_DISP_AAL0] = MMSYS_RST_NR(0, 26),
140 [MT8188_VDO0_RST_INLINEROT0] = MMSYS_RST_NR(0, 27),
141 [MT8188_VDO0_RST_APB_BUS] = MMSYS_RST_NR(0, 28),
142 [MT8188_VDO0_RST_DISP_COLOR0] = MMSYS_RST_NR(0, 29),
143 [MT8188_VDO0_RST_MDP_WROT0] = MMSYS_RST_NR(0, 30),
144 [MT8188_VDO0_RST_DISP_RSZ0] = MMSYS_RST_NR(0, 31),
148 [MT8188_VDO1_RST_SMI_LARB2] = MMSYS_RST_NR(0, 0),
149 [MT8188_VDO1_RST_SMI_LARB3] = MMSYS_RST_NR(0, 1),
150 [MT8188_VDO1_RST_GALS] = MMSYS_RST_NR(0, 2),
151 [MT8188_VDO1_RST_FAKE_ENG0] = MMSYS_RST_NR(0, 3),
152 [MT8188_VDO1_RST_FAKE_ENG1] = MMSYS_RST_NR(0, 4),
153 [MT8188_VDO1_RST_MDP_RDMA0] = MMSYS_RST_NR(0, 5),
154 [MT8188_VDO1_RST_MDP_RDMA1] = MMSYS_RST_NR(0, 6),
155 [MT8188_VDO1_RST_MDP_RDMA2] = MMSYS_RST_NR(0, 7),
156 [MT8188_VDO1_RST_MDP_RDMA3] = MMSYS_RST_NR(0, 8),
157 [MT8188_VDO1_RST_VPP_MERGE0] = MMSYS_RST_NR(0, 9),
158 [MT8188_VDO1_RST_VPP_MERGE1] = MMSYS_RST_NR(0, 10),
159 [MT8188_VDO1_RST_VPP_MERGE2] = MMSYS_RST_NR(0, 11),
160 [MT8188_VDO1_RST_VPP_MERGE3] = MMSYS_RST_NR(1, 0),
191 [MT8188_VDO1_RST_HDR_VDO_FE0] = MMSYS_RST_NR(2, 0),
286 MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
290 MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
294 MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
298 MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
302 MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
306 MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
310 MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
314 MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
318 MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
322 MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
326 MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
330 MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
334 MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
338 MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
342 MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
346 MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
350 MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
354 MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),