1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <linux/gpio/legacy-of-mm-gpiochip.h>
23 #include <soc/fsl/qe/qe.h>
40 	struct qe_pio_regs __iomem *regs = mm_gc->regs;  in qe_gpio_save_regs()
42 	qe_gc->cpdata = ioread32be(&regs->cpdata);  in qe_gpio_save_regs()
43 	qe_gc->saved_regs.cpdata = qe_gc->cpdata;  in qe_gpio_save_regs()
44 	qe_gc->saved_regs.cpdir1 = ioread32be(&regs->cpdir1);  in qe_gpio_save_regs()
45 	qe_gc->saved_regs.cpdir2 = ioread32be(&regs->cpdir2);  in qe_gpio_save_regs()
46 	qe_gc->saved_regs.cppar1 = ioread32be(&regs->cppar1);  in qe_gpio_save_regs()
47 	qe_gc->saved_regs.cppar2 = ioread32be(&regs->cppar2);  in qe_gpio_save_regs()
48 	qe_gc->saved_regs.cpodr = ioread32be(&regs->cpodr);  in qe_gpio_save_regs()
54 	struct qe_pio_regs __iomem *regs = mm_gc->regs;  in qe_gpio_get()
55 	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);  in qe_gpio_get()
57 	return !!(ioread32be(&regs->cpdata) & pin_mask);  in qe_gpio_get()
64 	struct qe_pio_regs __iomem *regs = mm_gc->regs;  in qe_gpio_set()
66 	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);  in qe_gpio_set()
68 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_gpio_set()
71 		qe_gc->cpdata |= pin_mask;  in qe_gpio_set()
73 		qe_gc->cpdata &= ~pin_mask;  in qe_gpio_set()
75 	iowrite32be(qe_gc->cpdata, &regs->cpdata);  in qe_gpio_set()
77 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_gpio_set()
85 	struct qe_pio_regs __iomem *regs = mm_gc->regs;  in qe_gpio_set_multiple()
89 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_gpio_set_multiple()
91 	for (i = 0; i < gc->ngpio; i++) {  in qe_gpio_set_multiple()
96 				qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i));  in qe_gpio_set_multiple()
98 				qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i));  in qe_gpio_set_multiple()
102 	iowrite32be(qe_gc->cpdata, &regs->cpdata);  in qe_gpio_set_multiple()
104 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_gpio_set_multiple()
113 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_gpio_dir_in()
115 	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);  in qe_gpio_dir_in()
117 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_gpio_dir_in()
130 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_gpio_dir_out()
132 	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);  in qe_gpio_dir_out()
134 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_gpio_dir_out()
149  * qe_pin_request - Request a QE pin
152  * Context:	non-atomic
155  * the QE Pin Multiplexing API.
168 		return ERR_PTR(-ENOMEM);  in qe_pin_request()
188 		err = -ENODEV;  in qe_pin_request()
192 	qe_pin->controller = gpiochip_get_data(gc);  in qe_pin_request()
198 	qe_pin->num = gpio_num - gc->base;  in qe_pin_request()
200 	if (!fwnode_device_is_compatible(gc->fwnode, "fsl,mpc8323-qe-pario-bank")) {  in qe_pin_request()
201 		dev_dbg(dev, "%s: tried to get a non-qe pin\n", __func__);  in qe_pin_request()
202 		err = -EINVAL;  in qe_pin_request()
214  * qe_pin_free - Free a pin
228  * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
233  * has been set up by the firmware.
237 	struct qe_gpio_chip *qe_gc = qe_pin->controller;  in qe_pin_set_dedicated()
238 	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;  in qe_pin_set_dedicated()
239 	struct qe_pio_regs *sregs = &qe_gc->saved_regs;  in qe_pin_set_dedicated()
240 	int pin = qe_pin->num;  in qe_pin_set_dedicated()
241 	u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));  in qe_pin_set_dedicated()
242 	u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);  in qe_pin_set_dedicated()
243 	bool second_reg = pin > (QE_PIO_PINS / 2) - 1;  in qe_pin_set_dedicated()
246 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_pin_set_dedicated()
249 		qe_clrsetbits_be32(&regs->cpdir2, mask2,  in qe_pin_set_dedicated()
250 				   sregs->cpdir2 & mask2);  in qe_pin_set_dedicated()
251 		qe_clrsetbits_be32(&regs->cppar2, mask2,  in qe_pin_set_dedicated()
252 				   sregs->cppar2 & mask2);  in qe_pin_set_dedicated()
254 		qe_clrsetbits_be32(&regs->cpdir1, mask2,  in qe_pin_set_dedicated()
255 				   sregs->cpdir1 & mask2);  in qe_pin_set_dedicated()
256 		qe_clrsetbits_be32(&regs->cppar1, mask2,  in qe_pin_set_dedicated()
257 				   sregs->cppar1 & mask2);  in qe_pin_set_dedicated()
260 	if (sregs->cpdata & mask1)  in qe_pin_set_dedicated()
261 		qe_gc->cpdata |= mask1;  in qe_pin_set_dedicated()
263 		qe_gc->cpdata &= ~mask1;  in qe_pin_set_dedicated()
265 	iowrite32be(qe_gc->cpdata, &regs->cpdata);  in qe_pin_set_dedicated()
266 	qe_clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);  in qe_pin_set_dedicated()
268 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_pin_set_dedicated()
273  * qe_pin_set_gpio - Set a pin to the GPIO mode
281 	struct qe_gpio_chip *qe_gc = qe_pin->controller;  in qe_pin_set_gpio()
282 	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;  in qe_pin_set_gpio()
285 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_pin_set_gpio()
288 	__par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);  in qe_pin_set_gpio()
290 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_pin_set_gpio()
298 	for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {  in qe_add_gpiochips()
306 			ret = -ENOMEM;  in qe_add_gpiochips()
310 		spin_lock_init(&qe_gc->lock);  in qe_add_gpiochips()
312 		mm_gc = &qe_gc->mm_gc;  in qe_add_gpiochips()
313 		gc = &mm_gc->gc;  in qe_add_gpiochips()
315 		mm_gc->save_regs = qe_gpio_save_regs;  in qe_add_gpiochips()
316 		gc->ngpio = QE_PIO_PINS;  in qe_add_gpiochips()
317 		gc->direction_input = qe_gpio_dir_in;  in qe_add_gpiochips()
318 		gc->direction_output = qe_gpio_dir_out;  in qe_add_gpiochips()
319 		gc->get = qe_gpio_get;  in qe_add_gpiochips()
320 		gc->set = qe_gpio_set;  in qe_add_gpiochips()
321 		gc->set_multiple = qe_gpio_set_multiple;  in qe_add_gpiochips()