45 	IMR0	= 0x10,	/* MU_INBOUND_MESSAGE_REG0 */
46 	IMR1	= 0x14,	/* MU_INBOUND_MESSAGE_REG1 */
47 	OMR0	= 0x18,	/* MU_OUTBOUND_MESSAGE_REG0 */
48 	OMR1	= 0x1c,	/* MU_OUTBOUND_MESSAGE_REG1 */
49 	IDBL	= 0x20,	/* MU_INBOUND_DOORBELL */
50 	IIS	= 0x24,	/* MU_INBOUND_INTERRUPT_STATUS */
51 	IIM	= 0x28,	/* MU_INBOUND_INTERRUPT_MASK */
52 	ODBL	= 0x2c,	/* MU_OUTBOUND_DOORBELL */
53 	OIS	= 0x30,	/* MU_OUTBOUND_INTERRUPT_STATUS */
54 	OIM	= 0x3c,	/* MU_OUTBOUND_INTERRUPT_MASK */
56 	YIOA_STATUS				= 0x00,
57 	YH2I_INT				= 0x20,
58 	YINT_EN					= 0x34,
59 	YI2H_INT				= 0x9c,
60 	YI2H_INT_C				= 0xa0,
61 	YH2I_REQ				= 0xc0,
62 	YH2I_REQ_HI				= 0xc4,
63 	PSCRATCH0				= 0xb0,
64 	PSCRATCH1				= 0xb4,
65 	PSCRATCH2				= 0xb8,
66 	PSCRATCH3				= 0xbc,
67 	PSCRATCH4				= 0xc8,
68 	MAILBOX_BASE			= 0x1000,
69 	MAILBOX_HNDSHK_STS		= 0x0,
72 	MU_INBOUND_DOORBELL_HANDSHAKE		= (1 << 0),
78 	MU_OUTBOUND_DOORBELL_HANDSHAKE		= (1 << 0),
94 	MU_HANDSHAKE_SIGNATURE			= 0x55aaaa55,
95 	MU_HANDSHAKE_SIGNATURE_HALF		= 0x5a5a0000,
100 	SRB_STATUS_SUCCESS			= 0x01,
101 	SRB_STATUS_ERROR			= 0x04,
102 	SRB_STATUS_BUSY				= 0x05,
103 	SRB_STATUS_INVALID_REQUEST		= 0x06,
104 	SRB_STATUS_SELECTION_TIMEOUT		= 0x0A,
105 	SRB_SEE_SENSE 				= 0x80,
108 	TASK_ATTRIBUTE_SIMPLE			= 0x0,
109 	TASK_ATTRIBUTE_HEADOFQUEUE		= 0x1,
110 	TASK_ATTRIBUTE_ORDERED			= 0x2,
111 	TASK_ATTRIBUTE_ACA			= 0x4,
115 	SS_STS_NORMAL				= 0x80000000,
116 	SS_STS_DONE				= 0x40000000,
117 	SS_STS_HANDSHAKE			= 0x20000000,
119 	SS_HEAD_HANDSHAKE			= 0x80,
121 	SS_H2I_INT_RESET			= 0x100,
123 	SS_I2H_REQUEST_RESET			= 0x2000,
125 	SS_MU_OPERATIONAL			= 0x80000000,
133 	SG_CF_EOT				= 0x80,	/* end of table */
134 	SG_CF_64B				= 0x40,	/* 64 bit item */
135 	SG_CF_HOST				= 0x20,	/* sg in host memory */
136 	MSG_DATA_DIR_ND				= 0,
140 	st_shasta				= 0,
147 	PASSTHRU_REQ_TYPE			= 0x00000001,
148 	PASSTHRU_REQ_NO_WAKEUP			= 0x00000100,
151 	ST_TO_CMD				= 0,
155 	MGT_CMD					= 0xd8,
156 	SINBAND_MGT_CMD				= 0xd9,
157 	ARRAY_CMD				= 0xe0,
158 	CONTROLLER_CMD				= 0xe1,
159 	DEBUGGING_CMD				= 0xe2,
160 	PASSTHRU_CMD				= 0xe3,
162 	PASSTHRU_GET_ADAPTER			= 0x05,
163 	PASSTHRU_GET_DRVVER			= 0x10,
165 	CTLR_CONFIG_CMD				= 0x03,
166 	CTLR_SHUTDOWN				= 0x0d,
168 	CTLR_POWER_STATE_CHANGE			= 0x0e,
169 	CTLR_POWER_SAVING			= 0x01,
171 	PASSTHRU_SIGNATURE			= 0x4e415041,
172 	MGT_CMD_SIGNATURE			= 0xba,
174 	INQUIRY_EVPD				= 0x01,
176 	ST_ADDITIONAL_MEM			= 0x200000,
177 	ST_ADDITIONAL_MEM_MIN			= 0x80000,
178 	PMIC_SHUTDOWN				= 0x0D,
179 	PMIC_REUMSE					= 0x10,
367 	stex_halt, NULL, 0
371 module_param(msi, int, 0);
372 MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
376 	0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
377 	0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,	/* "Promise " */
378 	0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,	/* "RAID Con" */
379 	0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,	/* "sole    " */
380 	0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,	/* "1.00    " */
381 	0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,	/* "SX/RSAF-" */
382 	0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,	/* "TE1.00  " */
383 	0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
405 	scsi_build_sense(cmd, 0, ILLEGAL_REQUEST, 0x24, 0x0);  in stex_invalid_field()
436 	BUG_ON(nseg < 0);  in stex_map_sg()
468 	BUG_ON(nseg < 0);  in stex_ss_map_sg()
481 				cpu_to_le32(sg_dma_address(sg) & 0xffffffff);  in stex_ss_map_sg()
497 	memset(p->base, 0, sizeof(u32)*6);  in stex_controller_info()
498 	*(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);  in stex_controller_info()
499 	p->rom_addr = 0;  in stex_controller_info()
508 	p->irq_level = 0;  in stex_controller_info()
572 	for (tag = 0; tag < hba->host->can_queue; tag++) {  in return_abnormal_state()
593 	return 0;  in stex_sdev_configure()
608 	hba = (struct st_hba *) &host->hostdata[0];  in stex_queuecommand_lck()
612 		return 0;  in stex_queuecommand_lck()
617 	switch (cmd->cmnd[0]) {  in stex_queuecommand_lck()
621 			{ 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };  in stex_queuecommand_lck()
624 		page = cmd->cmnd[2] & 0x3f;  in stex_queuecommand_lck()
625 		if (page == 0x8 || page == 0x3f) {  in stex_queuecommand_lck()
632 		return 0;  in stex_queuecommand_lck()
642 			return 0;  in stex_queuecommand_lck()
649 			return 0;  in stex_queuecommand_lck()
656 			return 0;  in stex_queuecommand_lck()
661 			(cmd->cmnd[1] & INQUIRY_EVPD) == 0) {  in stex_queuecommand_lck()
668 		return 0;  in stex_queuecommand_lck()
676 				.signature[0] = PASSTHRU_SIGNATURE,  in stex_queuecommand_lck()
688 			return 0;  in stex_queuecommand_lck()
720 		hba->ccb[tag].sg_count = 0;  in stex_queuecommand_lck()
721 		memset(&req->variable[0], 0, 8);  in stex_queuecommand_lck()
725 	return 0;  in stex_queuecommand_lck()
735 	if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {  in DEF_SCSI_QCMD()
790 	if (ccb->cmd->cmnd[0] == MGT_CMD &&  in stex_check_cmd()
793 			le32_to_cpu(*(__le32 *)&resp->variable[0]));  in stex_check_cmd()
823 	if (unlikely(hba->out_req_cnt <= 0 ||  in stex_mu_intr()
868 			if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&  in stex_mu_intr()
875 			ccb->req_type = 0;  in stex_mu_intr()
894 	if (data && data != 0xffffffff) {  in stex_intr()
917 	int count = 0;  in stex_ss_mu_intr()
921 	if (unlikely(hba->out_req_cnt <= 0 ||  in stex_ss_mu_intr()
932 		*scratch = 0;  in stex_ss_mu_intr()
980 			ccb->req_type = 0;  in stex_ss_mu_intr()
995 		if (data && data != 0xffffffff) {  in stex_ss_intr()
1006 		if (data != 0xffffffff) {  in stex_ss_intr()
1007 			if (data != 0) {  in stex_ss_intr()
1052 	if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {  in stex_common_handshake()
1053 		data &= 0x0000ffff;  in stex_common_handshake()
1072 		h->extra_offset = h->extra_size = 0;  in stex_common_handshake()
1098 	writel(0, base + IMR0);  in stex_common_handshake()
1100 	writel(0, base + OMR0);  in stex_common_handshake()
1102 	writel(0, base + IMR1);  in stex_common_handshake()
1104 	writel(0, base + OMR1);  in stex_common_handshake()
1106 	return 0;  in stex_common_handshake()
1117 	int ret = 0;  in stex_ss_handshake()
1159 	h->extra_offset = h->extra_size = 0;  in stex_ss_handshake()
1173 		data &= ~(1 << 0);  in stex_ss_handshake()
1176 		if (hba->msi_lock == 0) {  in stex_ss_handshake()
1214 	memset(scratch, 0, scratch_size);  in stex_ss_handshake()
1215 	msg_h->flag = 0;  in stex_ss_handshake()
1232 	if (err == 0) {  in stex_handshake()
1233 		hba->req_head = 0;  in stex_handshake()
1234 		hba->req_tail = 0;  in stex_handshake()
1235 		hba->status_head = 0;  in stex_handshake()
1236 		hba->status_tail = 0;  in stex_handshake()
1237 		hba->out_req_cnt = 0;  in stex_handshake()
1269 		if (data == 0 || data == 0xffffffff)  in stex_abort()
1276 		if (data == 0xffffffff)  in stex_abort()
1278 		if (data != 0) {  in stex_abort()
1285 		if (data == 0 || data == 0xffffffff)  in stex_abort()
1315 	for (i = 0; i < 16; i++)  in stex_hard_reset()
1334 	for (i = 0; i < MU_HARD_RESET_WAIT; i++) {  in stex_hard_reset()
1336 		if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))  in stex_hard_reset()
1342 	for (i = 0; i < 16; i++)  in stex_hard_reset()
1351 	int ret = 0;  in stex_yos_reset()
1357 	while (hba->out_req_cnt > 0) {  in stex_yos_reset()
1401 		return 0;  in stex_do_reset()
1414 		return (mu_status == MU_STATE_STARTED) ? 0 : -1;  in stex_do_reset()
1432 	if (stex_handshake(hba) == 0)  in stex_do_reset()
1433 		return 0;  in stex_do_reset()
1444 	hba = (struct st_hba *) &cmd->device->host->hostdata[0];  in stex_reset()
1464 	if (capacity < 0x200000) {  in stex_biosparam()
1471 	geom[0] = heads;  in stex_biosparam()
1475 	return 0;  in stex_biosparam()
1493 	{ 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1495 	{ 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1497 	{ 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1499 	{ 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1503 	{ 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1506 	{ 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
1509 	{ 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1512 	{ 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1513 	{ 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
1516 	{ PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
1517 		0x8870, 0, 0, st_P3 },
1519 	{ PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
1520 		0x4300, 0, 0, st_P3 },
1523 	{ PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1524 		0x4311, 0, 0, st_P3 },
1526 	{ PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1527 		0x4312, 0, 0, st_P3 },
1529 	{ PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1530 		0x4321, 0, 0, st_P3 },
1532 	{ PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1533 		0x4322, 0, 0, st_P3 },
1542 		.max_channel	= 0,
1555 		.max_channel	= 0,
1568 		.max_channel	= 0,
1581 		.max_channel	= 0,
1607 		.max_channel	= 0,
1624 		if (status != 0)  in stex_request_irq()
1631 		hba->msi_enabled = 0;  in stex_request_irq()
1637 	if (status != 0) {  in stex_request_irq()
1667 	S6flag = 0;  in stex_probe()
1680 	memset(hba, 0, sizeof(struct st_hba));  in stex_probe()
1683 	if (err < 0) {  in stex_probe()
1689 	hba->mmio_base = pci_ioremap_bar(pdev, 0);  in stex_probe()
1709 	case 0x4221:  in stex_probe()
1710 	case 0x4222:  in stex_probe()
1711 	case 0x4223:  in stex_probe()
1712 	case 0x4224:  in stex_probe()
1713 	case 0x4225:  in stex_probe()
1714 	case 0x4226:  in stex_probe()
1715 	case 0x4227:  in stex_probe()
1716 	case 0x4261:  in stex_probe()
1717 	case 0x4262:  in stex_probe()
1718 	case 0x4263:  in stex_probe()
1719 	case 0x4264:  in stex_probe()
1720 	case 0x4265:  in stex_probe()
1779 	hba->msi_lock = 0;  in stex_probe()
1829 	return 0;  in stex_probe()
1858 	u16 tag = 0;  in stex_hba_stop()
1872 		memset(msg_h, 0, hba->rq_size);  in stex_hba_stop()
1874 		memset(req, 0, hba->rq_size);  in stex_hba_stop()
1879 		req->cdb[0] = MGT_CMD;  in stex_hba_stop()
1885 		req->cdb[0] = MGT_CMD;  in stex_hba_stop()
1891 		req->cdb[0] = CONTROLLER_CMD;  in stex_hba_stop()
1896 	hba->ccb[tag].sg_count = 0;  in stex_hba_stop()
1897 	hba->ccb[tag].sense_bufflen = 0;  in stex_hba_stop()
1905 			hba->ccb[tag].req_type = 0;  in stex_hba_stop()
1953 	if (hba->supports_pm == 0) {  in stex_shutdown()
1968 		hba->msi_lock = 0;  in stex_choice_sleep_mic()
1984 	return 0;  in stex_suspend()
1993 	return 0;  in stex_resume()