2  * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
4  * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
18  * 3. Neither the names of the above-listed copyright holders nor the names
55 	pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);  in pm80xx_bar4_shift()
59 		reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);  in pm80xx_bar4_shift()
62 		pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n",  in pm80xx_bar4_shift()
64 		return -1;  in pm80xx_bar4_shift()
66 	return 0;  in pm80xx_bar4_shift()
75 	for (index = 0; index < dw_count; index += 4, destination++) {  in pm80xx_pci_mem_copy()
90 	struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;  in pm80xx_get_fatal_dump()
91 	void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;  in pm80xx_get_fatal_dump()
100 	pm8001_ha->forensic_info.data_buf.direct_data = buf;  in pm80xx_get_fatal_dump()
101 	if (pm8001_ha->chip_id == chip_8001) {  in pm80xx_get_fatal_dump()
102 		pm8001_ha->forensic_info.data_buf.direct_data +=  in pm80xx_get_fatal_dump()
103 			sprintf(pm8001_ha->forensic_info.data_buf.direct_data,  in pm80xx_get_fatal_dump()
105 		return (char *)pm8001_ha->forensic_info.data_buf.direct_data -  in pm80xx_get_fatal_dump()
109 	if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {  in pm80xx_get_fatal_dump()
113 		pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;  in pm80xx_get_fatal_dump()
114 		pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;  in pm80xx_get_fatal_dump()
115 		pm8001_ha->forensic_info.data_buf.direct_offset = 0;  in pm80xx_get_fatal_dump()
116 		pm8001_ha->forensic_info.data_buf.read_len = 0;  in pm80xx_get_fatal_dump()
117 		pm8001_ha->forensic_preserved_accumulated_transfer = 0;  in pm80xx_get_fatal_dump()
121 				MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd);  in pm80xx_get_fatal_dump()
123 		pm8001_ha->forensic_info.data_buf.direct_data = direct_data;  in pm80xx_get_fatal_dump()
125 		pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n",  in pm80xx_get_fatal_dump()
126 			   pm8001_ha->forensic_info.data_buf.read_len);  in pm80xx_get_fatal_dump()
127 		pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n",  in pm80xx_get_fatal_dump()
128 			   pm8001_ha->forensic_info.data_buf.direct_len);  in pm80xx_get_fatal_dump()
129 		pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n",  in pm80xx_get_fatal_dump()
130 			   pm8001_ha->forensic_info.data_buf.direct_offset);  in pm80xx_get_fatal_dump()
132 	if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {  in pm80xx_get_fatal_dump()
134 		/* Program the MEMBASE II Shifting Register with 0x00.*/  in pm80xx_get_fatal_dump()
135 		pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,  in pm80xx_get_fatal_dump()
136 				pm8001_ha->fatal_forensic_shift_offset);  in pm80xx_get_fatal_dump()
137 		pm8001_ha->forensic_last_offset = 0;  in pm80xx_get_fatal_dump()
138 		pm8001_ha->forensic_fatal_step = 0;  in pm80xx_get_fatal_dump()
139 		pm8001_ha->fatal_bar_loc = 0;  in pm80xx_get_fatal_dump()
149 		accum_len - pm8001_ha->forensic_preserved_accumulated_transfer;  in pm80xx_get_fatal_dump()
150 	pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n",  in pm80xx_get_fatal_dump()
152 	pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n",  in pm80xx_get_fatal_dump()
154 	pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n",  in pm80xx_get_fatal_dump()
155 		   pm8001_ha->forensic_last_offset);  in pm80xx_get_fatal_dump()
156 	pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n",  in pm80xx_get_fatal_dump()
157 		   pm8001_ha->forensic_info.data_buf.read_len);  in pm80xx_get_fatal_dump()
158 	pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n",  in pm80xx_get_fatal_dump()
159 		   pm8001_ha->forensic_info.data_buf.direct_len);  in pm80xx_get_fatal_dump()
160 	pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n",  in pm80xx_get_fatal_dump()
161 		   pm8001_ha->forensic_info.data_buf.direct_offset);  in pm80xx_get_fatal_dump()
164 	if (accum_len == 0xFFFFFFFF) {  in pm80xx_get_fatal_dump()
166 			   "Possible PCI issue 0x%x not expected\n",  in pm80xx_get_fatal_dump()
171 	if (accum_len == 0) {  in pm80xx_get_fatal_dump()
172 		pm8001_ha->forensic_info.data_buf.direct_data +=  in pm80xx_get_fatal_dump()
173 			sprintf(pm8001_ha->forensic_info.data_buf.direct_data,  in pm80xx_get_fatal_dump()
174 			"%08x ", 0xFFFFFFFF);  in pm80xx_get_fatal_dump()
175 		return (char *)pm8001_ha->forensic_info.data_buf.direct_data -  in pm80xx_get_fatal_dump()
179 	temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;  in pm80xx_get_fatal_dump()
180 	if (pm8001_ha->forensic_fatal_step == 0) {  in pm80xx_get_fatal_dump()
185 		if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET  in pm80xx_get_fatal_dump()
187 			pm8001_ha->forensic_info.data_buf.direct_len =  in pm80xx_get_fatal_dump()
188 				length_to_read -  in pm80xx_get_fatal_dump()
189 				pm8001_ha->forensic_last_offset;  in pm80xx_get_fatal_dump()
191 			pm8001_ha->forensic_info.data_buf.direct_len =  in pm80xx_get_fatal_dump()
194 		if (pm8001_ha->forensic_info.data_buf.direct_data) {  in pm80xx_get_fatal_dump()
197 			pm8001_ha->fatal_bar_loc,  in pm80xx_get_fatal_dump()
198 			pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,  in pm80xx_get_fatal_dump()
199 			pm8001_ha->forensic_info.data_buf.direct_len, 1);  in pm80xx_get_fatal_dump()
201 		pm8001_ha->fatal_bar_loc +=  in pm80xx_get_fatal_dump()
202 			pm8001_ha->forensic_info.data_buf.direct_len;  in pm80xx_get_fatal_dump()
203 		pm8001_ha->forensic_info.data_buf.direct_offset +=  in pm80xx_get_fatal_dump()
204 			pm8001_ha->forensic_info.data_buf.direct_len;  in pm80xx_get_fatal_dump()
205 		pm8001_ha->forensic_last_offset	+=  in pm80xx_get_fatal_dump()
206 			pm8001_ha->forensic_info.data_buf.direct_len;  in pm80xx_get_fatal_dump()
207 		pm8001_ha->forensic_info.data_buf.read_len =  in pm80xx_get_fatal_dump()
208 			pm8001_ha->forensic_info.data_buf.direct_len;  in pm80xx_get_fatal_dump()
210 		if (pm8001_ha->forensic_last_offset  >= length_to_read) {  in pm80xx_get_fatal_dump()
211 			pm8001_ha->forensic_info.data_buf.direct_data +=  in pm80xx_get_fatal_dump()
212 			sprintf(pm8001_ha->forensic_info.data_buf.direct_data,  in pm80xx_get_fatal_dump()
214 			for (index = 0; index <  in pm80xx_get_fatal_dump()
215 				(pm8001_ha->forensic_info.data_buf.direct_len  in pm80xx_get_fatal_dump()
217 				pm8001_ha->forensic_info.data_buf.direct_data +=  in pm80xx_get_fatal_dump()
219 				pm8001_ha->forensic_info.data_buf.direct_data,  in pm80xx_get_fatal_dump()
223 			pm8001_ha->fatal_bar_loc = 0;  in pm80xx_get_fatal_dump()
224 			pm8001_ha->forensic_fatal_step = 1;  in pm80xx_get_fatal_dump()
225 			pm8001_ha->fatal_forensic_shift_offset = 0;  in pm80xx_get_fatal_dump()
226 			pm8001_ha->forensic_last_offset	= 0;  in pm80xx_get_fatal_dump()
227 			status = 0;  in pm80xx_get_fatal_dump()
229 			((char *)pm8001_ha->forensic_info.data_buf.direct_data  in pm80xx_get_fatal_dump()
230 			- (char *)buf);  in pm80xx_get_fatal_dump()
232 				   "get_fatal_spcv:return1 0x%x\n", offset);  in pm80xx_get_fatal_dump()
233 			return (char *)pm8001_ha->  in pm80xx_get_fatal_dump()
234 				forensic_info.data_buf.direct_data -  in pm80xx_get_fatal_dump()
237 		if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {  in pm80xx_get_fatal_dump()
238 			pm8001_ha->forensic_info.data_buf.direct_data +=  in pm80xx_get_fatal_dump()
239 				sprintf(pm8001_ha->  in pm80xx_get_fatal_dump()
242 			for (index = 0; index <  in pm80xx_get_fatal_dump()
243 				(pm8001_ha->forensic_info.data_buf.direct_len  in pm80xx_get_fatal_dump()
245 				pm8001_ha->forensic_info.data_buf.direct_data  in pm80xx_get_fatal_dump()
246 					+= sprintf(pm8001_ha->  in pm80xx_get_fatal_dump()
250 			status = 0;  in pm80xx_get_fatal_dump()
252 			((char *)pm8001_ha->forensic_info.data_buf.direct_data  in pm80xx_get_fatal_dump()
253 			- (char *)buf);  in pm80xx_get_fatal_dump()
255 				   "get_fatal_spcv:return2 0x%x\n", offset);  in pm80xx_get_fatal_dump()
256 			return (char *)pm8001_ha->  in pm80xx_get_fatal_dump()
257 				forensic_info.data_buf.direct_data -  in pm80xx_get_fatal_dump()
261 		/* Increment the MEMBASE II Shifting Register value by 0x100.*/  in pm80xx_get_fatal_dump()
262 		pm8001_ha->forensic_info.data_buf.direct_data +=  in pm80xx_get_fatal_dump()
263 			sprintf(pm8001_ha->forensic_info.data_buf.direct_data,  in pm80xx_get_fatal_dump()
265 		for (index = 0; index <  in pm80xx_get_fatal_dump()
266 			(pm8001_ha->forensic_info.data_buf.direct_len  in pm80xx_get_fatal_dump()
268 			pm8001_ha->forensic_info.data_buf.direct_data +=  in pm80xx_get_fatal_dump()
269 				sprintf(pm8001_ha->  in pm80xx_get_fatal_dump()
273 		pm8001_ha->fatal_forensic_shift_offset += 0x100;  in pm80xx_get_fatal_dump()
274 		pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,  in pm80xx_get_fatal_dump()
275 			pm8001_ha->fatal_forensic_shift_offset);  in pm80xx_get_fatal_dump()
276 		pm8001_ha->fatal_bar_loc = 0;  in pm80xx_get_fatal_dump()
277 		status = 0;  in pm80xx_get_fatal_dump()
279 			((char *)pm8001_ha->forensic_info.data_buf.direct_data  in pm80xx_get_fatal_dump()
280 			- (char *)buf);  in pm80xx_get_fatal_dump()
281 		pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n",  in pm80xx_get_fatal_dump()
283 		return (char *)pm8001_ha->forensic_info.data_buf.direct_data -  in pm80xx_get_fatal_dump()
286 	if (pm8001_ha->forensic_fatal_step == 1) {  in pm80xx_get_fatal_dump()
290 		pm8001_ha->forensic_preserved_accumulated_transfer =  in pm80xx_get_fatal_dump()
294 		/* continue capturing the fatal log until Dump status is 0x3 */  in pm80xx_get_fatal_dump()
301 					MPI_FATAL_EDUMP_TABLE_STATUS, 0x0);  in pm80xx_get_fatal_dump()
318 			if (reg_val != 0) {  in pm80xx_get_fatal_dump()
320 					   "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n",  in pm80xx_get_fatal_dump()
323 				pm8001_ha->forensic_info.data_buf.direct_data +=  in pm80xx_get_fatal_dump()
325 				pm8001_ha->forensic_info.data_buf.direct_data,  in pm80xx_get_fatal_dump()
326 				"%08x ", 0xFFFFFFFF);  in pm80xx_get_fatal_dump()
328 				pm8001_ha->forensic_info.data_buf.direct_data  in pm80xx_get_fatal_dump()
329 				- (char *)buf);  in pm80xx_get_fatal_dump()
344 					   "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n",  in pm80xx_get_fatal_dump()
347 				pm8001_ha->forensic_info.data_buf.direct_data +=  in pm80xx_get_fatal_dump()
349 				pm8001_ha->forensic_info.data_buf.direct_data,  in pm80xx_get_fatal_dump()
350 				"%08x ", 0xFFFFFFFF);  in pm80xx_get_fatal_dump()
351 				return((char *)pm8001_ha->forensic_info.data_buf.direct_data -  in pm80xx_get_fatal_dump()
355 			pm8001_ha->fatal_forensic_shift_offset = 0; /* location in 64k region */  in pm80xx_get_fatal_dump()
356 			pm8001_cw32(pm8001_ha, 0,  in pm80xx_get_fatal_dump()
358 					pm8001_ha->fatal_forensic_shift_offset);  in pm80xx_get_fatal_dump()
362 		MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) -  in pm80xx_get_fatal_dump()
363 		pm8001_ha->forensic_preserved_accumulated_transfer;  in pm80xx_get_fatal_dump()
364 		if (length_to_read != 0x0) {  in pm80xx_get_fatal_dump()
365 			pm8001_ha->forensic_fatal_step = 0;  in pm80xx_get_fatal_dump()
368 			pm8001_ha->forensic_info.data_buf.direct_data +=  in pm80xx_get_fatal_dump()
369 			sprintf(pm8001_ha->forensic_info.data_buf.direct_data,  in pm80xx_get_fatal_dump()
371 			pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;  in pm80xx_get_fatal_dump()
372 			pm8001_ha->forensic_info.data_buf.direct_len =  0;  in pm80xx_get_fatal_dump()
373 			pm8001_ha->forensic_info.data_buf.direct_offset = 0;  in pm80xx_get_fatal_dump()
374 			pm8001_ha->forensic_info.data_buf.read_len = 0;  in pm80xx_get_fatal_dump()
377 	offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data  in pm80xx_get_fatal_dump()
378 			- (char *)buf);  in pm80xx_get_fatal_dump()
379 	pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset);  in pm80xx_get_fatal_dump()
380 	return ((char *)pm8001_ha->forensic_info.data_buf.direct_data -  in pm80xx_get_fatal_dump()
384 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma
392 	struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;  in pm80xx_get_non_fatal_dump()
393 	void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr;  in pm80xx_get_non_fatal_dump()
394 	u32 accum_len = 0;  in pm80xx_get_non_fatal_dump()
395 	u32 total_len = 0;  in pm80xx_get_non_fatal_dump()
396 	u32 reg_val = 0;  in pm80xx_get_non_fatal_dump()
398 	u32 index = 0;  in pm80xx_get_non_fatal_dump()
400 	unsigned long start = 0;  in pm80xx_get_non_fatal_dump()
403 	temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;  in pm80xx_get_non_fatal_dump()
404 	if (++pm8001_ha->non_fatal_count == 1) {  in pm80xx_get_non_fatal_dump()
405 		if (pm8001_ha->chip_id == chip_8001) {  in pm80xx_get_non_fatal_dump()
406 			snprintf(pm8001_ha->forensic_info.data_buf.direct_data,  in pm80xx_get_non_fatal_dump()
408 			return 0;  in pm80xx_get_non_fatal_dump()
413 		 * Non-Fatal Error Dump Capture Table.This is the buffer  in pm80xx_get_non_fatal_dump()
418 		pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo);  in pm80xx_get_non_fatal_dump()
422 		pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi);  in pm80xx_get_non_fatal_dump()
428 		 * keeps sending active I/Os while capturing the non-fatal  in pm80xx_get_non_fatal_dump()
436 		 * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump  in pm80xx_get_non_fatal_dump()
440 				MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0);  in pm80xx_get_non_fatal_dump()
442 		/* initiallize previous accumulated length to 0 */  in pm80xx_get_non_fatal_dump()
443 		pm8001_ha->forensic_preserved_accumulated_transfer = 0;  in pm80xx_get_non_fatal_dump()
444 		pm8001_ha->non_fatal_read_length = 0;  in pm80xx_get_non_fatal_dump()
450 	 * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT]  in pm80xx_get_non_fatal_dump()
454 	pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0);  in pm80xx_get_non_fatal_dump()
455 	pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET,  in pm80xx_get_non_fatal_dump()
465 		reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) &  in pm80xx_get_non_fatal_dump()
467 	} while ((reg_val != 0) && time_before(jiffies, start));  in pm80xx_get_non_fatal_dump()
471 	 * the MPI Fatal and Non-Fatal Error Dump Capture Table.  in pm80xx_get_non_fatal_dump()
479 	if ((reg_val == 0x00) ||  in pm80xx_get_non_fatal_dump()
482 		pm8001_ha->non_fatal_read_length = 0;  in pm80xx_get_non_fatal_dump()
483 		buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF);  in pm80xx_get_non_fatal_dump()
484 		pm8001_ha->non_fatal_count = 0;  in pm80xx_get_non_fatal_dump()
485 		return (buf_copy - buf);  in pm80xx_get_non_fatal_dump()
490 		(pm8001_ha->non_fatal_read_length >= total_len)) {  in pm80xx_get_non_fatal_dump()
491 		pm8001_ha->non_fatal_read_length = 0;  in pm80xx_get_non_fatal_dump()
493 		pm8001_ha->non_fatal_count = 0;  in pm80xx_get_non_fatal_dump()
497 	output_length = accum_len -  in pm80xx_get_non_fatal_dump()
498 		pm8001_ha->forensic_preserved_accumulated_transfer;  in pm80xx_get_non_fatal_dump()
500 	for (index = 0; index < output_length/4; index++)  in pm80xx_get_non_fatal_dump()
504 	pm8001_ha->non_fatal_read_length += output_length;  in pm80xx_get_non_fatal_dump()
509 	pm8001_ha->forensic_preserved_accumulated_transfer = accum_len;  in pm80xx_get_non_fatal_dump()
510 	return (buf_copy - buf);  in pm80xx_get_non_fatal_dump()
514  * read_main_config_table - read the configure table and save it.
519 	void __iomem *address = pm8001_ha->main_cfg_tbl_addr;  in read_main_config_table()
521 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature	=  in read_main_config_table()
523 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =  in read_main_config_table()
525 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev	=  in read_main_config_table()
527 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io	=  in read_main_config_table()
529 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl	=  in read_main_config_table()
531 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =  in read_main_config_table()
533 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset	=  in read_main_config_table()
535 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =  in read_main_config_table()
537 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =  in read_main_config_table()
541 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =  in read_main_config_table()
543 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =  in read_main_config_table()
545 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =  in read_main_config_table()
547 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =  in read_main_config_table()
551 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =  in read_main_config_table()
555 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =  in read_main_config_table()
558 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =  in read_main_config_table()
560 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =  in read_main_config_table()
563 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =  in read_main_config_table()
566 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =  in read_main_config_table()
568 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =  in read_main_config_table()
573 		   pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,  in read_main_config_table()
574 		   pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,  in read_main_config_table()
575 		   pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev);  in read_main_config_table()
579 		   pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,  in read_main_config_table()
580 		   pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,  in read_main_config_table()
581 		   pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,  in read_main_config_table()
582 		   pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,  in read_main_config_table()
583 		   pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset);  in read_main_config_table()
587 		   pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,  in read_main_config_table()
588 		   pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version);  in read_main_config_table()
592  * read_general_status_table - read the general status table and save it.
597 	void __iomem *address = pm8001_ha->general_stat_tbl_addr;  in read_general_status_table()
598 	pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate	=  in read_general_status_table()
600 	pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0	=  in read_general_status_table()
602 	pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1	=  in read_general_status_table()
604 	pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt		=  in read_general_status_table()
606 	pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt		=  in read_general_status_table()
608 	pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val	=  in read_general_status_table()
610 	pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =  in read_general_status_table()
612 	pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =  in read_general_status_table()
614 	pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =  in read_general_status_table()
616 	pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =  in read_general_status_table()
618 	pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =  in read_general_status_table()
620 	pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =  in read_general_status_table()
622 	pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =  in read_general_status_table()
624 	pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =  in read_general_status_table()
628  * read_phy_attr_table - read the phy attribute table and save it.
633 	void __iomem *address = pm8001_ha->pspa_q_tbl_addr;  in read_phy_attr_table()
634 	pm8001_ha->phy_attr_table.phystart1_16[0] =  in read_phy_attr_table()
636 	pm8001_ha->phy_attr_table.phystart1_16[1] =  in read_phy_attr_table()
638 	pm8001_ha->phy_attr_table.phystart1_16[2] =  in read_phy_attr_table()
640 	pm8001_ha->phy_attr_table.phystart1_16[3] =  in read_phy_attr_table()
642 	pm8001_ha->phy_attr_table.phystart1_16[4] =  in read_phy_attr_table()
644 	pm8001_ha->phy_attr_table.phystart1_16[5] =  in read_phy_attr_table()
646 	pm8001_ha->phy_attr_table.phystart1_16[6] =  in read_phy_attr_table()
648 	pm8001_ha->phy_attr_table.phystart1_16[7] =  in read_phy_attr_table()
650 	pm8001_ha->phy_attr_table.phystart1_16[8] =  in read_phy_attr_table()
652 	pm8001_ha->phy_attr_table.phystart1_16[9] =  in read_phy_attr_table()
654 	pm8001_ha->phy_attr_table.phystart1_16[10] =  in read_phy_attr_table()
656 	pm8001_ha->phy_attr_table.phystart1_16[11] =  in read_phy_attr_table()
658 	pm8001_ha->phy_attr_table.phystart1_16[12] =  in read_phy_attr_table()
660 	pm8001_ha->phy_attr_table.phystart1_16[13] =  in read_phy_attr_table()
662 	pm8001_ha->phy_attr_table.phystart1_16[14] =  in read_phy_attr_table()
664 	pm8001_ha->phy_attr_table.phystart1_16[15] =  in read_phy_attr_table()
667 	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =  in read_phy_attr_table()
669 	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =  in read_phy_attr_table()
671 	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =  in read_phy_attr_table()
673 	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =  in read_phy_attr_table()
675 	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =  in read_phy_attr_table()
677 	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =  in read_phy_attr_table()
679 	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =  in read_phy_attr_table()
681 	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =  in read_phy_attr_table()
683 	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =  in read_phy_attr_table()
685 	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =  in read_phy_attr_table()
687 	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =  in read_phy_attr_table()
689 	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =  in read_phy_attr_table()
691 	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =  in read_phy_attr_table()
693 	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =  in read_phy_attr_table()
695 	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =  in read_phy_attr_table()
697 	pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =  in read_phy_attr_table()
703  * read_inbnd_queue_table - read the inbound queue table and save it.
709 	void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;  in read_inbnd_queue_table()
710 	for (i = 0; i < PM8001_MAX_INB_NUM; i++) {  in read_inbnd_queue_table()
711 		u32 offset = i * 0x20;  in read_inbnd_queue_table()
712 		pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =  in read_inbnd_queue_table()
715 		pm8001_ha->inbnd_q_tbl[i].pi_offset =  in read_inbnd_queue_table()
721  * read_outbnd_queue_table - read the outbound queue table and save it.
727 	void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;  in read_outbnd_queue_table()
728 	for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {  in read_outbnd_queue_table()
729 		u32 offset = i * 0x24;  in read_outbnd_queue_table()
730 		pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =  in read_outbnd_queue_table()
733 		pm8001_ha->outbnd_q_tbl[i].ci_offset =  in read_outbnd_queue_table()
739  * init_default_table_values - init the default table.
746 	void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;  in init_default_table_values()
747 	void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;  in init_default_table_values()
748 	u32 ib_offset = pm8001_ha->ib_offset;  in init_default_table_values()
749 	u32 ob_offset = pm8001_ha->ob_offset;  in init_default_table_values()
750 	u32 ci_offset = pm8001_ha->ci_offset;  in init_default_table_values()
751 	u32 pi_offset = pm8001_ha->pi_offset;  in init_default_table_values()
753 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr		=  in init_default_table_values()
754 		pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;  in init_default_table_values()
755 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr		=  in init_default_table_values()
756 		pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;  in init_default_table_values()
757 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size		=  in init_default_table_values()
759 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity		= 0x01;  in init_default_table_values()
760 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr	=  in init_default_table_values()
761 		pm8001_ha->memoryMap.region[IOP].phys_addr_hi;  in init_default_table_values()
762 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr	=  in init_default_table_values()
763 		pm8001_ha->memoryMap.region[IOP].phys_addr_lo;  in init_default_table_values()
764 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size		=  in init_default_table_values()
766 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity	=  in init_default_table_values()
768 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt		= 0x01;  in init_default_table_values()
771 	if (pm8001_ha->max_q_num > 32)  in init_default_table_values()
772 		pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=  in init_default_table_values()
775 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);  in init_default_table_values()
777 	for (i = 0; i < pm8001_ha->max_q_num; i++) {  in init_default_table_values()
778 		pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt	=  in init_default_table_values()
779 			PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);  in init_default_table_values()
780 		pm8001_ha->inbnd_q_tbl[i].upper_base_addr	=  in init_default_table_values()
781 			pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;  in init_default_table_values()
782 		pm8001_ha->inbnd_q_tbl[i].lower_base_addr	=  in init_default_table_values()
783 		pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;  in init_default_table_values()
784 		pm8001_ha->inbnd_q_tbl[i].base_virt		=  in init_default_table_values()
785 		  (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;  in init_default_table_values()
786 		pm8001_ha->inbnd_q_tbl[i].total_length		=  in init_default_table_values()
787 			pm8001_ha->memoryMap.region[ib_offset + i].total_len;  in init_default_table_values()
788 		pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr	=  in init_default_table_values()
789 			pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;  in init_default_table_values()
790 		pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr	=  in init_default_table_values()
791 			pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;  in init_default_table_values()
792 		pm8001_ha->inbnd_q_tbl[i].ci_virt		=  in init_default_table_values()
793 			pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;  in init_default_table_values()
794 		pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0);  in init_default_table_values()
795 		offsetib = i * 0x20;  in init_default_table_values()
796 		pm8001_ha->inbnd_q_tbl[i].pi_pci_bar		=  in init_default_table_values()
798 				(offsetib + 0x14)));  in init_default_table_values()
799 		pm8001_ha->inbnd_q_tbl[i].pi_offset		=  in init_default_table_values()
800 			pm8001_mr32(addressib, (offsetib + 0x18));  in init_default_table_values()
801 		pm8001_ha->inbnd_q_tbl[i].producer_idx		= 0;  in init_default_table_values()
802 		pm8001_ha->inbnd_q_tbl[i].consumer_index	= 0;  in init_default_table_values()
805 			   "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i,  in init_default_table_values()
806 			   pm8001_ha->inbnd_q_tbl[i].pi_pci_bar,  in init_default_table_values()
807 			   pm8001_ha->inbnd_q_tbl[i].pi_offset);  in init_default_table_values()
809 	for (i = 0; i < pm8001_ha->max_q_num; i++) {  in init_default_table_values()
810 		pm8001_ha->outbnd_q_tbl[i].element_size_cnt	=  in init_default_table_values()
811 			PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);  in init_default_table_values()
812 		pm8001_ha->outbnd_q_tbl[i].upper_base_addr	=  in init_default_table_values()
813 			pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;  in init_default_table_values()
814 		pm8001_ha->outbnd_q_tbl[i].lower_base_addr	=  in init_default_table_values()
815 			pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;  in init_default_table_values()
816 		pm8001_ha->outbnd_q_tbl[i].base_virt		=  in init_default_table_values()
817 		  (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;  in init_default_table_values()
818 		pm8001_ha->outbnd_q_tbl[i].total_length		=  in init_default_table_values()
819 			pm8001_ha->memoryMap.region[ob_offset + i].total_len;  in init_default_table_values()
820 		pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr	=  in init_default_table_values()
821 			pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;  in init_default_table_values()
822 		pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr	=  in init_default_table_values()
823 			pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;  in init_default_table_values()
825 		pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);  in init_default_table_values()
826 		pm8001_ha->outbnd_q_tbl[i].pi_virt		=  in init_default_table_values()
827 			pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;  in init_default_table_values()
828 		pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0);  in init_default_table_values()
829 		offsetob = i * 0x24;  in init_default_table_values()
830 		pm8001_ha->outbnd_q_tbl[i].ci_pci_bar		=  in init_default_table_values()
832 			offsetob + 0x14));  in init_default_table_values()
833 		pm8001_ha->outbnd_q_tbl[i].ci_offset		=  in init_default_table_values()
834 			pm8001_mr32(addressob, (offsetob + 0x18));  in init_default_table_values()
835 		pm8001_ha->outbnd_q_tbl[i].consumer_idx		= 0;  in init_default_table_values()
836 		pm8001_ha->outbnd_q_tbl[i].producer_index	= 0;  in init_default_table_values()
839 			   "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i,  in init_default_table_values()
840 			   pm8001_ha->outbnd_q_tbl[i].ci_pci_bar,  in init_default_table_values()
841 			   pm8001_ha->outbnd_q_tbl[i].ci_offset);  in init_default_table_values()
846  * update_main_config_table - update the main default table to the HBA.
851 	void __iomem *address = pm8001_ha->main_cfg_tbl_addr;  in update_main_config_table()
853 		pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);  in update_main_config_table()
855 		pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);  in update_main_config_table()
857 		pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);  in update_main_config_table()
859 		pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);  in update_main_config_table()
861 		pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);  in update_main_config_table()
863 		pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);  in update_main_config_table()
865 		pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);  in update_main_config_table()
867 		pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);  in update_main_config_table()
869 		pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);  in update_main_config_table()
871 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=  in update_main_config_table()
872 					((pm8001_ha->max_q_num - 1) << 8);  in update_main_config_table()
874 		pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);  in update_main_config_table()
876 		   "Updated Fatal error interrupt vector 0x%x\n",  in update_main_config_table()
880 		pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);  in update_main_config_table()
883 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;  in update_main_config_table()
884 	/* Set GPIOLED to 0x2 for LED indicator */  in update_main_config_table()
885 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;  in update_main_config_table()
887 		pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);  in update_main_config_table()
889 		   "Programming DW 0x21 in main cfg table with 0x%x\n",  in update_main_config_table()
893 		pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);  in update_main_config_table()
895 		pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);  in update_main_config_table()
897 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;  in update_main_config_table()
898 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=  in update_main_config_table()
900 	if (pm8001_ha->chip_id == chip_8006) {  in update_main_config_table()
901 		pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=  in update_main_config_table()
902 					0x0000ffff;  in update_main_config_table()
903 		pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=  in update_main_config_table()
907 			pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);  in update_main_config_table()
911  * update_inbnd_queue_table - update the inbound queue table to the HBA.
918 	void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;  in update_inbnd_queue_table()
919 	u16 offset = number * 0x20;  in update_inbnd_queue_table()
921 		pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);  in update_inbnd_queue_table()
923 		pm8001_ha->inbnd_q_tbl[number].upper_base_addr);  in update_inbnd_queue_table()
925 		pm8001_ha->inbnd_q_tbl[number].lower_base_addr);  in update_inbnd_queue_table()
927 		pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);  in update_inbnd_queue_table()
929 		pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);  in update_inbnd_queue_table()
932 		   "IQ %d: Element pri size 0x%x\n",  in update_inbnd_queue_table()
934 		   pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);  in update_inbnd_queue_table()
937 		   "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n",  in update_inbnd_queue_table()
938 		   pm8001_ha->inbnd_q_tbl[number].upper_base_addr,  in update_inbnd_queue_table()
939 		   pm8001_ha->inbnd_q_tbl[number].lower_base_addr);  in update_inbnd_queue_table()
942 		   "CI upper base addr 0x%x CI lower base addr 0x%x\n",  in update_inbnd_queue_table()
943 		   pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr,  in update_inbnd_queue_table()
944 		   pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);  in update_inbnd_queue_table()
948  * update_outbnd_queue_table - update the outbound queue table to the HBA.
955 	void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;  in update_outbnd_queue_table()
956 	u16 offset = number * 0x24;  in update_outbnd_queue_table()
958 		pm8001_ha->outbnd_q_tbl[number].element_size_cnt);  in update_outbnd_queue_table()
960 		pm8001_ha->outbnd_q_tbl[number].upper_base_addr);  in update_outbnd_queue_table()
962 		pm8001_ha->outbnd_q_tbl[number].lower_base_addr);  in update_outbnd_queue_table()
964 		pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);  in update_outbnd_queue_table()
966 		pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);  in update_outbnd_queue_table()
968 		pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);  in update_outbnd_queue_table()
971 		   "OQ %d: Element pri size 0x%x\n",  in update_outbnd_queue_table()
973 		   pm8001_ha->outbnd_q_tbl[number].element_size_cnt);  in update_outbnd_queue_table()
976 		   "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n",  in update_outbnd_queue_table()
977 		   pm8001_ha->outbnd_q_tbl[number].upper_base_addr,  in update_outbnd_queue_table()
978 		   pm8001_ha->outbnd_q_tbl[number].lower_base_addr);  in update_outbnd_queue_table()
981 		   "PI upper base addr 0x%x PI lower base addr 0x%x\n",  in update_outbnd_queue_table()
982 		   pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr,  in update_outbnd_queue_table()
983 		   pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);  in update_outbnd_queue_table()
987  * mpi_init_check - check firmware initialization status.
998 	pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);  in mpi_init_check()
1000 	if (IS_SPCV_12G(pm8001_ha->pdev)) {  in mpi_init_check()
1007 		value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);  in mpi_init_check()
1009 	} while ((value != 0) && (--max_wait_count));  in mpi_init_check()
1016 		return -EBUSY;  in mpi_init_check()
1018 	/* check the MPI-State for initialization up to 100ms*/  in mpi_init_check()
1023 			pm8001_mr32(pm8001_ha->general_stat_tbl_addr,  in mpi_init_check()
1026 		(gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));  in mpi_init_check()
1028 		return -EBUSY;  in mpi_init_check()
1032 	if (0x0000 != gst_len_mpistate)  in mpi_init_check()
1033 		return -EBUSY;  in mpi_init_check()
1042 	return 0;  in mpi_init_check()
1046  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
1056 	int ret = 0;  in check_fw_ready()
1062 		value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);  in check_fw_ready()
1063 	} while ((value == 0xFFFFFFFF) && (--max_wait_count));  in check_fw_ready()
1066 	if ((pm8001_ha->chip_id != chip_8008) &&  in check_fw_ready()
1067 			(pm8001_ha->chip_id != chip_8009)) {  in check_fw_ready()
1081 		value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);  in check_fw_ready()
1083 				 expected_mask) && (--max_wait_count));  in check_fw_ready()
1086 		"At least one FW component failed to load within %d millisec: Scratchpad1: 0x%x\n",  in check_fw_ready()
1088 		ret = -1;  in check_fw_ready()
1092 			(max_wait_time - max_wait_count) * FW_READY_INTERVAL);  in check_fw_ready()
1105 	value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);  in init_pci_device_addresses()
1111 	offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */  in init_pci_device_addresses()
1113 	pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n",  in init_pci_device_addresses()
1119 	pcilogic = (value & 0xFC000000) >> 26;  in init_pci_device_addresses()
1121 	pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);  in init_pci_device_addresses()
1126 	if (offset > pm8001_ha->io_mem[pcibar].memsize) {  in init_pci_device_addresses()
1129 				offset, pm8001_ha->io_mem[pcibar].memsize);  in init_pci_device_addresses()
1130 		return -EBUSY;  in init_pci_device_addresses()
1132 	pm8001_ha->main_cfg_tbl_addr = base_addr =  in init_pci_device_addresses()
1133 		pm8001_ha->io_mem[pcibar].memvirtaddr + offset;  in init_pci_device_addresses()
1139 	value = pm8001_mr32(pm8001_ha->main_cfg_tbl_addr, 0);  in init_pci_device_addresses()
1140 	if (memcmp(&value, "PMCS", 4) != 0) {  in init_pci_device_addresses()
1142 			"BAD main config signature 0x%x\n",  in init_pci_device_addresses()
1144 		return -EBUSY;  in init_pci_device_addresses()
1147 			"VALID main config signature 0x%x\n", value);  in init_pci_device_addresses()
1148 	pm8001_ha->general_stat_tbl_addr =  in init_pci_device_addresses()
1149 		base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &  in init_pci_device_addresses()
1150 					0xFFFFFF);  in init_pci_device_addresses()
1151 	pm8001_ha->inbnd_q_tbl_addr =  in init_pci_device_addresses()
1152 		base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &  in init_pci_device_addresses()
1153 					0xFFFFFF);  in init_pci_device_addresses()
1154 	pm8001_ha->outbnd_q_tbl_addr =  in init_pci_device_addresses()
1155 		base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &  in init_pci_device_addresses()
1156 					0xFFFFFF);  in init_pci_device_addresses()
1157 	pm8001_ha->ivt_tbl_addr =  in init_pci_device_addresses()
1158 		base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &  in init_pci_device_addresses()
1159 					0xFFFFFF);  in init_pci_device_addresses()
1160 	pm8001_ha->pspa_q_tbl_addr =  in init_pci_device_addresses()
1161 		base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &  in init_pci_device_addresses()
1162 					0xFFFFFF);  in init_pci_device_addresses()
1163 	pm8001_ha->fatal_tbl_addr =  in init_pci_device_addresses()
1164 		base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &  in init_pci_device_addresses()
1165 					0xFFFFFF);  in init_pci_device_addresses()
1167 	pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n",  in init_pci_device_addresses()
1168 		   pm8001_cr32(pm8001_ha, pcibar, offset + 0x18));  in init_pci_device_addresses()
1169 	pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n",  in init_pci_device_addresses()
1170 		   pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C));  in init_pci_device_addresses()
1171 	pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n",  in init_pci_device_addresses()
1172 		   pm8001_cr32(pm8001_ha, pcibar, offset + 0x20));  in init_pci_device_addresses()
1173 	pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n",  in init_pci_device_addresses()
1174 		   pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C));  in init_pci_device_addresses()
1175 	pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n",  in init_pci_device_addresses()
1176 		   pm8001_cr32(pm8001_ha, pcibar, offset + 0x90));  in init_pci_device_addresses()
1177 	pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n",  in init_pci_device_addresses()
1178 		   pm8001_ha->main_cfg_tbl_addr,  in init_pci_device_addresses()
1179 		   pm8001_ha->general_stat_tbl_addr);  in init_pci_device_addresses()
1180 	pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n",  in init_pci_device_addresses()
1181 		   pm8001_ha->inbnd_q_tbl_addr,  in init_pci_device_addresses()
1182 		   pm8001_ha->outbnd_q_tbl_addr);  in init_pci_device_addresses()
1183 	pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n",  in init_pci_device_addresses()
1184 		   pm8001_ha->pspa_q_tbl_addr,  in init_pci_device_addresses()
1185 		   pm8001_ha->ivt_tbl_addr);  in init_pci_device_addresses()
1186 	return 0;  in init_pci_device_addresses()
1190  * pm80xx_set_thermal_config - support the thermal configuration
1202 	memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));  in pm80xx_set_thermal_config()
1209 	if (IS_SPCV_12G(pm8001_ha->pdev))  in pm80xx_set_thermal_config()
1214 	payload.cfg_pg[0] =  in pm80xx_set_thermal_config()
1221 		   "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n",  in pm80xx_set_thermal_config()
1222 		   payload.cfg_pg[0], payload.cfg_pg[1]);  in pm80xx_set_thermal_config()
1224 	rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,  in pm80xx_set_thermal_config()
1225 			sizeof(payload), 0);  in pm80xx_set_thermal_config()
1233 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
1246 	memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));  in pm80xx_set_sas_protocol_timer_config()
1247 	memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));  in pm80xx_set_sas_protocol_timer_config()
1272 	pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n",  in pm80xx_set_sas_protocol_timer_config()
1274 	pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI  0x%08x\n",  in pm80xx_set_sas_protocol_timer_config()
1276 	pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO  0x%08x\n",  in pm80xx_set_sas_protocol_timer_config()
1278 	pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO  0x%08x\n",  in pm80xx_set_sas_protocol_timer_config()
1280 	pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO  0x%08x\n",  in pm80xx_set_sas_protocol_timer_config()
1282 	pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL  0x%08x\n",  in pm80xx_set_sas_protocol_timer_config()
1284 	pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO  0x%08x\n",  in pm80xx_set_sas_protocol_timer_config()
1286 	pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR  0x%08x\n",  in pm80xx_set_sas_protocol_timer_config()
1288 	pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP  0x%08x\n",  in pm80xx_set_sas_protocol_timer_config()
1294 	rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,  in pm80xx_set_sas_protocol_timer_config()
1295 			sizeof(payload), 0);  in pm80xx_set_sas_protocol_timer_config()
1303  * pm80xx_get_encrypt_info - Check for encryption
1310 	int ret = -1;  in pm80xx_get_encrypt_info()
1313 	scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);  in pm80xx_get_encrypt_info()
1318 			pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;  in pm80xx_get_encrypt_info()
1321 			pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;  in pm80xx_get_encrypt_info()
1324 			pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;  in pm80xx_get_encrypt_info()
1327 			pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;  in pm80xx_get_encrypt_info()
1328 		pm8001_ha->encrypt_info.status = 0;  in pm80xx_get_encrypt_info()
1330 			   "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",  in pm80xx_get_encrypt_info()
1332 			   pm8001_ha->encrypt_info.cipher_mode,  in pm80xx_get_encrypt_info()
1333 			   pm8001_ha->encrypt_info.sec_mode,  in pm80xx_get_encrypt_info()
1334 			   pm8001_ha->encrypt_info.status);  in pm80xx_get_encrypt_info()
1335 		ret = 0;  in pm80xx_get_encrypt_info()
1339 			   "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",  in pm80xx_get_encrypt_info()
1341 		pm8001_ha->encrypt_info.status = 0xFFFFFFFF;  in pm80xx_get_encrypt_info()
1342 		pm8001_ha->encrypt_info.cipher_mode = 0;  in pm80xx_get_encrypt_info()
1343 		pm8001_ha->encrypt_info.sec_mode = 0;  in pm80xx_get_encrypt_info()
1344 		ret = 0;  in pm80xx_get_encrypt_info()
1347 		pm8001_ha->encrypt_info.status =  in pm80xx_get_encrypt_info()
1350 			pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;  in pm80xx_get_encrypt_info()
1353 			pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;  in pm80xx_get_encrypt_info()
1356 			pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;  in pm80xx_get_encrypt_info()
1359 			pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;  in pm80xx_get_encrypt_info()
1361 			   "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",  in pm80xx_get_encrypt_info()
1363 			   pm8001_ha->encrypt_info.cipher_mode,  in pm80xx_get_encrypt_info()
1364 			   pm8001_ha->encrypt_info.sec_mode,  in pm80xx_get_encrypt_info()
1365 			   pm8001_ha->encrypt_info.status);  in pm80xx_get_encrypt_info()
1369 		pm8001_ha->encrypt_info.status =  in pm80xx_get_encrypt_info()
1372 			pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;  in pm80xx_get_encrypt_info()
1375 			pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;  in pm80xx_get_encrypt_info()
1378 			pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;  in pm80xx_get_encrypt_info()
1381 			pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;  in pm80xx_get_encrypt_info()
1384 			   "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",  in pm80xx_get_encrypt_info()
1386 			   pm8001_ha->encrypt_info.cipher_mode,  in pm80xx_get_encrypt_info()
1387 			   pm8001_ha->encrypt_info.sec_mode,  in pm80xx_get_encrypt_info()
1388 			   pm8001_ha->encrypt_info.status);  in pm80xx_get_encrypt_info()
1394  * pm80xx_encrypt_update - update flash with encryption information
1404 	memset(&payload, 0, sizeof(struct kek_mgmt_req));  in pm80xx_encrypt_update()
1418 		   "Saving Encryption info to flash. payload 0x%x\n",  in pm80xx_encrypt_update()
1421 	rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,  in pm80xx_encrypt_update()
1422 			sizeof(payload), 0);  in pm80xx_encrypt_update()
1430  * pm80xx_chip_init - the main init function that initializes whole PM8001 chip.
1436 	u8 i = 0;  in pm80xx_chip_init()
1439 	if (-1 == check_fw_ready(pm8001_ha)) {  in pm80xx_chip_init()
1441 		return -EBUSY;  in pm80xx_chip_init()
1445 	pm8001_ha->controller_fatal_error = false;  in pm80xx_chip_init()
1463 	for (i = 0; i < pm8001_ha->max_q_num; i++) {  in pm80xx_chip_init()
1468 	if (0 == mpi_init_check(pm8001_ha)) {  in pm80xx_chip_init()
1471 		return -EBUSY;  in pm80xx_chip_init()
1473 	return 0;  in pm80xx_chip_init()
1482 	if (pm8001_ha->chip->encrypt) {  in pm80xx_chip_post_init()
1487 		if (ret == -1) {  in pm80xx_chip_post_init()
1489 			if (pm8001_ha->encrypt_info.status == 0x81) {  in pm80xx_chip_post_init()
1514 	pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);  in mpi_uninit_check()
1517 	if (IS_SPCV_12G(pm8001_ha->pdev)) {  in mpi_uninit_check()
1524 		value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);  in mpi_uninit_check()
1526 	} while ((value != 0) && (--max_wait_count));  in mpi_uninit_check()
1530 		return -1;  in mpi_uninit_check()
1533 	/* check the MPI-State for termination in progress */  in mpi_uninit_check()
1539 			pm8001_mr32(pm8001_ha->general_stat_tbl_addr,  in mpi_uninit_check()
1544 	} while (--max_wait_count);  in mpi_uninit_check()
1546 		pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",  in mpi_uninit_check()
1548 		return -1;  in mpi_uninit_check()
1551 	return 0;  in mpi_uninit_check()
1555  * pm80xx_fatal_errors - returns non-zero *ONLY* when fatal errors
1563 	int ret = 0;  in pm80xx_fatal_errors()
1564 	u32 scratch_pad_rsvd0 = pm8001_cr32(pm8001_ha, 0,  in pm80xx_fatal_errors()
1566 	u32 scratch_pad_rsvd1 = pm8001_cr32(pm8001_ha, 0,  in pm80xx_fatal_errors()
1568 	u32 scratch_pad1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);  in pm80xx_fatal_errors()
1569 	u32 scratch_pad2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);  in pm80xx_fatal_errors()
1570 	u32 scratch_pad3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);  in pm80xx_fatal_errors()
1572 	if (pm8001_ha->chip_id != chip_8006 &&  in pm80xx_fatal_errors()
1573 			pm8001_ha->chip_id != chip_8074 &&  in pm80xx_fatal_errors()
1574 			pm8001_ha->chip_id != chip_8076) {  in pm80xx_fatal_errors()
1575 		return 0;  in pm80xx_fatal_errors()
1580 …"Fatal error SCRATCHPAD1 = 0x%x SCRATCHPAD2 = 0x%x SCRATCHPAD3 = 0x%x SCRATCHPAD_RSVD0 = 0x%x SCRA…  in pm80xx_fatal_errors()
1590  * pm80xx_chip_soft_rst - soft reset the PM8001 chip, so that all
1603 	if (!pm8001_ha->controller_fatal_error) {  in pm80xx_chip_soft_rst()
1605 		if (mpi_uninit_check(pm8001_ha) != 0) {  in pm80xx_chip_soft_rst()
1606 			u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);  in pm80xx_chip_soft_rst()
1607 			u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);  in pm80xx_chip_soft_rst()
1608 			u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);  in pm80xx_chip_soft_rst()
1609 			u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);  in pm80xx_chip_soft_rst()
1617 				return -1;  in pm80xx_chip_soft_rst()
1620 	/* checked for reset register normal state; 0x0 */  in pm80xx_chip_soft_rst()
1621 	regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);  in pm80xx_chip_soft_rst()
1622 	pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n",  in pm80xx_chip_soft_rst()
1625 	pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);  in pm80xx_chip_soft_rst()
1628 	regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);  in pm80xx_chip_soft_rst()
1629 	pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n",  in pm80xx_chip_soft_rst()
1635 			   " soft reset successful [regval: 0x%x]\n",  in pm80xx_chip_soft_rst()
1639 			   " soft reset failed [regval: 0x%x]\n",  in pm80xx_chip_soft_rst()
1644 			pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &  in pm80xx_chip_soft_rst()
1649 				   "Bootloader state - HDA mode SEEPROM\n");  in pm80xx_chip_soft_rst()
1653 				   "Bootloader state - HDA mode Bootstrap Pin\n");  in pm80xx_chip_soft_rst()
1657 				   "Bootloader state - HDA mode soft reset\n");  in pm80xx_chip_soft_rst()
1661 				   "Bootloader state-HDA mode critical error\n");  in pm80xx_chip_soft_rst()
1663 		return -EBUSY;  in pm80xx_chip_soft_rst()
1667 	if (-1 == check_fw_ready(pm8001_ha)) {  in pm80xx_chip_soft_rst()
1670 		if (pm8001_ha->pdev->subsystem_vendor !=  in pm80xx_chip_soft_rst()
1672 			pm8001_ha->pdev->subsystem_vendor !=  in pm80xx_chip_soft_rst()
1674 			pm8001_ha->pdev->subsystem_vendor != 0) {  in pm80xx_chip_soft_rst()
1675 			ibutton0 = pm8001_cr32(pm8001_ha, 0,  in pm80xx_chip_soft_rst()
1677 			ibutton1 = pm8001_cr32(pm8001_ha, 0,  in pm80xx_chip_soft_rst()
1682 				return -EBUSY;  in pm80xx_chip_soft_rst()
1684 			if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {  in pm80xx_chip_soft_rst()
1687 				return -EBUSY;  in pm80xx_chip_soft_rst()
1692 	return 0;  in pm80xx_chip_soft_rst()
1702 	pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);  in pm80xx_hw_chip_rst()
1713 	} while ((--i) != 0);  in pm80xx_hw_chip_rst()
1719  * pm80xx_chip_interrupt_enable - enable PM8001 chip interrupt
1726 	if (!pm8001_ha->use_msix) {  in pm80xx_chip_interrupt_enable()
1727 		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);  in pm80xx_chip_interrupt_enable()
1728 		pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);  in pm80xx_chip_interrupt_enable()
1733 		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec);  in pm80xx_chip_interrupt_enable()
1735 		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U, 1U << (vec - 32));  in pm80xx_chip_interrupt_enable()
1739  * pm80xx_chip_interrupt_disable - disable PM8001 chip interrupt
1746 	if (!pm8001_ha->use_msix) {  in pm80xx_chip_interrupt_disable()
1747 		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);  in pm80xx_chip_interrupt_disable()
1751 	if (vec == 0xFF) {  in pm80xx_chip_interrupt_disable()
1752 		/* disable all vectors 0-31, 32-63 */  in pm80xx_chip_interrupt_disable()
1753 		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF);  in pm80xx_chip_interrupt_disable()
1754 		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF);  in pm80xx_chip_interrupt_disable()
1756 		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec);  in pm80xx_chip_interrupt_disable()
1758 		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 1U << (vec - 32));  in pm80xx_chip_interrupt_disable()
1763  * mpi_ssp_completion - process the event that FW response to the SSP request.
1787 	status = le32_to_cpu(psspPayload->status);  in mpi_ssp_completion()
1788 	tag = le32_to_cpu(psspPayload->tag);  in mpi_ssp_completion()
1789 	ccb = &pm8001_ha->ccb_info[tag];  in mpi_ssp_completion()
1790 	if ((status == IO_ABORTED) && ccb->open_retry) {  in mpi_ssp_completion()
1792 		ccb->open_retry = 0;  in mpi_ssp_completion()
1795 	pm8001_dev = ccb->device;  in mpi_ssp_completion()
1796 	param = le32_to_cpu(psspPayload->param);  in mpi_ssp_completion()
1797 	t = ccb->task;  in mpi_ssp_completion()
1800 		pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);  in mpi_ssp_completion()
1801 	if (unlikely(!t || !t->lldd_task || !t->dev))  in mpi_ssp_completion()
1803 	ts = &t->task_status;  in mpi_ssp_completion()
1806 		   "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t);  in mpi_ssp_completion()
1812 			   SAS_ADDR(t->dev->sas_addr));  in mpi_ssp_completion()
1816 		pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n",  in mpi_ssp_completion()
1818 		if (param == 0) {  in mpi_ssp_completion()
1819 			ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1820 			ts->stat = SAS_SAM_STAT_GOOD;  in mpi_ssp_completion()
1822 			ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1823 			ts->stat = SAS_PROTO_RESPONSE;  in mpi_ssp_completion()
1824 			ts->residual = param;  in mpi_ssp_completion()
1825 			iu = &psspPayload->ssp_resp_iu;  in mpi_ssp_completion()
1826 			sas_ssp_task_response(pm8001_ha->dev, t, iu);  in mpi_ssp_completion()
1829 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1833 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1834 		ts->stat = SAS_ABORTED_TASK;  in mpi_ssp_completion()
1836 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1840 		pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n",  in mpi_ssp_completion()
1842 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1843 		ts->stat = SAS_DATA_UNDERRUN;  in mpi_ssp_completion()
1844 		ts->residual = param;  in mpi_ssp_completion()
1846 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1850 		ts->resp = SAS_TASK_UNDELIVERED;  in mpi_ssp_completion()
1851 		ts->stat = SAS_PHY_DOWN;  in mpi_ssp_completion()
1853 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1857 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1858 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
1860 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;  in mpi_ssp_completion()
1862 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1866 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1867 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
1868 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;  in mpi_ssp_completion()
1870 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1875 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1876 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
1877 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;  in mpi_ssp_completion()
1879 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1884 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1885 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
1886 		ts->open_rej_reason = SAS_OREJ_EPROTO;  in mpi_ssp_completion()
1888 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1893 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1894 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
1895 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;  in mpi_ssp_completion()
1897 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1901 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1902 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
1903 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;  in mpi_ssp_completion()
1905 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1914 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1915 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
1916 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;  in mpi_ssp_completion()
1917 		if (!t->uldd_task)  in mpi_ssp_completion()
1925 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1926 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
1927 		ts->open_rej_reason = SAS_OREJ_BAD_DEST;  in mpi_ssp_completion()
1929 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1934 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1935 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
1936 		ts->open_rej_reason = SAS_OREJ_CONN_RATE;  in mpi_ssp_completion()
1938 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1943 		ts->resp = SAS_TASK_UNDELIVERED;  in mpi_ssp_completion()
1944 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
1945 		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;  in mpi_ssp_completion()
1947 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1951 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1952 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
1953 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;  in mpi_ssp_completion()
1955 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1959 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1960 		ts->stat = SAS_NAK_R_ERR;  in mpi_ssp_completion()
1962 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1966 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1967 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
1969 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1973 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1974 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
1975 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;  in mpi_ssp_completion()
1977 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1981 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1982 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
1984 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1988 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1989 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
1991 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
1995 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
1996 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
1997 		if (!t->uldd_task)  in mpi_ssp_completion()
2004 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
2005 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
2007 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
2011 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
2012 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
2014 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
2018 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
2019 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
2021 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
2026 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
2027 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
2028 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;  in mpi_ssp_completion()
2030 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
2033 		pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);  in mpi_ssp_completion()
2035 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_completion()
2036 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_completion()
2038 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_completion()
2041 	pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n",  in mpi_ssp_completion()
2042 		   psspPayload->ssp_resp_iu.status);  in mpi_ssp_completion()
2043 	spin_lock_irqsave(&t->task_state_lock, flags);  in mpi_ssp_completion()
2044 	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;  in mpi_ssp_completion()
2045 	t->task_state_flags |= SAS_TASK_STATE_DONE;  in mpi_ssp_completion()
2046 	if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {  in mpi_ssp_completion()
2047 		spin_unlock_irqrestore(&t->task_state_lock, flags);  in mpi_ssp_completion()
2049 			   "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",  in mpi_ssp_completion()
2050 			   t, status, ts->resp, ts->stat);  in mpi_ssp_completion()
2052 		if (t->slow_task)  in mpi_ssp_completion()
2053 			complete(&t->slow_task->completion);  in mpi_ssp_completion()
2055 		spin_unlock_irqrestore(&t->task_state_lock, flags);  in mpi_ssp_completion()
2070 	u32 event = le32_to_cpu(psspPayload->event);  in mpi_ssp_event()
2071 	u32 tag = le32_to_cpu(psspPayload->tag);  in mpi_ssp_event()
2072 	u32 port_id = le32_to_cpu(psspPayload->port_id);  in mpi_ssp_event()
2074 	ccb = &pm8001_ha->ccb_info[tag];  in mpi_ssp_event()
2075 	t = ccb->task;  in mpi_ssp_event()
2076 	pm8001_dev = ccb->device;  in mpi_ssp_event()
2078 		pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);  in mpi_ssp_event()
2079 	if (unlikely(!t || !t->lldd_task || !t->dev))  in mpi_ssp_event()
2081 	ts = &t->task_status;  in mpi_ssp_event()
2082 	pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",  in mpi_ssp_event()
2087 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2088 		ts->stat = SAS_DATA_OVERRUN;  in mpi_ssp_event()
2089 		ts->residual = 0;  in mpi_ssp_event()
2091 			atomic_dec(&pm8001_dev->running_req);  in mpi_ssp_event()
2099 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2100 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_event()
2101 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;  in mpi_ssp_event()
2106 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2107 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_event()
2108 		ts->open_rej_reason = SAS_OREJ_EPROTO;  in mpi_ssp_event()
2113 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2114 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_event()
2115 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;  in mpi_ssp_event()
2119 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2120 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_event()
2121 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;  in mpi_ssp_event()
2130 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2131 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_event()
2132 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;  in mpi_ssp_event()
2133 		if (!t->uldd_task)  in mpi_ssp_event()
2141 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2142 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_event()
2143 		ts->open_rej_reason = SAS_OREJ_BAD_DEST;  in mpi_ssp_event()
2148 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2149 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_event()
2150 		ts->open_rej_reason = SAS_OREJ_CONN_RATE;  in mpi_ssp_event()
2155 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2156 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_event()
2157 		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;  in mpi_ssp_event()
2161 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2162 		ts->stat = SAS_OPEN_REJECT;  in mpi_ssp_event()
2163 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;  in mpi_ssp_event()
2167 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2168 		ts->stat = SAS_NAK_R_ERR;  in mpi_ssp_event()
2176 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2177 		ts->stat = SAS_DATA_OVERRUN;  in mpi_ssp_event()
2181 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2182 		ts->stat = SAS_DATA_OVERRUN;  in mpi_ssp_event()
2187 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2188 		ts->stat = SAS_DATA_OVERRUN;  in mpi_ssp_event()
2193 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2194 		ts->stat = SAS_DATA_OVERRUN;  in mpi_ssp_event()
2198 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2199 		ts->stat = SAS_DATA_OVERRUN;  in mpi_ssp_event()
2204 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2205 		ts->stat = SAS_DATA_OVERRUN;  in mpi_ssp_event()
2211 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2212 		ts->stat = SAS_DATA_OVERRUN;  in mpi_ssp_event()
2218 		pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);  in mpi_ssp_event()
2220 		ts->resp = SAS_TASK_COMPLETE;  in mpi_ssp_event()
2221 		ts->stat = SAS_DATA_OVERRUN;  in mpi_ssp_event()
2224 	spin_lock_irqsave(&t->task_state_lock, flags);  in mpi_ssp_event()
2225 	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;  in mpi_ssp_event()
2226 	t->task_state_flags |= SAS_TASK_STATE_DONE;  in mpi_ssp_event()
2227 	if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {  in mpi_ssp_event()
2228 		spin_unlock_irqrestore(&t->task_state_lock, flags);  in mpi_ssp_event()
2230 			   "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",  in mpi_ssp_event()
2231 			   t, event, ts->resp, ts->stat);  in mpi_ssp_event()
2234 		spin_unlock_irqrestore(&t->task_state_lock, flags);  in mpi_ssp_event()
2249 	int i, j, ata_tag = -1;  in mpi_sata_completion()
2262 	status = le32_to_cpu(psataPayload->status);  in mpi_sata_completion()
2263 	param = le32_to_cpu(psataPayload->param);  in mpi_sata_completion()
2264 	tag = le32_to_cpu(psataPayload->tag);  in mpi_sata_completion()
2266 	ccb = &pm8001_ha->ccb_info[tag];  in mpi_sata_completion()
2267 	t = ccb->task;  in mpi_sata_completion()
2268 	pm8001_dev = ccb->device;  in mpi_sata_completion()
2271 		if (t->dev && (t->dev->lldd_dev)) {  in mpi_sata_completion()
2272 			pm8001_dev = t->dev->lldd_dev;  in mpi_sata_completion()
2273 			qc = t->uldd_task;  in mpi_sata_completion()
2274 			ata_tag = qc ? qc->tag : -1;  in mpi_sata_completion()
2278 			   ccb->ccb_tag);  in mpi_sata_completion()
2283 	if (pm8001_dev && unlikely(!t->lldd_task || !t->dev))  in mpi_sata_completion()
2286 	ts = &t->task_status;  in mpi_sata_completion()
2296 		if (!((t->dev->parent) &&  in mpi_sata_completion()
2297 			(dev_is_expander(t->dev->parent->dev_type)))) {  in mpi_sata_completion()
2298 			for (i = 0, j = 4; i <= 3 && j <= 7; i++, j++)  in mpi_sata_completion()
2299 				sata_addr_low[i] = pm8001_ha->sas_addr[j];  in mpi_sata_completion()
2300 			for (i = 0, j = 0; i <= 3 && j <= 3; i++, j++)  in mpi_sata_completion()
2301 				sata_addr_hi[i] = pm8001_ha->sas_addr[j];  in mpi_sata_completion()
2306 			temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)  in mpi_sata_completion()
2308 						0xff0000) |  in mpi_sata_completion()
2310 						& 0xff00) |  in mpi_sata_completion()
2312 						0xff000000));  in mpi_sata_completion()
2314 						& 0xff) |  in mpi_sata_completion()
2316 						& 0xff0000) |  in mpi_sata_completion()
2318 						& 0xff00) |  in mpi_sata_completion()
2320 						& 0xff000000)) +  in mpi_sata_completion()
2321 						pm8001_dev->attached_phy +  in mpi_sata_completion()
2322 						0x10);  in mpi_sata_completion()
2331 				   SAS_ADDR(t->dev->sas_addr));  in mpi_sata_completion()
2337 		if (param == 0) {  in mpi_sata_completion()
2338 			ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2339 			ts->stat = SAS_SAM_STAT_GOOD;  in mpi_sata_completion()
2342 			ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2343 			ts->stat = SAS_PROTO_RESPONSE;  in mpi_sata_completion()
2344 			ts->residual = param;  in mpi_sata_completion()
2348 			sata_resp = &psataPayload->sata_resp[0];  in mpi_sata_completion()
2349 			resp = (struct ata_task_resp *)ts->buf;  in mpi_sata_completion()
2350 			if (t->ata_task.dma_xfer == 0 &&  in mpi_sata_completion()
2351 			    t->data_dir == DMA_FROM_DEVICE) {  in mpi_sata_completion()
2355 			} else if (t->ata_task.use_ncq &&  in mpi_sata_completion()
2356 				   t->data_dir != DMA_NONE) {  in mpi_sata_completion()
2366 				resp->frame_len = len;  in mpi_sata_completion()
2367 				memcpy(&resp->ending_fis[0], sata_resp, len);  in mpi_sata_completion()
2368 				ts->buf_valid_size = sizeof(*resp);  in mpi_sata_completion()
2374 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2378 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2379 		ts->stat = SAS_ABORTED_TASK;  in mpi_sata_completion()
2381 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2387 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2388 		ts->stat = SAS_DATA_UNDERRUN;  in mpi_sata_completion()
2389 		ts->residual = param;  in mpi_sata_completion()
2391 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2395 		ts->resp = SAS_TASK_UNDELIVERED;  in mpi_sata_completion()
2396 		ts->stat = SAS_PHY_DOWN;  in mpi_sata_completion()
2398 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2402 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2403 		ts->stat = SAS_INTERRUPTED;  in mpi_sata_completion()
2405 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2409 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2410 		ts->stat = SAS_OPEN_REJECT;  in mpi_sata_completion()
2411 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;  in mpi_sata_completion()
2413 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2418 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2419 		ts->stat = SAS_OPEN_REJECT;  in mpi_sata_completion()
2420 		ts->open_rej_reason = SAS_OREJ_EPROTO;  in mpi_sata_completion()
2422 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2427 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2428 		ts->stat = SAS_OPEN_REJECT;  in mpi_sata_completion()
2429 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;  in mpi_sata_completion()
2431 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2435 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2436 		ts->stat = SAS_OPEN_REJECT;  in mpi_sata_completion()
2437 		ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;  in mpi_sata_completion()
2439 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2448 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2449 		ts->stat = SAS_DEV_NO_RESPONSE;  in mpi_sata_completion()
2450 		if (!t->uldd_task) {  in mpi_sata_completion()
2454 			ts->resp = SAS_TASK_UNDELIVERED;  in mpi_sata_completion()
2455 			ts->stat = SAS_QUEUE_FULL;  in mpi_sata_completion()
2456 			spin_unlock_irqrestore(&circularQ->oq_lock,  in mpi_sata_completion()
2457 					circularQ->lock_flags);  in mpi_sata_completion()
2459 			spin_lock_irqsave(&circularQ->oq_lock,  in mpi_sata_completion()
2460 					circularQ->lock_flags);  in mpi_sata_completion()
2467 		ts->resp = SAS_TASK_UNDELIVERED;  in mpi_sata_completion()
2468 		ts->stat = SAS_OPEN_REJECT;  in mpi_sata_completion()
2469 		ts->open_rej_reason = SAS_OREJ_BAD_DEST;  in mpi_sata_completion()
2470 		if (!t->uldd_task) {  in mpi_sata_completion()
2474 			ts->resp = SAS_TASK_UNDELIVERED;  in mpi_sata_completion()
2475 			ts->stat = SAS_QUEUE_FULL;  in mpi_sata_completion()
2476 			spin_unlock_irqrestore(&circularQ->oq_lock,  in mpi_sata_completion()
2477 					circularQ->lock_flags);  in mpi_sata_completion()
2479 			spin_lock_irqsave(&circularQ->oq_lock,  in mpi_sata_completion()
2480 					circularQ->lock_flags);  in mpi_sata_completion()
2487 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2488 		ts->stat = SAS_OPEN_REJECT;  in mpi_sata_completion()
2489 		ts->open_rej_reason = SAS_OREJ_CONN_RATE;  in mpi_sata_completion()
2491 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2496 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2497 		ts->stat = SAS_DEV_NO_RESPONSE;  in mpi_sata_completion()
2498 		if (!t->uldd_task) {  in mpi_sata_completion()
2502 			ts->resp = SAS_TASK_UNDELIVERED;  in mpi_sata_completion()
2503 			ts->stat = SAS_QUEUE_FULL;  in mpi_sata_completion()
2504 			spin_unlock_irqrestore(&circularQ->oq_lock,  in mpi_sata_completion()
2505 					circularQ->lock_flags);  in mpi_sata_completion()
2507 			spin_lock_irqsave(&circularQ->oq_lock,  in mpi_sata_completion()
2508 					circularQ->lock_flags);  in mpi_sata_completion()
2515 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2516 		ts->stat = SAS_OPEN_REJECT;  in mpi_sata_completion()
2517 		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;  in mpi_sata_completion()
2519 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2523 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2524 		ts->stat = SAS_NAK_R_ERR;  in mpi_sata_completion()
2526 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2530 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2531 		ts->stat = SAS_NAK_R_ERR;  in mpi_sata_completion()
2533 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2537 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2538 		ts->stat = SAS_ABORTED_TASK;  in mpi_sata_completion()
2540 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2544 		ts->resp = SAS_TASK_UNDELIVERED;  in mpi_sata_completion()
2545 		ts->stat = SAS_DEV_NO_RESPONSE;  in mpi_sata_completion()
2547 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2551 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2552 		ts->stat = SAS_DATA_UNDERRUN;  in mpi_sata_completion()
2554 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2558 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2559 		ts->stat = SAS_OPEN_TO;  in mpi_sata_completion()
2561 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2565 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2566 		ts->stat = SAS_DEV_NO_RESPONSE;  in mpi_sata_completion()
2568 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2572 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2573 		ts->stat = SAS_DEV_NO_RESPONSE;  in mpi_sata_completion()
2574 		if (!t->uldd_task) {  in mpi_sata_completion()
2577 			ts->resp = SAS_TASK_UNDELIVERED;  in mpi_sata_completion()
2578 			ts->stat = SAS_QUEUE_FULL;  in mpi_sata_completion()
2579 			spin_unlock_irqrestore(&circularQ->oq_lock,  in mpi_sata_completion()
2580 					circularQ->lock_flags);  in mpi_sata_completion()
2582 			spin_lock_irqsave(&circularQ->oq_lock,  in mpi_sata_completion()
2583 					circularQ->lock_flags);  in mpi_sata_completion()
2589 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2590 		ts->stat = SAS_DEV_NO_RESPONSE;  in mpi_sata_completion()
2592 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2596 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2597 		ts->stat = SAS_DEV_NO_RESPONSE;  in mpi_sata_completion()
2598 		if (!t->uldd_task) {  in mpi_sata_completion()
2601 			ts->resp = SAS_TASK_UNDELIVERED;  in mpi_sata_completion()
2602 			ts->stat = SAS_QUEUE_FULL;  in mpi_sata_completion()
2603 			spin_unlock_irqrestore(&circularQ->oq_lock,  in mpi_sata_completion()
2604 					circularQ->lock_flags);  in mpi_sata_completion()
2606 			spin_lock_irqsave(&circularQ->oq_lock,  in mpi_sata_completion()
2607 					circularQ->lock_flags);  in mpi_sata_completion()
2614 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2615 		ts->stat = SAS_OPEN_REJECT;  in mpi_sata_completion()
2616 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;  in mpi_sata_completion()
2618 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2622 				"Unknown status device_id %u status 0x%x tag %d\n",  in mpi_sata_completion()
2623 			pm8001_dev->device_id, status, tag);  in mpi_sata_completion()
2625 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_completion()
2626 		ts->stat = SAS_DEV_NO_RESPONSE;  in mpi_sata_completion()
2628 			atomic_dec(&pm8001_dev->running_req);  in mpi_sata_completion()
2631 	spin_lock_irqsave(&t->task_state_lock, flags);  in mpi_sata_completion()
2632 	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;  in mpi_sata_completion()
2633 	t->task_state_flags |= SAS_TASK_STATE_DONE;  in mpi_sata_completion()
2634 	if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {  in mpi_sata_completion()
2635 		spin_unlock_irqrestore(&t->task_state_lock, flags);  in mpi_sata_completion()
2637 			   "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",  in mpi_sata_completion()
2638 			   t, status, ts->resp, ts->stat);  in mpi_sata_completion()
2640 		if (t->slow_task)  in mpi_sata_completion()
2641 			complete(&t->slow_task->completion);  in mpi_sata_completion()
2643 		spin_unlock_irqrestore(&t->task_state_lock, flags);  in mpi_sata_completion()
2644 		spin_unlock_irqrestore(&circularQ->oq_lock,  in mpi_sata_completion()
2645 				circularQ->lock_flags);  in mpi_sata_completion()
2647 		spin_lock_irqsave(&circularQ->oq_lock,  in mpi_sata_completion()
2648 				circularQ->lock_flags);  in mpi_sata_completion()
2662 	u32 event = le32_to_cpu(psataPayload->event);  in mpi_sata_event()
2663 	u32 tag = le32_to_cpu(psataPayload->tag);  in mpi_sata_event()
2664 	u32 port_id = le32_to_cpu(psataPayload->port_id);  in mpi_sata_event()
2665 	u32 dev_id = le32_to_cpu(psataPayload->device_id);  in mpi_sata_event()
2668 		pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);  in mpi_sata_event()
2678 		/* send read log extension by aborting the link - libata does what we want */  in mpi_sata_event()
2688 	ccb = &pm8001_ha->ccb_info[tag];  in mpi_sata_event()
2689 	t = ccb->task;  in mpi_sata_event()
2690 	pm8001_dev = ccb->device;  in mpi_sata_event()
2693 			   ccb->ccb_tag);  in mpi_sata_event()
2698 	if (unlikely(!t->lldd_task || !t->dev))  in mpi_sata_event()
2701 	ts = &t->task_status;  in mpi_sata_event()
2702 	pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",  in mpi_sata_event()
2707 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2708 		ts->stat = SAS_DATA_OVERRUN;  in mpi_sata_event()
2709 		ts->residual = 0;  in mpi_sata_event()
2713 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2714 		ts->stat = SAS_INTERRUPTED;  in mpi_sata_event()
2718 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2719 		ts->stat = SAS_OPEN_REJECT;  in mpi_sata_event()
2720 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;  in mpi_sata_event()
2725 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2726 		ts->stat = SAS_OPEN_REJECT;  in mpi_sata_event()
2727 		ts->open_rej_reason = SAS_OREJ_EPROTO;  in mpi_sata_event()
2732 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2733 		ts->stat = SAS_OPEN_REJECT;  in mpi_sata_event()
2734 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;  in mpi_sata_event()
2738 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2739 		ts->stat = SAS_OPEN_REJECT;  in mpi_sata_event()
2740 		ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;  in mpi_sata_event()
2750 		ts->resp = SAS_TASK_UNDELIVERED;  in mpi_sata_event()
2751 		ts->stat = SAS_DEV_NO_RESPONSE;  in mpi_sata_event()
2752 		if (!t->uldd_task) {  in mpi_sata_event()
2756 			ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2757 			ts->stat = SAS_QUEUE_FULL;  in mpi_sata_event()
2764 		ts->resp = SAS_TASK_UNDELIVERED;  in mpi_sata_event()
2765 		ts->stat = SAS_OPEN_REJECT;  in mpi_sata_event()
2766 		ts->open_rej_reason = SAS_OREJ_BAD_DEST;  in mpi_sata_event()
2771 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2772 		ts->stat = SAS_OPEN_REJECT;  in mpi_sata_event()
2773 		ts->open_rej_reason = SAS_OREJ_CONN_RATE;  in mpi_sata_event()
2778 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2779 		ts->stat = SAS_OPEN_REJECT;  in mpi_sata_event()
2780 		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;  in mpi_sata_event()
2784 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2785 		ts->stat = SAS_NAK_R_ERR;  in mpi_sata_event()
2789 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2790 		ts->stat = SAS_NAK_R_ERR;  in mpi_sata_event()
2794 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2795 		ts->stat = SAS_DATA_UNDERRUN;  in mpi_sata_event()
2799 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2800 		ts->stat = SAS_OPEN_TO;  in mpi_sata_event()
2804 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2805 		ts->stat = SAS_OPEN_TO;  in mpi_sata_event()
2809 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2810 		ts->stat = SAS_OPEN_TO;  in mpi_sata_event()
2815 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2816 		ts->stat = SAS_OPEN_TO;  in mpi_sata_event()
2820 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2821 		ts->stat = SAS_OPEN_TO;  in mpi_sata_event()
2826 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2827 		ts->stat = SAS_OPEN_TO;  in mpi_sata_event()
2834 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2835 		ts->stat = SAS_OPEN_TO;  in mpi_sata_event()
2841 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2842 		ts->stat = SAS_OPEN_TO;  in mpi_sata_event()
2847 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2848 		ts->stat = SAS_OPEN_TO;  in mpi_sata_event()
2851 		pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event);  in mpi_sata_event()
2853 		ts->resp = SAS_TASK_COMPLETE;  in mpi_sata_event()
2854 		ts->stat = SAS_OPEN_TO;  in mpi_sata_event()
2874 	status = le32_to_cpu(psmpPayload->status);  in mpi_smp_completion()
2875 	tag = le32_to_cpu(psmpPayload->tag);  in mpi_smp_completion()
2877 	ccb = &pm8001_ha->ccb_info[tag];  in mpi_smp_completion()
2878 	param = le32_to_cpu(psmpPayload->param);  in mpi_smp_completion()
2879 	t = ccb->task;  in mpi_smp_completion()
2880 	ts = &t->task_status;  in mpi_smp_completion()
2881 	pm8001_dev = ccb->device;  in mpi_smp_completion()
2883 		pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);  in mpi_smp_completion()
2884 	if (unlikely(!t || !t->lldd_task || !t->dev))  in mpi_smp_completion()
2887 	pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status);  in mpi_smp_completion()
2893 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
2894 		ts->stat = SAS_SAM_STAT_GOOD;  in mpi_smp_completion()
2896 			atomic_dec(&pm8001_dev->running_req);  in mpi_smp_completion()
2897 		if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {  in mpi_smp_completion()
2898 			struct scatterlist *sg_resp = &t->smp_task.smp_resp;  in mpi_smp_completion()
2906 			payload = to + sg_resp->offset;  in mpi_smp_completion()
2907 			for (i = 0; i < param; i++) {  in mpi_smp_completion()
2908 				*(payload + i) = psmpPayload->_r_a[i];  in mpi_smp_completion()
2910 					   "SMP Byte%d DMA data 0x%x psmp 0x%x\n",  in mpi_smp_completion()
2912 					   psmpPayload->_r_a[i]);  in mpi_smp_completion()
2919 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
2920 		ts->stat = SAS_ABORTED_TASK;  in mpi_smp_completion()
2922 			atomic_dec(&pm8001_dev->running_req);  in mpi_smp_completion()
2926 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
2927 		ts->stat = SAS_DATA_OVERRUN;  in mpi_smp_completion()
2928 		ts->residual = 0;  in mpi_smp_completion()
2930 			atomic_dec(&pm8001_dev->running_req);  in mpi_smp_completion()
2934 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
2935 		ts->stat = SAS_PHY_DOWN;  in mpi_smp_completion()
2939 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
2940 		ts->stat = SAS_SAM_STAT_BUSY;  in mpi_smp_completion()
2944 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
2945 		ts->stat = SAS_SAM_STAT_BUSY;  in mpi_smp_completion()
2949 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
2950 		ts->stat = SAS_SAM_STAT_BUSY;  in mpi_smp_completion()
2955 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
2956 		ts->stat = SAS_OPEN_REJECT;  in mpi_smp_completion()
2957 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;  in mpi_smp_completion()
2962 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
2963 		ts->stat = SAS_OPEN_REJECT;  in mpi_smp_completion()
2964 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;  in mpi_smp_completion()
2968 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
2969 		ts->stat = SAS_OPEN_REJECT;  in mpi_smp_completion()
2970 		ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;  in mpi_smp_completion()
2979 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
2980 		ts->stat = SAS_OPEN_REJECT;  in mpi_smp_completion()
2981 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;  in mpi_smp_completion()
2989 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
2990 		ts->stat = SAS_OPEN_REJECT;  in mpi_smp_completion()
2991 		ts->open_rej_reason = SAS_OREJ_BAD_DEST;  in mpi_smp_completion()
2996 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
2997 		ts->stat = SAS_OPEN_REJECT;  in mpi_smp_completion()
2998 		ts->open_rej_reason = SAS_OREJ_CONN_RATE;  in mpi_smp_completion()
3003 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
3004 		ts->stat = SAS_OPEN_REJECT;  in mpi_smp_completion()
3005 		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;  in mpi_smp_completion()
3009 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
3010 		ts->stat = SAS_DEV_NO_RESPONSE;  in mpi_smp_completion()
3014 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
3015 		ts->stat = SAS_OPEN_REJECT;  in mpi_smp_completion()
3016 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;  in mpi_smp_completion()
3020 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
3021 		ts->stat = SAS_QUEUE_FULL;  in mpi_smp_completion()
3025 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
3026 		ts->stat = SAS_OPEN_REJECT;  in mpi_smp_completion()
3027 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;  in mpi_smp_completion()
3031 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
3032 		ts->stat = SAS_DEV_NO_RESPONSE;  in mpi_smp_completion()
3036 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
3037 		ts->stat = SAS_OPEN_REJECT;  in mpi_smp_completion()
3038 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;  in mpi_smp_completion()
3043 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
3044 		ts->stat = SAS_OPEN_REJECT;  in mpi_smp_completion()
3045 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;  in mpi_smp_completion()
3048 		pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);  in mpi_smp_completion()
3049 		ts->resp = SAS_TASK_COMPLETE;  in mpi_smp_completion()
3050 		ts->stat = SAS_DEV_NO_RESPONSE;  in mpi_smp_completion()
3054 	spin_lock_irqsave(&t->task_state_lock, flags);  in mpi_smp_completion()
3055 	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;  in mpi_smp_completion()
3056 	t->task_state_flags |= SAS_TASK_STATE_DONE;  in mpi_smp_completion()
3057 	if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {  in mpi_smp_completion()
3058 		spin_unlock_irqrestore(&t->task_state_lock, flags);  in mpi_smp_completion()
3060 			   "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n",  in mpi_smp_completion()
3061 			   t, status, ts->resp, ts->stat);  in mpi_smp_completion()
3064 		spin_unlock_irqrestore(&t->task_state_lock, flags);  in mpi_smp_completion()
3067 		t->task_done(t);  in mpi_smp_completion()
3072  * pm80xx_hw_event_ack_req- For PM8001, some events need to acknowledge to FW.
3078  * @param0: parameter 0.
3087 	memset((u8 *)&payload, 0, sizeof(payload));  in pm80xx_hw_event_ack_req()
3089 	payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |  in pm80xx_hw_event_ack_req()
3090 		((phyId & 0xFF) << 24) | (port_id & 0xFF));  in pm80xx_hw_event_ack_req()
3095 			     sizeof(payload), 0);  in pm80xx_hw_event_ack_req()
3105 	u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);  in hw_event_port_recover()
3106 	u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);  in hw_event_port_recover()
3108 		le32_to_cpu(pPayload->lr_status_evt_portid);  in hw_event_port_recover()
3109 	u8 deviceType = pPayload->sas_identify.dev_type;  in hw_event_port_recover()
3110 	u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);  in hw_event_port_recover()
3111 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];  in hw_event_port_recover()
3112 	u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);  in hw_event_port_recover()
3113 	struct pm8001_port *port = &pm8001_ha->port[port_id];  in hw_event_port_recover()
3120 	port->wide_port_phymap |= (1U << phy_id);  in hw_event_port_recover()
3122 	phy->sas_phy.oob_mode = SAS_OOB_MODE;  in hw_event_port_recover()
3123 	phy->phy_state = PHY_STATE_LINK_UP_SPCV;  in hw_event_port_recover()
3124 	phy->phy_attached = 1;  in hw_event_port_recover()
3128  * hw_event_sas_phy_up - FW tells me a SAS phy up event.
3138 		le32_to_cpu(pPayload->lr_status_evt_portid);  in hw_event_sas_phy_up()
3139 	u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);  in hw_event_sas_phy_up()
3142 		(u8)((lr_status_evt_portid & 0xF0000000) >> 28);  in hw_event_sas_phy_up()
3143 	u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);  in hw_event_sas_phy_up()
3145 		(u8)((phyid_npip_portstate & 0xFF0000) >> 16);  in hw_event_sas_phy_up()
3146 	u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);  in hw_event_sas_phy_up()
3148 	struct pm8001_port *port = &pm8001_ha->port[port_id];  in hw_event_sas_phy_up()
3149 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];  in hw_event_sas_phy_up()
3151 	u8 deviceType = pPayload->sas_identify.dev_type;  in hw_event_sas_phy_up()
3152 	phy->port = port;  in hw_event_sas_phy_up()
3153 	port->port_id = port_id;  in hw_event_sas_phy_up()
3154 	port->port_state = portstate;  in hw_event_sas_phy_up()
3155 	port->wide_port_phymap |= (1U << phy_id);  in hw_event_sas_phy_up()
3156 	phy->phy_state = PHY_STATE_LINK_UP_SPCV;  in hw_event_sas_phy_up()
3169 		port->port_attached = 1;  in hw_event_sas_phy_up()
3174 		port->port_attached = 1;  in hw_event_sas_phy_up()
3179 		port->port_attached = 1;  in hw_event_sas_phy_up()
3187 	phy->phy_type |= PORT_TYPE_SAS;  in hw_event_sas_phy_up()
3188 	phy->identify.device_type = deviceType;  in hw_event_sas_phy_up()
3189 	phy->phy_attached = 1;  in hw_event_sas_phy_up()
3190 	if (phy->identify.device_type == SAS_END_DEVICE)  in hw_event_sas_phy_up()
3191 		phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;  in hw_event_sas_phy_up()
3192 	else if (phy->identify.device_type != SAS_PHY_UNUSED)  in hw_event_sas_phy_up()
3193 		phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;  in hw_event_sas_phy_up()
3194 	phy->sas_phy.oob_mode = SAS_OOB_MODE;  in hw_event_sas_phy_up()
3195 	sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);  in hw_event_sas_phy_up()
3196 	spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);  in hw_event_sas_phy_up()
3197 	memcpy(phy->frame_rcvd, &pPayload->sas_identify,  in hw_event_sas_phy_up()
3198 		sizeof(struct sas_identify_frame)-4);  in hw_event_sas_phy_up()
3199 	phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;  in hw_event_sas_phy_up()
3200 	pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);  in hw_event_sas_phy_up()
3201 	spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);  in hw_event_sas_phy_up()
3202 	if (pm8001_ha->flags == PM8001F_RUN_TIME)  in hw_event_sas_phy_up()
3208  * hw_event_sata_phy_up - FW tells me a SATA phy up event.
3217 	u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);  in hw_event_sata_phy_up()
3219 		le32_to_cpu(pPayload->lr_status_evt_portid);  in hw_event_sata_phy_up()
3221 		(u8)((lr_status_evt_portid & 0xF0000000) >> 28);  in hw_event_sata_phy_up()
3222 	u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);  in hw_event_sata_phy_up()
3224 		(u8)((phyid_npip_portstate & 0xFF0000) >> 16);  in hw_event_sata_phy_up()
3226 	u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);  in hw_event_sata_phy_up()
3228 	struct pm8001_port *port = &pm8001_ha->port[port_id];  in hw_event_sata_phy_up()
3229 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];  in hw_event_sata_phy_up()
3235 	phy->port = port;  in hw_event_sata_phy_up()
3236 	port->port_id = port_id;  in hw_event_sata_phy_up()
3237 	port->port_state = portstate;  in hw_event_sata_phy_up()
3238 	phy->phy_state = PHY_STATE_LINK_UP_SPCV;  in hw_event_sata_phy_up()
3239 	port->port_attached = 1;  in hw_event_sata_phy_up()
3241 	phy->phy_type |= PORT_TYPE_SATA;  in hw_event_sata_phy_up()
3242 	phy->phy_attached = 1;  in hw_event_sata_phy_up()
3243 	phy->sas_phy.oob_mode = SATA_OOB_MODE;  in hw_event_sata_phy_up()
3244 	sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);  in hw_event_sata_phy_up()
3245 	spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);  in hw_event_sata_phy_up()
3246 	memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),  in hw_event_sata_phy_up()
3248 	phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);  in hw_event_sata_phy_up()
3249 	phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;  in hw_event_sata_phy_up()
3250 	phy->identify.device_type = SAS_SATA_DEV;  in hw_event_sata_phy_up()
3251 	pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);  in hw_event_sata_phy_up()
3252 	spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);  in hw_event_sata_phy_up()
3257  * hw_event_phy_down - we should notify the libsas the phy is down.
3268 		le32_to_cpu(pPayload->lr_status_evt_portid);  in hw_event_phy_down()
3269 	u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);  in hw_event_phy_down()
3270 	u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);  in hw_event_phy_down()
3272 		(u8)((phyid_npip_portstate & 0xFF0000) >> 16);  in hw_event_phy_down()
3273 	u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);  in hw_event_phy_down()
3275 	struct pm8001_port *port = &pm8001_ha->port[port_id];  in hw_event_phy_down()
3276 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];  in hw_event_phy_down()
3277 	u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);  in hw_event_phy_down()
3278 	port->port_state = portstate;  in hw_event_phy_down()
3279 	phy->identify.device_type = 0;  in hw_event_phy_down()
3280 	phy->phy_attached = 0;  in hw_event_phy_down()
3294 			phy->phy_type = 0;  in hw_event_phy_down()
3295 			port->port_attached = 0;  in hw_event_phy_down()
3296 			pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,  in hw_event_phy_down()
3297 					port_id, phy_id, 0, 0);  in hw_event_phy_down()
3299 		sas_phy_disconnected(&phy->sas_phy);  in hw_event_phy_down()
3310 		port->port_attached = 0;  in hw_event_phy_down()
3318 			port->port_attached = 0;  in hw_event_phy_down()
3319 			phy->phy_type = 0;  in hw_event_phy_down()
3320 			pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,  in hw_event_phy_down()
3321 					port_id, phy_id, 0, 0);  in hw_event_phy_down()
3323 		sas_phy_disconnected(&phy->sas_phy);  in hw_event_phy_down()
3326 		port->port_attached = 0;  in hw_event_phy_down()
3334 		sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL,  in hw_event_phy_down()
3343 		le32_to_cpu(pPayload->status);  in mpi_phy_start_resp()
3345 		le32_to_cpu(pPayload->phyid) & 0xFF;  in mpi_phy_start_resp()
3346 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];  in mpi_phy_start_resp()
3347 	u32 tag = le32_to_cpu(pPayload->tag);  in mpi_phy_start_resp()
3350 		   "phy start resp status:0x%x, phyid:0x%x, tag 0x%x\n",  in mpi_phy_start_resp()
3352 	if (status == 0)  in mpi_phy_start_resp()
3353 		phy->phy_state = PHY_LINK_DOWN;  in mpi_phy_start_resp()
3355 	if (pm8001_ha->flags == PM8001F_RUN_TIME &&  in mpi_phy_start_resp()
3356 			phy->enable_completion != NULL) {  in mpi_phy_start_resp()
3357 		complete(phy->enable_completion);  in mpi_phy_start_resp()
3358 		phy->enable_completion = NULL;  in mpi_phy_start_resp()
3362 	return 0;  in mpi_phy_start_resp()
3367  * mpi_thermal_hw_event - a thermal hw event has come.
3376 	u32 thermal_event = le32_to_cpu(pPayload->thermal_event);  in mpi_thermal_hw_event()
3377 	u32 rht_lht = le32_to_cpu(pPayload->rht_lht);  in mpi_thermal_hw_event()
3379 	if (thermal_event & 0x40) {  in mpi_thermal_hw_event()
3384 			   ((rht_lht & 0xFF00) >> 8));  in mpi_thermal_hw_event()
3386 	if (thermal_event & 0x10) {  in mpi_thermal_hw_event()
3391 			   ((rht_lht & 0xFF000000) >> 24));  in mpi_thermal_hw_event()
3393 	return 0;  in mpi_thermal_hw_event()
3397  * mpi_hw_event - The hw event has come.
3407 		le32_to_cpu(pPayload->lr_status_evt_portid);  in mpi_hw_event()
3408 	u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);  in mpi_hw_event()
3409 	u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);  in mpi_hw_event()
3411 		(u8)((phyid_npip_portstate & 0xFF0000) >> 16);  in mpi_hw_event()
3412 	u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);  in mpi_hw_event()
3414 		(u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);  in mpi_hw_event()
3416 		(u8)((lr_status_evt_portid & 0x0F000000) >> 24);  in mpi_hw_event()
3417 	struct sas_ha_struct *sas_ha = pm8001_ha->sas;  in mpi_hw_event()
3418 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];  in mpi_hw_event()
3419 	struct pm8001_port *port = &pm8001_ha->port[port_id];  in mpi_hw_event()
3420 	struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];  in mpi_hw_event()
3422 		   "portid:%d phyid:%d event:0x%x status:0x%x\n",  in mpi_hw_event()
3440 		sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD,  in mpi_hw_event()
3445 		phy->phy_state = PHY_LINK_DISABLE;  in mpi_hw_event()
3452 		phy->phy_attached = 0;  in mpi_hw_event()
3460 		pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,  in mpi_hw_event()
3461 			port_id, phy_id, 1, 0);  in mpi_hw_event()
3462 		spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);  in mpi_hw_event()
3463 		sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;  in mpi_hw_event()
3464 		spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);  in mpi_hw_event()
3472 		sas_phy_disconnected(&phy->sas_phy);  in mpi_hw_event()
3473 		phy->phy_attached = 0;  in mpi_hw_event()
3474 		sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC);  in mpi_hw_event()
3478 		spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);  in mpi_hw_event()
3479 		sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;  in mpi_hw_event()
3480 		spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);  in mpi_hw_event()
3488 		pm80xx_hw_event_ack_req(pm8001_ha, 0,  in mpi_hw_event()
3489 			HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);  in mpi_hw_event()
3495 		pm80xx_hw_event_ack_req(pm8001_ha, 0,  in mpi_hw_event()
3497 			port_id, phy_id, 0, 0);  in mpi_hw_event()
3503 		pm80xx_hw_event_ack_req(pm8001_ha, 0,  in mpi_hw_event()
3505 			port_id, phy_id, 0, 0);  in mpi_hw_event()
3511 		pm80xx_hw_event_ack_req(pm8001_ha, 0,  in mpi_hw_event()
3513 			port_id, phy_id, 0, 0);  in mpi_hw_event()
3521 		spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);  in mpi_hw_event()
3522 		sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;  in mpi_hw_event()
3523 		spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);  in mpi_hw_event()
3531 		pm80xx_hw_event_ack_req(pm8001_ha, 0,  in mpi_hw_event()
3533 			port_id, phy_id, 0, 0);  in mpi_hw_event()
3544 		phy->phy_attached = 0;  in mpi_hw_event()
3552 		pm80xx_hw_event_ack_req(pm8001_ha, 0,  in mpi_hw_event()
3554 			port_id, phy_id, 0, 0);  in mpi_hw_event()
3556 		phy->phy_attached = 0;  in mpi_hw_event()
3564 		if (!pm8001_ha->phy[phy_id].reset_completion) {  in mpi_hw_event()
3565 			pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,  in mpi_hw_event()
3566 				port_id, phy_id, 0, 0);  in mpi_hw_event()
3569 		phy->phy_attached = 0;  in mpi_hw_event()
3570 		port->port_state = portstate;  in mpi_hw_event()
3573 		if (pm8001_ha->phy[phy_id].reset_completion) {  in mpi_hw_event()
3574 			pm8001_ha->phy[phy_id].port_reset_status =  in mpi_hw_event()
3576 			complete(pm8001_ha->phy[phy_id].reset_completion);  in mpi_hw_event()
3577 			pm8001_ha->phy[phy_id].reset_completion = NULL;  in mpi_hw_event()
3584 		pm80xx_hw_event_ack_req(pm8001_ha, 0,  in mpi_hw_event()
3586 			port_id, phy_id, 0, 0);  in mpi_hw_event()
3587 		for (i = 0; i < pm8001_ha->chip->n_phy; i++) {  in mpi_hw_event()
3588 			if (port->wide_port_phymap & (1 << i)) {  in mpi_hw_event()
3589 				phy = &pm8001_ha->phy[i];  in mpi_hw_event()
3590 				sas_notify_phy_event(&phy->sas_phy,  in mpi_hw_event()
3592 				port->wide_port_phymap &= ~(1 << i);  in mpi_hw_event()
3606 		if (pm8001_ha->phy[phy_id].reset_completion) {  in mpi_hw_event()
3607 			pm8001_ha->phy[phy_id].port_reset_status =  in mpi_hw_event()
3609 			complete(pm8001_ha->phy[phy_id].reset_completion);  in mpi_hw_event()
3610 			pm8001_ha->phy[phy_id].reset_completion = NULL;  in mpi_hw_event()
3612 		phy->phy_attached = 1;  in mpi_hw_event()
3613 		phy->phy_state = PHY_STATE_LINK_UP_SPCV;  in mpi_hw_event()
3614 		port->port_state = portstate;  in mpi_hw_event()
3621 			   "Unknown event portid:%d phyid:%d event:0x%x status:0x%x\n",  in mpi_hw_event()
3625 	return 0;  in mpi_hw_event()
3629  * mpi_phy_stop_resp - SPCv specific
3638 		le32_to_cpu(pPayload->status);  in mpi_phy_stop_resp()
3640 		le32_to_cpu(pPayload->phyid) & 0xFF;  in mpi_phy_stop_resp()
3641 	struct pm8001_phy *phy = &pm8001_ha->phy[phyid];  in mpi_phy_stop_resp()
3642 	u32 tag = le32_to_cpu(pPayload->tag);  in mpi_phy_stop_resp()
3644 	pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x tag 0x%x\n", phyid,  in mpi_phy_stop_resp()
3648 		phy->phy_state = PHY_LINK_DISABLE;  in mpi_phy_stop_resp()
3649 		phy->sas_phy.phy->negotiated_linkrate = SAS_PHY_DISABLED;  in mpi_phy_stop_resp()
3650 		phy->sas_phy.linkrate = SAS_PHY_DISABLED;  in mpi_phy_stop_resp()
3654 	return 0;  in mpi_phy_stop_resp()
3658  * mpi_set_controller_config_resp - SPCv specific
3667 	u32 status = le32_to_cpu(pPayload->status);  in mpi_set_controller_config_resp()
3668 	u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);  in mpi_set_controller_config_resp()
3669 	u32 tag = le32_to_cpu(pPayload->tag);  in mpi_set_controller_config_resp()
3672 		   "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x tag 0x%x\n",  in mpi_set_controller_config_resp()
3675 	return 0;  in mpi_set_controller_config_resp()
3679  * mpi_get_controller_config_resp - SPCv specific
3688 	return 0;  in mpi_get_controller_config_resp()
3692  * mpi_get_phy_profile_resp - SPCv specific
3701 	return 0;  in mpi_get_phy_profile_resp()
3705  * mpi_flash_op_ext_resp - SPCv specific
3713 	return 0;  in mpi_flash_op_ext_resp()
3717  * mpi_set_phy_profile_resp - SPCv specific
3726 	int rc = 0;  in mpi_set_phy_profile_resp()
3729 	u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);  in mpi_set_phy_profile_resp()
3730 	u32 status = le32_to_cpu(pPayload->status);  in mpi_set_phy_profile_resp()
3732 	tag = le32_to_cpu(pPayload->tag);  in mpi_set_phy_profile_resp()
3733 	page_code = (u8)((ppc_phyid & 0xFF00) >> 8);  in mpi_set_phy_profile_resp()
3737 			   "PhyProfile command failed  with status 0x%08X\n",  in mpi_set_phy_profile_resp()
3739 		rc = -1;  in mpi_set_phy_profile_resp()
3742 			pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n",  in mpi_set_phy_profile_resp()
3744 			rc = -1;  in mpi_set_phy_profile_resp()
3752  * mpi_kek_management_resp - SPCv specific
3761 	u32 status = le32_to_cpu(pPayload->status);  in mpi_kek_management_resp()
3762 	u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);  in mpi_kek_management_resp()
3763 	u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);  in mpi_kek_management_resp()
3766 		   "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",  in mpi_kek_management_resp()
3769 	return 0;  in mpi_kek_management_resp()
3773  * mpi_dek_management_resp - SPCv specific
3782 	return 0;  in mpi_dek_management_resp()
3786  * ssp_coalesced_comp_resp - SPCv specific
3795 	return 0;  in ssp_coalesced_comp_resp()
3799  * process_one_iomb - process one outbound Queue memory block
3808 	u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);  in process_one_iomb()
3981 			   "Unknown outbound Queue IOMB OPC = 0x%x\n", opc);  in process_one_iomb()
3988 	pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n",  in print_scratchpad_registers()
3989 		   pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));  in print_scratchpad_registers()
3990 	pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n",  in print_scratchpad_registers()
3991 		   pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1));  in print_scratchpad_registers()
3992 	pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n",  in print_scratchpad_registers()
3993 		   pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2));  in print_scratchpad_registers()
3994 	pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n",  in print_scratchpad_registers()
3995 		   pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));  in print_scratchpad_registers()
3996 	pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",  in print_scratchpad_registers()
3997 		   pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0));  in print_scratchpad_registers()
3998 	pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",  in print_scratchpad_registers()
3999 		   pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1));  in print_scratchpad_registers()
4000 	pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",  in print_scratchpad_registers()
4001 		   pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2));  in print_scratchpad_registers()
4002 	pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",  in print_scratchpad_registers()
4003 		   pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3));  in print_scratchpad_registers()
4004 	pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",  in print_scratchpad_registers()
4005 		   pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4));  in print_scratchpad_registers()
4006 	pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",  in print_scratchpad_registers()
4007 		   pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5));  in print_scratchpad_registers()
4008 	pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",  in print_scratchpad_registers()
4009 		   pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_0));  in print_scratchpad_registers()
4010 	pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",  in print_scratchpad_registers()
4011 		   pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_1));  in print_scratchpad_registers()
4024 	 * pm8001_ha->max_q_num - 1 through pm8001_ha->main_cfg_tbl.pm80xx_tbl.  in process_oq()
4027 	if (vec == (pm8001_ha->max_q_num - 1)) {  in process_oq()
4030 		if (pm8001_ha->chip_id == chip_8008 ||  in process_oq()
4031 		    pm8001_ha->chip_id == chip_8009)  in process_oq()
4036 		regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);  in process_oq()
4038 			pm8001_ha->controller_fatal_error = true;  in process_oq()
4040 				   "Firmware Fatal error! Regval:0x%x\n",  in process_oq()
4046 			/*read scratchpad rsvd 0 register*/  in process_oq()
4047 			regval = pm8001_cr32(pm8001_ha, 0,  in process_oq()
4054 				pm8001_cw32(pm8001_ha, 0,  in process_oq()
4056 					    0x00000000);  in process_oq()
4063 	circularQ = &pm8001_ha->outbnd_q_tbl[vec];  in process_oq()
4064 	spin_lock_irqsave(&circularQ->oq_lock, circularQ->lock_flags);  in process_oq()
4066 		/* spurious interrupt during setup if kexec-ing and  in process_oq()
4067 		 * driver doing a doorbell access w/ the pre-kexec oq  in process_oq()
4070 		if (!circularQ->pi_virt)  in process_oq()
4076 						(void *)(pMsg1 - 4));  in process_oq()
4083 			circularQ->producer_index =  in process_oq()
4084 				cpu_to_le32(pm8001_read_32(circularQ->pi_virt));  in process_oq()
4085 			if (le32_to_cpu(circularQ->producer_index) ==  in process_oq()
4086 				circularQ->consumer_idx)  in process_oq()
4091 	spin_unlock_irqrestore(&circularQ->oq_lock, circularQ->lock_flags);  in process_oq()
4106 	psmp_cmd->tag = hTag;  in build_smp_cmd()
4107 	psmp_cmd->device_id = cpu_to_le32(deviceID);  in build_smp_cmd()
4109 		length = length - 4; /* subtract crc */  in build_smp_cmd()
4110 		psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);  in build_smp_cmd()
4112 		psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));  in build_smp_cmd()
4117  * pm80xx_chip_smp_req - send an SMP task to FW
4125 	struct sas_task *task = ccb->task;  in pm80xx_chip_smp_req()
4126 	struct domain_device *dev = task->dev;  in pm80xx_chip_smp_req()
4127 	struct pm8001_device *pm8001_dev = dev->lldd_dev;  in pm80xx_chip_smp_req()
4136 	memset(&smp_cmd, 0, sizeof(smp_cmd));  in pm80xx_chip_smp_req()
4138 	 * DMA-map SMP request, response buffers  in pm80xx_chip_smp_req()
4140 	sg_req = &task->smp_task.smp_req;  in pm80xx_chip_smp_req()
4141 	elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);  in pm80xx_chip_smp_req()
4143 		return -ENOMEM;  in pm80xx_chip_smp_req()
4146 	sg_resp = &task->smp_task.smp_resp;  in pm80xx_chip_smp_req()
4147 	elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);  in pm80xx_chip_smp_req()
4149 		rc = -ENOMEM;  in pm80xx_chip_smp_req()
4154 	if ((req_len & 0x3) || (resp_len & 0x3)) {  in pm80xx_chip_smp_req()
4155 		rc = -EINVAL;  in pm80xx_chip_smp_req()
4160 	smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);  in pm80xx_chip_smp_req()
4162 	length = sg_req->length;  in pm80xx_chip_smp_req()
4163 	pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length);  in pm80xx_chip_smp_req()
4164 	if (!(length - 8))  in pm80xx_chip_smp_req()
4165 		pm8001_ha->smp_exp_mode = SMP_DIRECT;  in pm80xx_chip_smp_req()
4167 		pm8001_ha->smp_exp_mode = SMP_INDIRECT;  in pm80xx_chip_smp_req()
4170 	smp_req = &task->smp_task.smp_req;  in pm80xx_chip_smp_req()
4172 	payload = to + smp_req->offset;  in pm80xx_chip_smp_req()
4175 	if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {  in pm80xx_chip_smp_req()
4179 		for (i = 0; i < 4; i++)  in pm80xx_chip_smp_req()
4184 				(&task->smp_task.smp_req) + 4);  in pm80xx_chip_smp_req()
4187 			cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);  in pm80xx_chip_smp_req()
4190 					(&task->smp_task.smp_resp));  in pm80xx_chip_smp_req()
4193 					(&task->smp_task.smp_resp)-4);  in pm80xx_chip_smp_req()
4197 					(&task->smp_task.smp_req));  in pm80xx_chip_smp_req()
4199 			cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);  in pm80xx_chip_smp_req()
4202 				(&task->smp_task.smp_resp));  in pm80xx_chip_smp_req()
4205 			((u32)sg_dma_len(&task->smp_task.smp_resp)-4);  in pm80xx_chip_smp_req()
4207 	if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {  in pm80xx_chip_smp_req()
4209 		for (i = 0; i < length; i++)  in pm80xx_chip_smp_req()
4225 	build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,  in pm80xx_chip_smp_req()
4226 				&smp_cmd, pm8001_ha->smp_exp_mode, length);  in pm80xx_chip_smp_req()
4227 	rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &smp_cmd,  in pm80xx_chip_smp_req()
4228 				  sizeof(smp_cmd), 0);  in pm80xx_chip_smp_req()
4231 	return 0;  in pm80xx_chip_smp_req()
4234 	dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,  in pm80xx_chip_smp_req()
4237 	dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,  in pm80xx_chip_smp_req()
4244 	u8 cmd = task->ssp_task.cmd->cmnd[0];  in check_enc_sas_cmd()
4249 		return 0;  in check_enc_sas_cmd()
4254 	int ret = 0;  in check_enc_sat_cmd()
4255 	switch (task->ata_task.fis.command) {  in check_enc_sat_cmd()
4269 		ret = 0;  in check_enc_sat_cmd()
4280 		return 0;  in pm80xx_chip_get_q_index()
4286  * pm80xx_chip_ssp_io_req - send an SSP task to FW
4293 	struct sas_task *task = ccb->task;  in pm80xx_chip_ssp_io_req()
4294 	struct domain_device *dev = task->dev;  in pm80xx_chip_ssp_io_req()
4295 	struct pm8001_device *pm8001_dev = dev->lldd_dev;  in pm80xx_chip_ssp_io_req()
4297 	u32 tag = ccb->ccb_tag;  in pm80xx_chip_ssp_io_req()
4303 	memset(&ssp_cmd, 0, sizeof(ssp_cmd));  in pm80xx_chip_ssp_io_req()
4304 	memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);  in pm80xx_chip_ssp_io_req()
4306 	/* data address domain added for spcv; set to 0 by host,  in pm80xx_chip_ssp_io_req()
4308 	 * 0 for SAS 1.1 and SAS 2.0 compatible TLR  in pm80xx_chip_ssp_io_req()
4311 		cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);  in pm80xx_chip_ssp_io_req()
4312 	ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);  in pm80xx_chip_ssp_io_req()
4313 	ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);  in pm80xx_chip_ssp_io_req()
4315 	ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);  in pm80xx_chip_ssp_io_req()
4316 	memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,  in pm80xx_chip_ssp_io_req()
4317 		       task->ssp_task.cmd->cmd_len);  in pm80xx_chip_ssp_io_req()
4321 	if (pm8001_ha->chip->encrypt &&  in pm80xx_chip_ssp_io_req()
4322 		!(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {  in pm80xx_chip_ssp_io_req()
4324 			   "Encryption enabled.Sending Encrypt SAS command 0x%x\n",  in pm80xx_chip_ssp_io_req()
4325 			   task->ssp_task.cmd->cmnd[0]);  in pm80xx_chip_ssp_io_req()
4327 		/* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/  in pm80xx_chip_ssp_io_req()
4329 			((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);  in pm80xx_chip_ssp_io_req()
4332 		if (task->num_scatter > 1) {  in pm80xx_chip_ssp_io_req()
4333 			pm8001_chip_make_sg(task->scatter,  in pm80xx_chip_ssp_io_req()
4334 						ccb->n_elem, ccb->buf_prd);  in pm80xx_chip_ssp_io_req()
4335 			phys_addr = ccb->ccb_dma_handle;  in pm80xx_chip_ssp_io_req()
4341 		} else if (task->num_scatter == 1) {  in pm80xx_chip_ssp_io_req()
4342 			u64 dma_addr = sg_dma_address(task->scatter);  in pm80xx_chip_ssp_io_req()
4348 			ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);  in pm80xx_chip_ssp_io_req()
4349 			ssp_cmd.enc_esgl = 0;  in pm80xx_chip_ssp_io_req()
4352 			end_addr = dma_addr + le32_to_cpu(ssp_cmd.enc_len) - 1;  in pm80xx_chip_ssp_io_req()
4358 …"The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x h…  in pm80xx_chip_ssp_io_req()
4362 				pm8001_chip_make_sg(task->scatter, 1,  in pm80xx_chip_ssp_io_req()
4363 					ccb->buf_prd);  in pm80xx_chip_ssp_io_req()
4364 				phys_addr = ccb->ccb_dma_handle;  in pm80xx_chip_ssp_io_req()
4371 		} else if (task->num_scatter == 0) {  in pm80xx_chip_ssp_io_req()
4372 			ssp_cmd.enc_addr_low = 0;  in pm80xx_chip_ssp_io_req()
4373 			ssp_cmd.enc_addr_high = 0;  in pm80xx_chip_ssp_io_req()
4374 			ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);  in pm80xx_chip_ssp_io_req()
4375 			ssp_cmd.enc_esgl = 0;  in pm80xx_chip_ssp_io_req()
4378 		/* XTS mode. All other fields are 0 */  in pm80xx_chip_ssp_io_req()
4379 		ssp_cmd.key_cmode = cpu_to_le32(0x6 << 4);  in pm80xx_chip_ssp_io_req()
4382 		ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |  in pm80xx_chip_ssp_io_req()
4383 						(task->ssp_task.cmd->cmnd[3] << 16) |  in pm80xx_chip_ssp_io_req()
4384 						(task->ssp_task.cmd->cmnd[4] << 8) |  in pm80xx_chip_ssp_io_req()
4385 						(task->ssp_task.cmd->cmnd[5]));  in pm80xx_chip_ssp_io_req()
4388 			   "Sending Normal SAS command 0x%x inb q %x\n",  in pm80xx_chip_ssp_io_req()
4389 			   task->ssp_task.cmd->cmnd[0], q_index);  in pm80xx_chip_ssp_io_req()
4391 		if (task->num_scatter > 1) {  in pm80xx_chip_ssp_io_req()
4392 			pm8001_chip_make_sg(task->scatter, ccb->n_elem,  in pm80xx_chip_ssp_io_req()
4393 					ccb->buf_prd);  in pm80xx_chip_ssp_io_req()
4394 			phys_addr = ccb->ccb_dma_handle;  in pm80xx_chip_ssp_io_req()
4400 		} else if (task->num_scatter == 1) {  in pm80xx_chip_ssp_io_req()
4401 			u64 dma_addr = sg_dma_address(task->scatter);  in pm80xx_chip_ssp_io_req()
4406 			ssp_cmd.len = cpu_to_le32(task->total_xfer_len);  in pm80xx_chip_ssp_io_req()
4407 			ssp_cmd.esgl = 0;  in pm80xx_chip_ssp_io_req()
4410 			end_addr = dma_addr + le32_to_cpu(ssp_cmd.len) - 1;  in pm80xx_chip_ssp_io_req()
4415 …"The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x h…  in pm80xx_chip_ssp_io_req()
4419 				pm8001_chip_make_sg(task->scatter, 1,  in pm80xx_chip_ssp_io_req()
4420 					ccb->buf_prd);  in pm80xx_chip_ssp_io_req()
4421 				phys_addr = ccb->ccb_dma_handle;  in pm80xx_chip_ssp_io_req()
4428 		} else if (task->num_scatter == 0) {  in pm80xx_chip_ssp_io_req()
4429 			ssp_cmd.addr_low = 0;  in pm80xx_chip_ssp_io_req()
4430 			ssp_cmd.addr_high = 0;  in pm80xx_chip_ssp_io_req()
4431 			ssp_cmd.len = cpu_to_le32(task->total_xfer_len);  in pm80xx_chip_ssp_io_req()
4432 			ssp_cmd.esgl = 0;  in pm80xx_chip_ssp_io_req()
4443 	struct sas_task *task = ccb->task;  in pm80xx_chip_sata_req()
4444 	struct domain_device *dev = task->dev;  in pm80xx_chip_sata_req()
4445 	struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;  in pm80xx_chip_sata_req()
4446 	struct ata_queued_cmd *qc = task->uldd_task;  in pm80xx_chip_sata_req()
4447 	u32 tag = ccb->ccb_tag, q_index;  in pm80xx_chip_sata_req()
4449 	u32 hdr_tag, ncg_tag = 0;  in pm80xx_chip_sata_req()
4452 	u32 ATAP = 0x0;  in pm80xx_chip_sata_req()
4453 	u32 dir, retfis = 0;  in pm80xx_chip_sata_req()
4455 	memset(&sata_cmd, 0, sizeof(sata_cmd));  in pm80xx_chip_sata_req()
4459 	if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) {  in pm80xx_chip_sata_req()
4460 		ATAP = 0x04; /* no data*/  in pm80xx_chip_sata_req()
4462 	} else if (likely(!task->ata_task.device_control_reg_update)) {  in pm80xx_chip_sata_req()
4463 		if (task->ata_task.use_ncq &&  in pm80xx_chip_sata_req()
4464 		    dev->sata_dev.class != ATA_DEV_ATAPI) {  in pm80xx_chip_sata_req()
4465 			ATAP = 0x07; /* FPDMA */  in pm80xx_chip_sata_req()
4467 		} else if (task->ata_task.dma_xfer) {  in pm80xx_chip_sata_req()
4468 			ATAP = 0x06; /* DMA */  in pm80xx_chip_sata_req()
4471 			ATAP = 0x05; /* PIO*/  in pm80xx_chip_sata_req()
4475 	if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {  in pm80xx_chip_sata_req()
4476 		task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);  in pm80xx_chip_sata_req()
4479 	dir = data_dir_flags[task->data_dir] << 8;  in pm80xx_chip_sata_req()
4481 	sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);  in pm80xx_chip_sata_req()
4482 	sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);  in pm80xx_chip_sata_req()
4483 	if (task->ata_task.return_fis_on_success)  in pm80xx_chip_sata_req()
4485 	sata_cmd.sata_fis = task->ata_task.fis;  in pm80xx_chip_sata_req()
4486 	if (likely(!task->ata_task.device_control_reg_update))  in pm80xx_chip_sata_req()
4487 		sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */  in pm80xx_chip_sata_req()
4488 	sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */  in pm80xx_chip_sata_req()
4491 	if (pm8001_ha->chip->encrypt &&  in pm80xx_chip_sata_req()
4492 		!(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {  in pm80xx_chip_sata_req()
4494 			   "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",  in pm80xx_chip_sata_req()
4497 		/* set encryption bit; dad (bits 0-1) is 0 */  in pm80xx_chip_sata_req()
4499 			cpu_to_le32((retfis << 24) | ((ncg_tag & 0xff) << 16) |  in pm80xx_chip_sata_req()
4500 				    ((ATAP & 0x3f) << 10) | 0x20 | dir);  in pm80xx_chip_sata_req()
4502 		if (task->num_scatter > 1) {  in pm80xx_chip_sata_req()
4503 			pm8001_chip_make_sg(task->scatter,  in pm80xx_chip_sata_req()
4504 						ccb->n_elem, ccb->buf_prd);  in pm80xx_chip_sata_req()
4505 			phys_addr = ccb->ccb_dma_handle;  in pm80xx_chip_sata_req()
4511 		} else if (task->num_scatter == 1) {  in pm80xx_chip_sata_req()
4512 			u64 dma_addr = sg_dma_address(task->scatter);  in pm80xx_chip_sata_req()
4518 			sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);  in pm80xx_chip_sata_req()
4519 			sata_cmd.enc_esgl = 0;  in pm80xx_chip_sata_req()
4522 			end_addr = dma_addr + le32_to_cpu(sata_cmd.enc_len) - 1;  in pm80xx_chip_sata_req()
4527 …"The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x h…  in pm80xx_chip_sata_req()
4531 				pm8001_chip_make_sg(task->scatter, 1,  in pm80xx_chip_sata_req()
4532 					ccb->buf_prd);  in pm80xx_chip_sata_req()
4533 				phys_addr = ccb->ccb_dma_handle;  in pm80xx_chip_sata_req()
4541 		} else if (task->num_scatter == 0) {  in pm80xx_chip_sata_req()
4542 			sata_cmd.enc_addr_low = 0;  in pm80xx_chip_sata_req()
4543 			sata_cmd.enc_addr_high = 0;  in pm80xx_chip_sata_req()
4544 			sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);  in pm80xx_chip_sata_req()
4545 			sata_cmd.enc_esgl = 0;  in pm80xx_chip_sata_req()
4547 		/* XTS mode. All other fields are 0 */  in pm80xx_chip_sata_req()
4548 		sata_cmd.key_index_mode = cpu_to_le32(0x6 << 4);  in pm80xx_chip_sata_req()
4561 			   "Sending Normal SATA command 0x%x inb %x\n",  in pm80xx_chip_sata_req()
4563 		/* dad (bits 0-1) is 0 */  in pm80xx_chip_sata_req()
4565 			cpu_to_le32((retfis << 24) | ((ncg_tag & 0xff) << 16) |  in pm80xx_chip_sata_req()
4566 				    ((ATAP & 0x3f) << 10) | dir);  in pm80xx_chip_sata_req()
4568 		if (task->num_scatter > 1) {  in pm80xx_chip_sata_req()
4569 			pm8001_chip_make_sg(task->scatter,  in pm80xx_chip_sata_req()
4570 					ccb->n_elem, ccb->buf_prd);  in pm80xx_chip_sata_req()
4571 			phys_addr = ccb->ccb_dma_handle;  in pm80xx_chip_sata_req()
4575 		} else if (task->num_scatter == 1) {  in pm80xx_chip_sata_req()
4576 			u64 dma_addr = sg_dma_address(task->scatter);  in pm80xx_chip_sata_req()
4580 			sata_cmd.len = cpu_to_le32(task->total_xfer_len);  in pm80xx_chip_sata_req()
4581 			sata_cmd.esgl = 0;  in pm80xx_chip_sata_req()
4584 			end_addr = dma_addr + le32_to_cpu(sata_cmd.len) - 1;  in pm80xx_chip_sata_req()
4589 …"The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x ha…  in pm80xx_chip_sata_req()
4593 				pm8001_chip_make_sg(task->scatter, 1,  in pm80xx_chip_sata_req()
4594 					ccb->buf_prd);  in pm80xx_chip_sata_req()
4595 				phys_addr = ccb->ccb_dma_handle;  in pm80xx_chip_sata_req()
4600 		} else if (task->num_scatter == 0) {  in pm80xx_chip_sata_req()
4601 			sata_cmd.addr_low = 0;  in pm80xx_chip_sata_req()
4602 			sata_cmd.addr_high = 0;  in pm80xx_chip_sata_req()
4603 			sata_cmd.len = cpu_to_le32(task->total_xfer_len);  in pm80xx_chip_sata_req()
4604 			sata_cmd.esgl = 0;  in pm80xx_chip_sata_req()
4608 		sata_cmd.atapi_scsi_cdb[0] =  in pm80xx_chip_sata_req()
4609 			cpu_to_le32(((task->ata_task.atapi_packet[0]) |  in pm80xx_chip_sata_req()
4610 				     (task->ata_task.atapi_packet[1] << 8) |  in pm80xx_chip_sata_req()
4611 				     (task->ata_task.atapi_packet[2] << 16) |  in pm80xx_chip_sata_req()
4612 				     (task->ata_task.atapi_packet[3] << 24)));  in pm80xx_chip_sata_req()
4614 			cpu_to_le32(((task->ata_task.atapi_packet[4]) |  in pm80xx_chip_sata_req()
4615 				     (task->ata_task.atapi_packet[5] << 8) |  in pm80xx_chip_sata_req()
4616 				     (task->ata_task.atapi_packet[6] << 16) |  in pm80xx_chip_sata_req()
4617 				     (task->ata_task.atapi_packet[7] << 24)));  in pm80xx_chip_sata_req()
4619 			cpu_to_le32(((task->ata_task.atapi_packet[8]) |  in pm80xx_chip_sata_req()
4620 				     (task->ata_task.atapi_packet[9] << 8) |  in pm80xx_chip_sata_req()
4621 				     (task->ata_task.atapi_packet[10] << 16) |  in pm80xx_chip_sata_req()
4622 				     (task->ata_task.atapi_packet[11] << 24)));  in pm80xx_chip_sata_req()
4624 			cpu_to_le32(((task->ata_task.atapi_packet[12]) |  in pm80xx_chip_sata_req()
4625 				     (task->ata_task.atapi_packet[13] << 8) |  in pm80xx_chip_sata_req()
4626 				     (task->ata_task.atapi_packet[14] << 16) |  in pm80xx_chip_sata_req()
4627 				     (task->ata_task.atapi_packet[15] << 24)));  in pm80xx_chip_sata_req()
4630 	trace_pm80xx_request_issue(pm8001_ha->id,  in pm80xx_chip_sata_req()
4631 				ccb->device ? ccb->device->attached_phy : PM8001_MAX_PHYS,  in pm80xx_chip_sata_req()
4632 				ccb->ccb_tag, opc,  in pm80xx_chip_sata_req()
4633 				qc ? qc->tf.command : 0, // ata opcode  in pm80xx_chip_sata_req()
4634 				ccb->device ? atomic_read(&ccb->device->running_req) : 0);  in pm80xx_chip_sata_req()
4640  * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4658 	memset(&payload, 0, sizeof(payload));  in pm80xx_chip_phy_start_req()
4664 			LINKMODE_AUTO | pm8001_ha->link_rate | phy_id);  in pm80xx_chip_phy_start_req()
4677 		&pm8001_ha->phy[phy_id].dev_sas_addr, SAS_ADDR_SIZE);  in pm80xx_chip_phy_start_req()
4680 	return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload,  in pm80xx_chip_phy_start_req()
4681 				    sizeof(payload), 0);  in pm80xx_chip_phy_start_req()
4685  * pm80xx_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4703 	memset(&payload, 0, sizeof(payload));  in pm80xx_chip_phy_stop_req()
4707 	return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload,  in pm80xx_chip_phy_stop_req()
4708 				    sizeof(payload), 0);  in pm80xx_chip_phy_stop_req()
4719 	u32 stp_sspsmp_sata = 0x4;  in pm80xx_chip_reg_dev_req()
4723 	u8 retryFlag = 0x1;  in pm80xx_chip_reg_dev_req()
4724 	u16 firstBurstSize = 0;  in pm80xx_chip_reg_dev_req()
4726 	struct domain_device *dev = pm8001_dev->sas_device;  in pm80xx_chip_reg_dev_req()
4727 	struct domain_device *parent_dev = dev->parent;  in pm80xx_chip_reg_dev_req()
4728 	struct pm8001_port *port = dev->port->lldd_port;  in pm80xx_chip_reg_dev_req()
4730 	memset(&payload, 0, sizeof(payload));  in pm80xx_chip_reg_dev_req()
4733 		return -SAS_QUEUE_FULL;  in pm80xx_chip_reg_dev_req()
4735 	payload.tag = cpu_to_le32(ccb->ccb_tag);  in pm80xx_chip_reg_dev_req()
4738 		stp_sspsmp_sata = 0x02; /*direct attached sata */  in pm80xx_chip_reg_dev_req()
4740 		if (pm8001_dev->dev_type == SAS_SATA_DEV)  in pm80xx_chip_reg_dev_req()
4741 			stp_sspsmp_sata = 0x00; /* stp*/  in pm80xx_chip_reg_dev_req()
4742 		else if (pm8001_dev->dev_type == SAS_END_DEVICE ||  in pm80xx_chip_reg_dev_req()
4743 			dev_is_expander(pm8001_dev->dev_type))  in pm80xx_chip_reg_dev_req()
4744 			stp_sspsmp_sata = 0x01; /*ssp or smp*/  in pm80xx_chip_reg_dev_req()
4746 	if (parent_dev && dev_is_expander(parent_dev->dev_type))  in pm80xx_chip_reg_dev_req()
4747 		phy_id = parent_dev->ex_dev.ex_phy->phy_id;  in pm80xx_chip_reg_dev_req()
4749 		phy_id = pm8001_dev->attached_phy;  in pm80xx_chip_reg_dev_req()
4753 	linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?  in pm80xx_chip_reg_dev_req()
4754 			pm8001_dev->sas_device->linkrate : dev->port->linkrate;  in pm80xx_chip_reg_dev_req()
4757 		cpu_to_le32(((port->port_id) & 0xFF) |  in pm80xx_chip_reg_dev_req()
4758 		((phy_id & 0xFF) << 8));  in pm80xx_chip_reg_dev_req()
4760 	payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |  in pm80xx_chip_reg_dev_req()
4761 		((linkrate & 0x0F) << 24) |  in pm80xx_chip_reg_dev_req()
4762 		((stp_sspsmp_sata & 0x03) << 28));  in pm80xx_chip_reg_dev_req()
4764 		cpu_to_le32(ITNT | (firstBurstSize * 0x10000));  in pm80xx_chip_reg_dev_req()
4766 	memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,  in pm80xx_chip_reg_dev_req()
4770 		   "register device req phy_id 0x%x port_id 0x%x\n", phy_id,  in pm80xx_chip_reg_dev_req()
4771 		   (port->port_id & 0xFF));  in pm80xx_chip_reg_dev_req()
4772 	rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,  in pm80xx_chip_reg_dev_req()
4773 			sizeof(payload), 0);  in pm80xx_chip_reg_dev_req()
4781  * pm80xx_chip_phy_ctl_req - support the local phy operation
4794 	memset(&payload, 0, sizeof(payload));  in pm80xx_chip_phy_ctl_req()
4801 		cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));  in pm80xx_chip_phy_ctl_req()
4803 	rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,  in pm80xx_chip_phy_ctl_req()
4804 				  sizeof(payload), 0);  in pm80xx_chip_phy_ctl_req()
4815 	if (pm8001_ha->use_msix)  in pm80xx_chip_is_our_interrupt()
4818 	value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);  in pm80xx_chip_is_our_interrupt()
4821 	return 0;  in pm80xx_chip_is_our_interrupt()
4825  * pm80xx_chip_isr - PM8001 isr handler.
4834 		   "irq vec %d, ODMR:0x%x\n",  in pm80xx_chip_isr()
4835 		   vec, pm8001_cr32(pm8001_ha, 0, 0x30));  in pm80xx_chip_isr()
4845 	u32 tag, i, j = 0;  in mpi_set_phy_profile_req()
4850 	memset(&payload, 0, sizeof(payload));  in mpi_set_phy_profile_req()
4859 		cpu_to_le32(((operation & 0xF) << 8) | (phyid  & 0xFF));  in mpi_set_phy_profile_req()
4863 	for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {  in mpi_set_phy_profile_req()
4867 	rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,  in mpi_set_phy_profile_req()
4868 				  sizeof(payload), 0);  in mpi_set_phy_profile_req()
4878 	for (i = 0; i < pm8001_ha->chip->n_phy; i++) {  in pm8001_set_phy_profile()
4893 	memset(&payload, 0, sizeof(payload));  in pm8001_set_phy_profile_single()
4905 		cpu_to_le32(((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)  in pm8001_set_phy_profile_single()
4906 			    | (phy & 0xFF));  in pm8001_set_phy_profile_single()
4908 	for (i = 0; i < length; i++)  in pm8001_set_phy_profile_single()
4911 	rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,  in pm8001_set_phy_profile_single()
4912 			sizeof(payload), 0);  in pm8001_set_phy_profile_single()