Lines Matching +full:0 +full:x7000f000
66 #define SCU_VIIT_ENTRY_ID_MASK (0xC0000000)
69 #define SCU_VIIT_ENTRY_FUNCTION_MASK (0x0FF00000)
72 #define SCU_VIIT_ENTRY_IPPTMODE_MASK (0x0001F800)
75 #define SCU_VIIT_ENTRY_LPVIE_MASK (0x00000F00)
78 #define SCU_VIIT_ENTRY_STATUS_MASK (0x000000FF)
79 #define SCU_VIIT_ENTRY_STATUS_SHIFT (0)
81 #define SCU_VIIT_ENTRY_ID_INVALID (0 << SCU_VIIT_ENTRY_ID_SHIFT)
86 #define SCU_VIIT_IPPT_SSP_INITIATOR (0x01 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
87 #define SCU_VIIT_IPPT_SMP_INITIATOR (0x02 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
88 #define SCU_VIIT_IPPT_STP_INITIATOR (0x04 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
96 #define SCU_VIIT_STATUS_RNC_VALID (0x01 << SCU_VIIT_ENTRY_STATUS_SHIFT)
97 #define SCU_VIIT_STATUS_ADDRESS_VALID (0x02 << SCU_VIIT_ENTRY_STATUS_SHIFT)
98 #define SCU_VIIT_STATUS_RNI_VALID (0x04 << SCU_VIIT_ENTRY_STATUS_SHIFT)
106 #define SCU_VIIT_IPPT_SMP_TARGET (0x10 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
131 * This must be 0
139 #define SCU_IIT_ENTRY_ID_MASK (0xC0000000)
142 #define SCU_IIT_ENTRY_STATUS_UPDATE_MASK (0x20000000)
145 #define SCU_IIT_ENTRY_LPI_MASK (0x00000F00)
148 #define SCU_IIT_ENTRY_STATUS_MASK (0x000000FF)
149 #define SCU_IIT_ENTRY_STATUS_SHIFT (0)
152 #define SCU_IIT_ENTRY_REMOTE_TAG_MASK (0x0000FFFF)
153 #define SCU_IIT_ENTRY_REMOTE_TAG_SHIFT (0)
155 #define SCU_IIT_ENTRY_REMOTE_RNC_MASK (0x0FFF0000)
158 #define SCU_IIT_ENTRY_ID_INVALID (0 << SCU_IIT_ENTRY_ID_SHIFT)
198 #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_SHIFT (0)
199 #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_MASK (0x00000FFF)
201 #define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_MASK (0x0000F000)
203 #define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_MASK (0x00030000)
205 #define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_MASK (0x00FC0000)
206 #define SMU_POST_CONTEXT_PORT_RESERVED_MASK (0xFF000000)
213 #define SMU_INTERRUPT_STATUS_COMPLETION_MASK (0x80000000)
215 #define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_MASK (0x00000002)
216 #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_SHIFT (0)
217 #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_MASK (0x00000001)
218 #define SMU_INTERRUPT_STATUS_RESERVED_MASK (0x7FFFFFFC)
229 #define SMU_INTERRUPT_MASK_COMPLETION_MASK (0x80000000)
231 #define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_MASK (0x00000002)
232 #define SMU_INTERRUPT_MASK_QUEUE_ERROR_SHIFT (0)
233 #define SMU_INTERRUPT_MASK_QUEUE_ERROR_MASK (0x00000001)
234 #define SMU_INTERRUPT_MASK_RESERVED_MASK (0x7FFFFFFC)
244 #define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_SHIFT (0)
245 #define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_MASK (0x0000001F)
247 #define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_MASK (0x0000FF00)
248 #define SMU_INTERRUPT_COALESCING_CONTROL_RESERVED_MASK (0xFFFF00E0)
254 #define SMU_TASK_CONTEXT_RANGE_START_SHIFT (0)
255 #define SMU_TASK_CONTEXT_RANGE_START_MASK (0x00000FFF)
257 #define SMU_TASK_CONTEXT_RANGE_ENDING_MASK (0x0FFF0000)
259 #define SMU_TASK_CONTEXT_RANGE_ENABLE_MASK (0x80000000)
260 #define SMU_TASK_CONTEXT_RANGE_RESERVED_MASK (0x7000F000)
270 #define SMU_COMPLETION_QUEUE_PUT_POINTER_SHIFT (0)
271 #define SMU_COMPLETION_QUEUE_PUT_POINTER_MASK (0x00003FFF)
273 #define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_MASK (0x00008000)
275 #define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_MASK (0x03FF0000)
277 #define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_MASK (0x04000000)
278 #define SMU_COMPLETION_QUEUE_PUT_RESERVED_MASK (0xF8004000)
288 #define SMU_COMPLETION_QUEUE_GET_POINTER_SHIFT (0)
289 #define SMU_COMPLETION_QUEUE_GET_POINTER_MASK (0x00003FFF)
291 #define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_MASK (0x00008000)
293 #define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK (0x03FF0000)
295 #define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_MASK (0x04000000)
297 #define SMU_COMPLETION_QUEUE_GET_ENABLE_MASK (0x40000000)
299 #define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_MASK (0x80000000)
300 #define SMU_COMPLETION_QUEUE_GET_RESERVED_MASK (0x38004000)
319 #define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_SHIFT (0)
320 #define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_MASK (0x00003FFF)
322 #define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_MASK (0x03FF0000)
323 #define SMU_COMPLETION_QUEUE_CONTROL_RESERVED_MASK (0xFC00C000)
336 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT (0)
337 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK (0x00000FFF)
339 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK (0x00007000)
341 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK (0x07FF8000)
343 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK (0x08000000)
344 #define SMU_DEVICE_CONTEXT_CAPACITY_RESERVED_MASK (0xF0000000)
374 #define SMU_CLOCK_GATING_CONTROL_IDLE_ENABLE_SHIFT (0)
375 #define SMU_CLOCK_GATING_CONTROL_IDLE_ENABLE_MASK (0x00000001)
377 #define SMU_CLOCK_GATING_CONTROL_XCLK_ENABLE_MASK (0x00000002)
379 #define SMU_CLOCK_GATING_CONTROL_TXCLK_ENABLE_MASK (0x00000004)
381 #define SMU_CLOCK_GATING_CONTROL_REGCLK_ENABLE_MASK (0x00000008)
383 #define SMU_CLOCK_GATING_CONTROL_IDLE_TIMEOUT_MASK (0x000F0000)
385 #define SMU_CLOCK_GATING_CONTROL_FORCE_IDLE_MASK (0x80000000)
386 #define SMU_CLOCK_GATING_CONTROL_RESERVED_MASK (0x7FF0FFF0)
396 #define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_SHIFT (0)
397 #define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_MASK (0x00000001)
399 #define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_MASK (0x00000002)
401 #define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_MASK (0x00010000)
403 #define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_MASK (0x00020000)
404 #define SMU_CONTROL_STATUS_RESERVED_MASK (0xFFFCFFFC)
423 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_SHIFT (0)
424 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_MASK (0x00000001)
426 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_MASK (0x00000002)
428 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_MASK (0x00000004)
430 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_MASK (0x00000008)
432 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_MASK (0x00000100)
434 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_MASK (0x00000200)
436 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_MASK (0x00000400)
438 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_MASK (0x00000800)
445 SMU_RESET_PROTOCOL_ENGINE(peg, 0) \
453 SMU_RESET_PEG_PROTOCOL_ENGINES(0) \
458 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_MASK (0x00010000)
460 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_MASK (0x00020000)
462 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_MASK (0x00040000)
464 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_MASK (0x00080000)
470 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_MASK (0x00100000)
472 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_MASK (0x00200000)
474 #define SMU_SOFTRESET_CONTROL_RESET_SCU_MASK (0x00400000)
482 | SMU_RESET_WIDE_PORT_QUEUE(peg, 0) \
489 SMU_RESET_PROTOCOL_ENGINE_GROUP(0) \
493 #define SMU_RESET_SCU() (0xFFFFFFFF)
498 #define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_SHIFT (0)
499 #define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_MASK (0x00000FFF)
501 #define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_MASK (0x0FFF0000)
503 #define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_MASK (0x80000000)
504 #define SMU_TASK_CONTEXT_ASSIGNMENT_RESERVED_MASK (0x7000F000)
513 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_SHIFT (0)
514 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_MASK (0x00000FFF)
515 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_RESERVED_MASK (0xFFFFF000)
524 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_SHIFT (0)
525 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_MASK (0x00000FFF)
527 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_MASK (0x00001000)
528 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_RESERVED_MASK (0xFFFFE000)
540 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_SHIFT (0)
541 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_MASK (0x00000FFF)
545 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_MASK (0x80000000)
546 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_RESERVED_MASK (0x7FFFE000)
570 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SHIFT (0)
571 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_MASK (0x0000FFFF)
573 #define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK (0x00010000)
575 #define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_MASK (0x00020000)
577 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_MASK (0x00040000)
579 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_MASK (0x00080000)
581 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_MASK (0x00100000)
583 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_MASK (0x00200000)
585 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_MASK (0x00400000)
586 #define SCU_PDMA_CONFIGURATION_RESERVED_MASK (0xFF800000)
599 #define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK (0x00000100)
608 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_SHIFT (0)
609 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_MASK (0x000000FF)
611 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_MASK (0x0000FF00)
613 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_MASK (0x00FF0000)
615 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_MASK (0xFF000000)
616 #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_REQUIRED_MASK (0x00000000)
617 #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_DEFAULT_MASK (0x7D00676F)
618 #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_RESERVED_MASK (0x00FF0000)
625 #define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_MASK (0x00000004)
627 #define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_MASK (0x00000010)
629 #define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_MASK (0x00000020)
630 #define SCU_LINK_STATUS_RESERVED_MASK (0xFFFFFFCD)
642 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_SHIFT (0)
643 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_MASK (0x00007FFF)
645 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_MASK (0x00008000)
659 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_MASK (0x00000002)
661 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_MASK (0x00000004)
663 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_MASK (0x00000008)
665 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_MASK (0x00000100)
667 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_MASK (0x00000200)
669 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_MASK (0x00000400)
671 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_MASK (0x00000800)
673 #define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_MASK (0x000F0000)
675 #define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_MASK (0x0F000000)
677 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_MASK (0x70000000)
678 #define SCU_SAS_TRANSMIT_IDENTIFICATION_RESERVED_MASK (0x80F0F1F1)
688 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_MASK (0x00010000)
690 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_MASK (0x00020000)
692 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_MASK (0x00040000)
694 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_MASK (0xFF000000)
695 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_RESERVED_MASK (0x00F800FF)
705 #define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_MASK (0x00000010)
707 #define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_MASK (0x00000040)
709 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_MASK (0x00000080)
711 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_MASK (0x00000100)
713 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_MASK (0x00000200)
715 #define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_MASK (0x00000800)
717 #define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_MASK (0x00001000)
719 #define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_MASK (0x00002000)
721 #define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_MASK (0x00004000)
723 #define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_MASK (0x00008000)
725 #define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_MASK (0x00800000)
727 #define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_MASK (0x08000000)
729 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_MASK (0x10000000)
731 #define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_MASK (0x20000000)
733 #define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_MASK (0x40000000)
735 #define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_MASK (0x80000000)
736 #define SCU_SAS_PHY_CONFIGURATION_REQUIRED_MASK (0x0100000F)
737 #define SCU_SAS_PHY_CONFIGURATION_DEFAULT_MASK (0x4180100F)
738 #define SCU_SAS_PHY_CONFIGURATION_RESERVED_MASK (0x00000000)
743 #define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_SHIFT (0)
744 #define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_MASK (0x000007FF)
746 #define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_CONNECTED_MASK (0x00ff0000)
751 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_SHIFT (0)
752 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_MASK (0x0003FFFF)
754 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_MASK (0x80000000)
755 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_RESERVED_MASK (0x7FFC0000)
765 #define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_MASK (0x00000002)
767 #define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_MASK (0x000000F0)
769 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_MASK (0x00000100)
771 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_MASK (0x00000201)
773 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_MASK (0x00000401)
775 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_MASK (0x00000801)
777 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_MASK (0x00001001)
779 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_MASK (0x00002001)
781 #define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_MASK (0x80000000)
782 #define SCU_LINK_LAYER_PHY_CAPABILITIES_DEFAULT_MASK (0x00003F01)
783 #define SCU_LINK_LAYER_PHY_CAPABILITIES_REQUIRED_MASK (0x00000001)
784 #define SCU_LINK_LAYER_PHY_CAPABILITIES_RESERVED_MASK (0x7FFFC00D)
793 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_SHIFT (0)
794 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_MASK (0x0000…
796 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_MASK (0x8000…
797 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_RESERVED_MASK (0x7FFF…
806 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_MASK (0x0000…
808 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_MASK (0x0000…
810 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_MASK (0x0000…
812 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_MASK (0x0000…
814 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_MASK (0x0003…
816 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_MASK (0x0008…
818 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_MASK (0x0030…
820 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_MASK (0x0080…
822 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_MASK (0x0300…
824 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_MASK (0x0800…
826 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_MASK (0x3000…
828 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_MASK (0x8000…
829 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_RESERVED_MASK (0x4444…
842 #define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_SHIFT (0)
843 #define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_MASK (0x0000FFFF)
845 #define SCU_PTSG_CONTROL_TASK_TIMEOUT_MASK (0x00FF0000)
847 #define SCU_PTSG_CONTROL_PTSG_ENABLE_MASK (0x01000000)
849 #define SCU_PTSG_CONTROL_ETM_ENABLE_MASK (0x02000000)
850 #define SCU_PTSG_CONTROL_DEFAULT_MASK (0x00020002)
851 #define SCU_PTSG_CONTROL_REQUIRED_MASK (0x00000000)
852 #define SCU_PTSG_CONTROL_RESERVED_MASK (0xFC000000)
862 #define SCU_PTSG_REAL_TIME_CLOCK_SHIFT (0)
863 #define SCU_PTSG_REAL_TIME_CLOCK_MASK (0x0000FFFF)
864 #define SCU_PTSG_REAL_TIME_CLOCK_RESERVED_MASK (0xFFFF0000)
870 #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_SHIFT (0)
871 #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_MASK (0x00FFFFFF)
872 #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_RESERVED_MASK (0xFF000000)
878 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_SHIFT (0)
879 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_MASK (0x00000001)
881 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_MASK (0x00000002)
882 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_RESERVED_MASK (0xFFFFFFFC)
888 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_SHIFT (0)
889 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_MASK (0x00000001)
891 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_MASK (0x00000002)
893 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_MASK (0x00000004)
894 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_RESERVED_MASK (0xFFFFFFF8)
912 * The TCA is only accessable from FN#0 (Physical Function) and each
913 * is programmed by (BAR0 + SCU_SMU_TCA_OFFSET + (FN# * 0x04)) or
914 * TCA0 for FN#0 is at BAR0 + 0x0400
915 * TCA1 for FN#1 is at BAR0 + 0x0404
919 #define SCU_SMU_PCP_OFFSET 0x0000
920 #define SCU_SMU_AMR_OFFSET 0x0004
921 #define SCU_SMU_ISR_OFFSET 0x0010
922 #define SCU_SMU_IMR_OFFSET 0x0014
923 #define SCU_SMU_ICC_OFFSET 0x0018
924 #define SCU_SMU_HTTLBAR_OFFSET 0x0020
925 #define SCU_SMU_HTTUBAR_OFFSET 0x0024
926 #define SCU_SMU_TCR_OFFSET 0x0028
927 #define SCU_SMU_CQLBAR_OFFSET 0x0030
928 #define SCU_SMU_CQUBAR_OFFSET 0x0034
929 #define SCU_SMU_CQPR_OFFSET 0x0040
930 #define SCU_SMU_CQGR_OFFSET 0x0044
931 #define SCU_SMU_CQC_OFFSET 0x0048
932 /* Accessable to FN#0 only */
933 #define SCU_SMU_RNCLBAR_OFFSET 0x0080
934 #define SCU_SMU_RNCUBAR_OFFSET 0x0084
935 #define SCU_SMU_DCC_OFFSET 0x0090
936 #define SCU_SMU_DFC_OFFSET 0x0094
937 #define SCU_SMU_SMUCSR_OFFSET 0x0098
938 #define SCU_SMU_SCUSRCR_OFFSET 0x009C
939 #define SCU_SMU_SMAW_OFFSET 0x00A0
940 #define SCU_SMU_SMDW_OFFSET 0x00A4
941 /* Accessable to FN#0 only */
942 #define SCU_SMU_TCA_OFFSET 0x0400
944 #define SCU_SMU_MT_MLAR0_OFFSET 0x2000
945 #define SCU_SMU_MT_MUAR0_OFFSET 0x2004
946 #define SCU_SMU_MT_MDR0_OFFSET 0x2008
947 #define SCU_SMU_MT_VCR0_OFFSET 0x200C
948 #define SCU_SMU_MT_MLAR1_OFFSET 0x2010
949 #define SCU_SMU_MT_MUAR1_OFFSET 0x2014
950 #define SCU_SMU_MT_MDR1_OFFSET 0x2018
951 #define SCU_SMU_MT_VCR1_OFFSET 0x201C
952 #define SCU_SMU_MPBA_OFFSET 0x3000
960 /* 0x0000 PCP */
962 /* 0x0004 AMR */
966 /* 0x0010 ISR */
968 /* 0x0014 IMR */
970 /* 0x0018 ICC */
973 /* 0x0020 HTTLBAR */
975 /* 0x0024 HTTUBAR */
977 /* 0x0028 TCR */
980 /* 0x0030 CQLBAR */
982 /* 0x0034 CQUBAR */
986 /* 0x0040 CQPR */
988 /* 0x0044 CQGR */
990 /* 0x0048 CQC */
997 * Accessable to FN#0 only
998 * 0x0080 RNCLBAR */
1000 /* 0x0084 RNCUBAR */
1004 /* 0x0090 DCC */
1006 /* 0x0094 DFC */
1008 /* 0x0098 SMUCSR */
1010 /* 0x009C SCUSRCR */
1012 /* 0x00A0 SMAW */
1014 /* 0x00A4 SMDW */
1016 /* 0x00A8 CGUCR */
1018 /* 0x00AC CGUPC */
1030 * Accessable to FN#0 only
1031 * 0x0400 TCA */
1040 #define SCU_SDMA_BASE 0x6000
1041 #define SCU_SDMA_PUFATLHAR_OFFSET 0x0000
1042 #define SCU_SDMA_PUFATUHAR_OFFSET 0x0004
1043 #define SCU_SDMA_UFLHBAR_OFFSET 0x0008
1044 #define SCU_SDMA_UFUHBAR_OFFSET 0x000C
1045 #define SCU_SDMA_UFQC_OFFSET 0x0010
1046 #define SCU_SDMA_UFQPP_OFFSET 0x0014
1047 #define SCU_SDMA_UFQGP_OFFSET 0x0018
1048 #define SCU_SDMA_PDMACR_OFFSET 0x001C
1049 #define SCU_SDMA_CDMACR_OFFSET 0x0080
1057 /* 0x0000 PUFATLHAR */
1059 /* 0x0004 PUFATUHAR */
1061 /* 0x0008 UFLHBAR */
1063 /* 0x000C UFUHBAR */
1065 /* 0x0010 UFQC */
1067 /* 0x0014 UFQPP */
1069 /* 0x0018 UFQGP */
1071 /* 0x001C PDMACR */
1073 /* Reserved until offset 0x80 */
1074 u32 reserved_0020_007C[0x18];
1075 /* 0x0080 CDMACR */
1078 u32 reserved_0084_0400[0xDF];
1086 #define SCU_PEG0_OFFSET 0x0000
1087 #define SCU_PEG1_OFFSET 0x8000
1089 #define SCU_TL0_OFFSET 0x0000
1090 #define SCU_TL1_OFFSET 0x0400
1091 #define SCU_TL2_OFFSET 0x0800
1092 #define SCU_TL3_OFFSET 0x0C00
1094 #define SCU_LL_OFFSET 0x0080
1101 #define SCU_TLCR_OFFSET 0x0000
1102 #define SCU_TLADTR_OFFSET 0x0004
1103 #define SCU_TLTTMR_OFFSET 0x0008
1104 #define SCU_TLEECR0_OFFSET 0x000C
1105 #define SCU_STPTLDARNI_OFFSET 0x0010
1108 #define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_SHIFT (0)
1109 #define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_MASK (0x00000001)
1111 #define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_MASK (0x00000002)
1113 #define SCU_TLCR_STP_WRITE_DATA_PREFETCH_MASK (0x00000008)
1115 #define SCU_TLCR_CMD_NAK_STATUS_CODE_MASK (0x00000010)
1116 #define SCU_TLCR_RESERVED_MASK (0xFFFFFFEB)
1128 /* 0x0000 TLCR */
1130 /* 0x0004 TLADTR */
1132 /* 0x0008 TLTTMR */
1134 /* 0x000C reserved */
1136 /* 0x0010 STPTLDARNI */
1138 /* 0x0014 TLFEWPORCTRL */
1140 /* 0x0018 TLFEWPORDATA */
1142 /* 0x001C RXTLSSCSR1 */
1144 /* 0x0020 RXTLSSCSR2 */
1146 /* 0x0024 AWTRDDCR */
1149 u32 reserved_0028_007F[0x16];
1154 #define SCU_SCUVZECRx_OFFSET 0x1080
1157 #define SCU_SAS_SPDTOV_OFFSET 0x0000
1158 #define SCU_SAS_LLSTA_OFFSET 0x0004
1159 #define SCU_SATA_PSELTOV_OFFSET 0x0008
1160 #define SCU_SAS_TIMETOV_OFFSET 0x0010
1161 #define SCU_SAS_LOSTOT_OFFSET 0x0014
1162 #define SCU_SAS_LNKTOV_OFFSET 0x0018
1163 #define SCU_SAS_PHYTOV_OFFSET 0x001C
1164 #define SCU_SAS_AFERCNT_OFFSET 0x0020
1165 #define SCU_SAS_WERCNT_OFFSET 0x0024
1166 #define SCU_SAS_TIID_OFFSET 0x0028
1167 #define SCU_SAS_TIDNH_OFFSET 0x002C
1168 #define SCU_SAS_TIDNL_OFFSET 0x0030
1169 #define SCU_SAS_TISSAH_OFFSET 0x0034
1170 #define SCU_SAS_TISSAL_OFFSET 0x0038
1171 #define SCU_SAS_TIPID_OFFSET 0x003C
1172 #define SCU_SAS_TIRES2_OFFSET 0x0040
1173 #define SCU_SAS_ADRSTA_OFFSET 0x0044
1174 #define SCU_SAS_MAWTTOV_OFFSET 0x0048
1175 #define SCU_SAS_FRPLDFIL_OFFSET 0x0054
1176 #define SCU_SAS_RFCNT_OFFSET 0x0060
1177 #define SCU_SAS_TFCNT_OFFSET 0x0064
1178 #define SCU_SAS_RFDCNT_OFFSET 0x0068
1179 #define SCU_SAS_TFDCNT_OFFSET 0x006C
1180 #define SCU_SAS_LERCNT_OFFSET 0x0070
1181 #define SCU_SAS_RDISERRCNT_OFFSET 0x0074
1182 #define SCU_SAS_CRERCNT_OFFSET 0x0078
1183 #define SCU_STPCTL_OFFSET 0x007C
1184 #define SCU_SAS_PCFG_OFFSET 0x0080
1185 #define SCU_SAS_CLKSM_OFFSET 0x0084
1186 #define SCU_SAS_TXCOMWAKE_OFFSET 0x0088
1187 #define SCU_SAS_TXCOMINIT_OFFSET 0x008C
1188 #define SCU_SAS_TXCOMSAS_OFFSET 0x0090
1189 #define SCU_SAS_COMINIT_OFFSET 0x0094
1190 #define SCU_SAS_COMWAKE_OFFSET 0x0098
1191 #define SCU_SAS_COMSAS_OFFSET 0x009C
1192 #define SCU_SAS_SFERCNT_OFFSET 0x00A0
1193 #define SCU_SAS_CDFERCNT_OFFSET 0x00A4
1194 #define SCU_SAS_DNFERCNT_OFFSET 0x00A8
1195 #define SCU_SAS_PRSTERCNT_OFFSET 0x00AC
1196 #define SCU_SAS_CNTCTL_OFFSET 0x00B0
1197 #define SCU_SAS_SSPTOV_OFFSET 0x00B4
1198 #define SCU_FTCTL_OFFSET 0x00B8
1199 #define SCU_FRCTL_OFFSET 0x00BC
1200 #define SCU_FTWMRK_OFFSET 0x00C0
1201 #define SCU_ENSPINUP_OFFSET 0x00C4
1202 #define SCU_SAS_TRNTOV_OFFSET 0x00C8
1203 #define SCU_SAS_PHYCAP_OFFSET 0x00CC
1204 #define SCU_SAS_PHYCTL_OFFSET 0x00D0
1205 #define SCU_SAS_LLCTL_OFFSET 0x00D8
1206 #define SCU_AFE_XCVRCR_OFFSET 0x00DC
1207 #define SCU_AFE_LUTCR_OFFSET 0x00E0
1209 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_SHIFT (0UL)
1210 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_MASK (0x000000FFUL)
1212 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_HOT_PLUG_MASK (0x0000FF00UL)
1214 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_COMSAS_DETECTION_MASK (0x00FF0000UL)
1216 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_RATE_CHANGE_MASK (0xFF000000UL)
1221 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_SHIFT (0)
1222 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_MASK (0x00000003)
1223 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1 (0)
1227 #define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_MASK (0x000003FC)
1229 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_MASK (0x00010000)
1231 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_MASK (0x00020000)
1233 #define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_MASK (0xFF000000)
1234 #define SCU_SAS_LINK_LAYER_CONTROL_RESERVED (0x00FCFC00)
1242 #define SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT (0xF0)
1243 #define SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_EXTENDED (0x1FF)
1244 #define SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_SHIFT (0)
1245 #define SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_MASK (0x3FF)
1251 /* #define SCU_FRXHECR_DCNT_OFFSET 0x00B0 */
1252 #define SCU_PSZGCR_OFFSET 0x00E4
1253 #define SCU_SAS_RECPHYCAP_OFFSET 0x00E8
1254 /* #define SCU_TX_LUTSEL_OFFSET 0x00B8 */
1256 #define SCU_SAS_PTxC_OFFSET 0x00D4 /* Same offset as SAS_TCTSTM */
1264 /* 0x0000 SAS_SPDTOV */
1266 /* 0x0004 SAS_LLSTA */
1268 /* 0x0008 SATA_PSELTOV */
1271 /* 0x0010 SAS_TIMETOV */
1273 /* 0x0014 SAS_RCDTOV */
1275 /* 0x0018 SAS_LNKTOV */
1277 /* 0x001C SAS_PHYTOV */
1279 /* 0x0020 SAS_AFERCNT */
1281 /* 0x0024 SAS_WERCNT */
1283 /* 0x0028 SAS_TIID */
1285 /* 0x002C SAS_TIDNH */
1287 /* 0x0030 SAS_TIDNL */
1289 /* 0x0034 SAS_TISSAH */
1291 /* 0x0038 SAS_TISSAL */
1293 /* 0x003C SAS_TIPID */
1295 /* 0x0040 SAS_TIRES2 */
1297 /* 0x0044 SAS_ADRSTA */
1299 /* 0x0048 SAS_MAWTTOV */
1301 /* 0x004C SAS_PTxC */
1303 /* 0x0050 SAS_RORES */
1305 /* 0x0054 SAS_FRPLDFIL */
1307 /* 0x0058 SAS_LLHANG_TOT */
1310 /* 0x0060 SAS_RFCNT */
1312 /* 0x0064 SAS_TFCNT */
1314 /* 0x0068 SAS_RFDCNT */
1316 /* 0x006C SAS_TFDCNT */
1318 /* 0x0070 SAS_LERCNT */
1320 /* 0x0074 SAS_RDISERRCNT */
1322 /* 0x0078 SAS_CRERCNT */
1324 /* 0x007C STPCTL */
1326 /* 0x0080 SAS_PCFG */
1328 /* 0x0084 SAS_CLKSM */
1330 /* 0x0088 SAS_TXCOMWAKE */
1332 /* 0x008C SAS_TXCOMINIT */
1334 /* 0x0090 SAS_TXCOMSAS */
1336 /* 0x0094 SAS_COMINIT */
1338 /* 0x0098 SAS_COMWAKE */
1340 /* 0x009C SAS_COMSAS */
1342 /* 0x00A0 SAS_SFERCNT */
1344 /* 0x00A4 SAS_CDFERCNT */
1346 /* 0x00A8 SAS_DNFERCNT */
1348 /* 0x00AC SAS_PRSTERCNT */
1350 /* 0x00B0 SAS_CNTCTL */
1352 /* 0x00B4 SAS_SSPTOV */
1354 /* 0x00B8 FTCTL */
1356 /* 0x00BC FRCTL */
1358 /* 0x00C0 FTWMRK */
1360 /* 0x00C4 ENSPINUP */
1362 /* 0x00C8 SAS_TRNTOV */
1364 /* 0x00CC SAS_PHYCAP */
1366 /* 0x00D0 SAS_PHYCTL */
1369 /* 0x00D8 LLCTL */
1371 /* 0x00DC AFE_XCVRCR */
1373 /* 0x00E0 AFE_LUTCR */
1375 /* 0x00E4 PSZGCR */
1377 /* 0x00E8 SAS_RECPHYCAP */
1380 /* 0x00F0 SNAFERXRSTCTL */
1382 /* 0x00F4 SAS_SSIPMCTL */
1384 /* 0x00F8 SAS_PSPREQ_PRIM */
1386 /* 0x00FC SAS_PSSREQ_PRIM */
1388 /* 0x0100 SAS_PPSACK_PRIM */
1390 /* 0x0104 SAS_PSNAK_PRIM */
1392 /* 0x0108 SAS_SSIPMTOV */
1395 /* 0x0110 - 0x011C PLAPRDCTRLxREG */
1397 /* 0x0120 PLAPRDSUMREG */
1399 /* 0x0124 PLACONTROLREG */
1402 u32 reserved_0128_037f[0x96];
1407 * 0x00D4 // Same offset as SAS_TCTSTM SAS_PTxC
1414 #define SCU_SGPIO_OFFSET 0x1400
1416 /* #define SCU_SGPIO_OFFSET 0x6000 // later moves to 0x1400 see HSD 652625 */
1417 #define SCU_SGPIO_SGICR_OFFSET 0x0000
1418 #define SCU_SGPIO_SGPBR_OFFSET 0x0004
1419 #define SCU_SGPIO_SGSDLR_OFFSET 0x0008
1420 #define SCU_SGPIO_SGSDUR_OFFSET 0x000C
1421 #define SCU_SGPIO_SGSIDLR_OFFSET 0x0010
1422 #define SCU_SGPIO_SGSIDUR_OFFSET 0x0014
1423 #define SCU_SGPIO_SGVSCR_OFFSET 0x0018
1424 /* Address from 0x0820 to 0x083C */
1425 #define SCU_SGPIO_SGODSR_OFFSET 0x0020
1433 /* 0x0000 SGPIO_SGICR */
1435 /* 0x0004 SGPIO_SGPBR */
1437 /* 0x0008 SGPIO_SGSDLR */
1439 /* 0x000C SGPIO_SGSDUR */
1441 /* 0x0010 SGPIO_SGSIDLR */
1443 /* 0x0014 SGPIO_SGSIDUR */
1445 /* 0x0018 SGPIO_SGVSCR */
1447 /* 0x001C Reserved */
1449 /* 0x0020 SGPIO_SGODSR */
1452 u32 reserved_1444_14ff[0x30];
1459 * * Access additional entries by SCU_VIIT_BASE + index * 0x10
1461 #define SCU_VIIT_BASE 0x1c00
1472 #define SCU_PTSG_BASE 0x1000
1474 #define SCU_PTSG_PTSGCR_OFFSET 0x0000
1475 #define SCU_PTSG_RTCR_OFFSET 0x0004
1476 #define SCU_PTSG_RTCCR_OFFSET 0x0008
1477 #define SCU_PTSG_PTS0CR_OFFSET 0x0010
1478 #define SCU_PTSG_PTS0SR_OFFSET 0x0014
1479 #define SCU_PTSG_PTS1CR_OFFSET 0x0018
1480 #define SCU_PTSG_PTS1SR_OFFSET 0x001C
1481 #define SCU_PTSG_PTS2CR_OFFSET 0x0020
1482 #define SCU_PTSG_PTS2SR_OFFSET 0x0024
1483 #define SCU_PTSG_PTS3CR_OFFSET 0x0028
1484 #define SCU_PTSG_PTS3SR_OFFSET 0x002C
1485 #define SCU_PTSG_PCSPE0CR_OFFSET 0x0030
1486 #define SCU_PTSG_PCSPE1CR_OFFSET 0x0034
1487 #define SCU_PTSG_PCSPE2CR_OFFSET 0x0038
1488 #define SCU_PTSG_PCSPE3CR_OFFSET 0x003C
1489 #define SCU_PTSG_ETMTSCCR_OFFSET 0x0040
1490 #define SCU_PTSG_ETMRNSCCR_OFFSET 0x0044
1510 /* 0x0000 PTSGCR */
1512 /* 0x0004 RTCR */
1514 /* 0x0008 RTCCR */
1516 /* 0x000C */
1519 * 0x0010 PTS0CR
1520 * 0x0014 PTS0SR
1521 * 0x0018 PTS1CR
1522 * 0x001C PTS1SR
1523 * 0x0020 PTS2CR
1524 * 0x0024 PTS2SR
1525 * 0x0028 PTS3CR
1526 * 0x002C PTS3SR */
1529 * 0x0030 PCSPE0CR
1530 * 0x0034 PCSPE1CR
1531 * 0x0038 PCSPE2CR
1532 * 0x003C PCSPE3CR */
1534 /* 0x0040 ETMTSCCR */
1536 /* 0x0044 ETMRNSCCR */
1539 u32 reserved_1048_107f[0x0E];
1543 #define SCU_PTSG_SCUVZECR_OFFSET 0x003C
1549 #define SCU_AFE_MMR_BASE 0xE000
1552 * AFE 0 is at offset 0x0800
1553 * AFE 1 is at offset 0x0900
1554 * AFE 2 is at offset 0x0a00
1555 * AFE 3 is at offset 0x0b00 */
1557 /* 0x0000 AFE_XCVR_CTRL0 */
1559 /* 0x0004 AFE_XCVR_CTRL1 */
1561 /* 0x0008 */
1563 /* 0x000c afe_dfx_rx_control0 */
1565 /* 0x0010 AFE_DFX_RX_CTRL1 */
1567 /* 0x0014 */
1569 /* 0x0018 AFE_DFX_RX_STS0 */
1571 /* 0x001c AFE_DFX_RX_STS1 */
1573 /* 0x0020 */
1575 /* 0x0024 AFE_TX_CTRL */
1577 /* 0x0028 AFE_TX_AMP_CTRL0 */
1579 /* 0x002c AFE_TX_AMP_CTRL1 */
1581 /* 0x0030 AFE_TX_AMP_CTRL2 */
1583 /* 0x0034 AFE_TX_AMP_CTRL3 */
1585 /* 0x0038 afe_tx_ssc_control */
1587 /* 0x003c */
1589 /* 0x0040 AFE_RX_SSC_CTRL0 */
1591 /* 0x0044 AFE_RX_SSC_CTRL1 */
1593 /* 0x0048 AFE_RX_SSC_CTRL2 */
1595 /* 0x004c AFE_RX_EQ_STS0 */
1597 /* 0x0050 AFE_RX_EQ_STS1 */
1599 /* 0x0054 AFE_RX_CDR_STS */
1601 /* 0x0058 */
1603 /* 0x005c AFE_CHAN_CTRL */
1605 /* 0x0060-0x006c */
1606 u32 reserved_0060_006c[0x04];
1607 /* 0x0070 AFE_XCVR_EC_STS0 */
1609 /* 0x0074 AFE_XCVR_EC_STS1 */
1611 /* 0x0078 AFE_XCVR_EC_STS2 */
1613 /* 0x007c afe_xcvr_ec_status3 */
1615 /* 0x0080 AFE_XCVR_EC_STS4 */
1617 /* 0x0084 AFE_XCVR_EC_STS5 */
1619 /* 0x0088-0x00fc */
1620 u32 reserved_008c_00fc[0x1e];
1630 /* 0Xe000 AFE_BIAS_CTRL */
1633 /* 0x0008 AFE_PLL_CTRL0 */
1635 /* 0x000c AFE_PLL_CTRL1 */
1637 /* 0x0010 AFE_PLL_CTRL2 */
1639 /* 0x0014 AFE_CB_STS */
1641 /* 0x0018-0x007c */
1642 u32 reserved_18_7c[0x1a];
1643 /* 0x0080 AFE_PMSN_MCTRL0 */
1645 /* 0x0084 AFE_PMSN_MCTRL1 */
1647 /* 0x0088 AFE_PMSN_MCTRL2 */
1649 /* 0x008C-0x00fc */
1650 u32 reserved_008c_00fc[0x1D];
1651 /* 0x0100 AFE_DFX_MST_CTRL0 */
1653 /* 0x0104 AFE_DFX_MST_CTRL1 */
1655 /* 0x0108 AFE_DFX_DCL_CTRL */
1657 /* 0x010c AFE_DFX_DMON_CTRL */
1659 /* 0x0110 AFE_DFX_AMONP_CTRL */
1661 /* 0x0114 AFE_DFX_AMONN_CTRL */
1663 /* 0x0118 AFE_DFX_NTL_STS */
1665 /* 0x011c AFE_DFX_FIFO_STS0 */
1667 /* 0x0120 AFE_DFX_FIFO_STS1 */
1669 /* 0x0124 AFE_DFX_MPAT_CTRL */
1671 /* 0x0128 AFE_DFX_P0_CTRL */
1673 /* 0x012c-0x01a8 AFE_DFX_P0_DRx */
1675 /* 0x01ac */
1677 /* 0x01b0-0x020c AFE_DFX_P0_IRx */
1679 /* 0x0210 */
1681 /* 0x0214 AFE_DFX_P1_CTRL */
1683 /* 0x0218-0x245 AFE_DFX_P1_DRx */
1685 /* 0x0258-0x029c */
1686 u32 reserved_0258_029c[0x12];
1687 /* 0x02a0-0x02bc AFE_DFX_P1_IRx */
1689 /* 0x02c0-0x2fc */
1690 u32 reserved_02c0_02fc[0x10];
1691 /* 0x0300 AFE_DFX_TX_PMSN_CTRL */
1693 /* 0x0304 AFE_DFX_RX_PMSN_CTRL */
1696 /* 0x030c AFE_DFX_NOA_CTRL0 */
1698 /* 0x0310 AFE_DFX_NOA_CTRL1 */
1700 /* 0x0314 AFE_DFX_NOA_CTRL2 */
1702 /* 0x0318 AFE_DFX_NOA_CTRL3 */
1704 /* 0x031c AFE_DFX_NOA_CTRL4 */
1706 /* 0x0320 AFE_DFX_NOA_CTRL5 */
1708 /* 0x0324 AFE_DFX_NOA_CTRL6 */
1710 /* 0x0328 AFE_DFX_NOA_CTRL7 */
1712 /* 0x032c-0x07fc */
1713 u32 reserved_032c_07fc[0x135];
1715 /* 0x0800-0x0bfc */
1718 /* 0x0c00-0x0ffc */
1719 u32 reserved_0c00_0ffc[0x0100];
1723 u32 table[0xE0];
1823 u32 reserved_01500_1BFF[0x1C0];
1837 /* 0x0000 - PEG 0 */
1840 /* 0x6000 - SDMA and Miscellaneous */
1844 u32 reserved_6800_69FF[0x80];
1848 u32 reserved_6d00_7fff[0x4c0];
1850 /* 0x8000 - PEG 1 */
1853 /* 0xE000 - AFE Registers */
1856 /* 0xF000 - reserved */
1857 u32 reserved_f000_211fff[0x80c00];
1859 /* 0x212000 - scratch RAM */