Lines Matching +full:0 +full:x3220
48 u32 req = 0; in iop_wait_ready_itl()
51 for (i = 0; i < millisec; i++) { in iop_wait_ready_itl()
61 return 0; in iop_wait_ready_itl()
118 int ret = 0; in iop_intr_itl()
120 if (plx && readl(plx + 0x11C5C) & 0xf) in iop_intr_itl()
121 writel(1, plx + 0x11C60); in iop_intr_itl()
154 outbound_tail = 0; in mv_outbound_read()
158 return 0; in mv_outbound_read()
167 head = 0; in mv_inbound_write()
177 u32 req_type = (tag >> 5) & 0x7; in hptiop_request_callback_mv()
182 BUG_ON((tag & MVIOP_MU_QUEUE_REQUEST_RETURN_CONTEXT) == 0); in hptiop_request_callback_mv()
206 int ret = 0; in iop_intr_mv()
232 u32 req_type = _tag & 0xf; in hptiop_request_callback_mvfrey()
242 req = hba->reqs[(_tag >> 4) & 0xff].req_virt; in hptiop_request_callback_mvfrey()
245 hptiop_finish_scsi_req(hba, (_tag >> 4) & 0xff, req); in hptiop_request_callback_mvfrey()
256 int ret = 0; in iop_intr_mvfrey()
259 writel(0, &(hba->u.mvfrey.mu->pcie_f0_int_enable)); in iop_intr_mvfrey()
276 cptr = *hba->u.mvfrey.outlist_cptr & 0xff; in iop_intr_mvfrey()
281 cur_rptr = 0; in iop_intr_mvfrey()
289 } while (cptr != (*hba->u.mvfrey.outlist_cptr & 0xff)); in iop_intr_mvfrey()
293 writel(0x1010, &(hba->u.mvfrey.mu->pcie_f0_int_enable)); in iop_intr_mvfrey()
305 writel(0, &req->context); in iop_send_sync_request_itl()
310 for (i = 0; i < millisec; i++) { in iop_send_sync_request_itl()
313 return 0; in iop_send_sync_request_itl()
326 hba->msg_done = 0; in iop_send_sync_request_mv()
331 for (i = 0; i < millisec; i++) { in iop_send_sync_request_mv()
334 return 0; in iop_send_sync_request_mv()
347 hba->msg_done = 0; in iop_send_sync_request_mvfrey()
351 for (i = 0; i < millisec; i++) { in iop_send_sync_request_mvfrey()
357 return hba->msg_done ? 0 : -1; in iop_send_sync_request_mvfrey()
383 hba->msg_done = 0; in iop_send_sync_msg()
387 for (i = 0; i < millisec; i++) { in iop_send_sync_msg()
397 return hba->msg_done? 0 : -1; in iop_send_sync_msg()
413 writel(0, &req->header.flags); in iop_get_config_itl()
425 return 0; in iop_get_config_itl()
439 req->header.context_hi32 = 0; in iop_get_config_mv()
441 if (iop_send_sync_request_mv(hba, 0, 20000)) { in iop_get_config_mv()
447 return 0; in iop_get_config_mv()
469 return 0; in iop_get_config_mvfrey()
490 writel(0, &req->header.flags); in iop_set_config_itl()
501 return 0; in iop_set_config_itl()
516 req->header.context_hi32 = 0; in iop_set_config_mv()
518 if (iop_send_sync_request_mv(hba, 0, 20000)) { in iop_set_config_mv()
523 return 0; in iop_set_config_mv()
539 req->header.context_hi32 = 0; in iop_set_config_mvfrey()
541 if (iop_send_sync_request_mvfrey(hba, 0, 20000)) { in iop_set_config_mvfrey()
546 return 0; in iop_set_config_mvfrey()
564 writel(0x1, &(hba->u.mvfrey.mu->isr_enable)); in hptiop_enable_intr_mvfrey()
565 writel(0x1010, &(hba->u.mvfrey.mu->pcie_f0_int_enable)); in hptiop_enable_intr_mvfrey()
582 return 0; in hptiop_initialize_iop()
614 hba->u.itl.iop = hptiop_map_pci_bar(hba, 0); in hptiop_map_pci_bar_itl()
617 if ((pcidev->device & 0xff00) == 0x4400) { in hptiop_map_pci_bar_itl()
625 return 0; in hptiop_map_pci_bar_itl()
637 hba->u.mv.regs = hptiop_map_pci_bar(hba, 0); in hptiop_map_pci_bar_mv()
647 return 0; in hptiop_map_pci_bar_mv()
652 hba->u.mvfrey.config = hptiop_map_pci_bar(hba, 0); in hptiop_map_pci_bar_mvfrey()
662 return 0; in hptiop_map_pci_bar_mvfrey()
679 dprintk("iop message 0x%x\n", msg); in hptiop_message_callback()
689 atomic_set(&hba->resetting, 0); in hptiop_message_callback()
722 "result=%d, context=0x%x tag=%d\n", in hptiop_finish_scsi_req()
803 "result=%d, context=0x%x tag=%d\n", in hptiop_iop_request_callback_itl()
854 BUG_ON(nseg < 0); in hptiop_buildsgl()
856 return 0; in hptiop_buildsgl()
868 cpu_to_le32(1) : 0; in hptiop_buildsgl()
880 reqhdr->context_hi32 = 0; in hptiop_post_req_itl()
908 reqhdr->context_hi32 = 0; in hptiop_post_req_mv()
912 size_bit = 0; in hptiop_post_req_mv()
932 ((_req->req_shifted_phy >> 11) & 0xffff0000)); in hptiop_post_req_mvfrey()
936 0xffffffff); in hptiop_post_req_mvfrey()
939 index = hba->u.mvfrey.inlist_wptr & 0x3fff; in hptiop_post_req_mvfrey()
942 index = 0; in hptiop_post_req_mvfrey()
943 hba->u.mvfrey.inlist_wptr &= ~0x3fff; in hptiop_post_req_mvfrey()
957 return 0; in hptiop_reset_comm_itl()
962 return 0; in hptiop_reset_comm_mv()
975 writel(cpu_to_le32(hba->u.mvfrey.inlist_phy & 0xffffffff), in hptiop_reset_comm_mvfrey()
980 writel(cpu_to_le32(hba->u.mvfrey.outlist_phy & 0xffffffff), in hptiop_reset_comm_mvfrey()
985 writel(cpu_to_le32(hba->u.mvfrey.outlist_cptr_phy & 0xffffffff), in hptiop_reset_comm_mvfrey()
993 return 0; in hptiop_reset_comm_mvfrey()
1001 int sg_count = 0; in hptiop_queuecommand_lck()
1017 cpu_to_be32(((u32 *)scp->cmnd)[0]), in hptiop_queuecommand_lck()
1023 scp->result = 0; in hptiop_queuecommand_lck()
1038 HPT_SCP(scp)->mapped = 0; in hptiop_queuecommand_lck()
1051 return 0; in hptiop_queuecommand_lck()
1056 return 0; in hptiop_queuecommand_lck()
1068 if (atomic_xchg(&hba->resetting, 1) == 0) { in hptiop_reset_hba()
1074 atomic_read(&hba->resetting) == 0, 60 * HZ); in hptiop_reset_hba()
1088 return 0; in hptiop_reset_hba()
1125 (hba->firmware_version >> 16) & 0xff, in hptiop_show_fw_version()
1126 (hba->firmware_version >> 8) & 0xff, in hptiop_show_fw_version()
1127 hba->firmware_version & 0xff); in hptiop_show_fw_version()
1159 return 0; in hptiop_sdev_configure()
1168 .emulated = 0,
1179 return 0; in hptiop_internal_memalloc_itl()
1185 0x800, &hba->u.mv.internal_req_phy, GFP_KERNEL); in hptiop_internal_memalloc_mv()
1187 return 0; in hptiop_internal_memalloc_mv()
1198 BUG_ON(hba->max_request_size == 0); in hptiop_internal_memalloc_mvfrey()
1200 if (list_count == 0) { in hptiop_internal_memalloc_mvfrey()
1208 hba->u.mvfrey.internal_mem_size = 0x800 + in hptiop_internal_memalloc_mvfrey()
1223 p += 0x800; in hptiop_internal_memalloc_mvfrey()
1224 phy += 0x800; in hptiop_internal_memalloc_mvfrey()
1241 return 0; in hptiop_internal_memalloc_mvfrey()
1246 return 0; in hptiop_internal_memfree_itl()
1252 dma_free_coherent(&hba->pcidev->dev, 0x800, in hptiop_internal_memfree_mv()
1254 return 0; in hptiop_internal_memfree_mv()
1267 return 0; in hptiop_internal_memfree_mvfrey()
1321 memset(hba, 0, sizeof(struct hptiop_hba)); in hptiop_probe()
1326 hba->initialized = 0; in hptiop_probe()
1327 hba->iopintf_v2 = 0; in hptiop_probe()
1329 atomic_set(&hba->resetting, 0); in hptiop_probe()
1330 atomic_set(&hba->reset_count, 0); in hptiop_probe()
1336 host->max_channel = 0; in hptiop_probe()
1337 host->io_port = 0; in hptiop_probe()
1338 host->n_io_port = 0; in hptiop_probe()
1386 if (hba->firmware_version > 0x01020000 || in hptiop_probe()
1387 hba->interface_version > 0x01020000) in hptiop_probe()
1399 if ((req_size & 0x1f) != 0) in hptiop_probe()
1400 req_size = (req_size + 0x1f) & ~0x1f; in hptiop_probe()
1402 memset(&set_config, 0, sizeof(struct hpt_iop_request_set_config)); in hptiop_probe()
1429 for (i = 0; i < hba->max_requests; i++) { in hptiop_probe()
1431 hba->req_size + 0x20, in hptiop_probe()
1443 if ((start_phy & 0x1f) != 0) { in hptiop_probe()
1444 offset = ((start_phy + 0x1f) & ~0x1f) - start_phy; in hptiop_probe()
1469 return 0; in hptiop_probe()
1472 for (i = 0; i < hba->max_requests; i++) { in hptiop_probe()
1475 hba->req_size + 0x20, in hptiop_probe()
1498 dprintk("scsi%d: hptiop_probe fail\n", host ? host->host_no : 0); in hptiop_probe()
1531 writel(0, &hba->u.mv.regs->outbound_intmask); in hptiop_disable_intr_mv()
1537 writel(0, &(hba->u.mvfrey.mu->f0_doorbell_enable)); in hptiop_disable_intr_mvfrey()
1539 writel(0, &(hba->u.mvfrey.mu->isr_enable)); in hptiop_disable_intr_mvfrey()
1541 writel(0, &(hba->u.mvfrey.mu->pcie_f0_int_enable)); in hptiop_disable_intr_mvfrey()
1559 for (i = 0; i < hba->max_requests; i++) { in hptiop_remove()
1562 hba->req_size + 0x20, in hptiop_remove()
1596 .host_phy_flag = cpu_to_le64(0),
1615 .host_phy_flag = cpu_to_le64(0),
1638 { PCI_VDEVICE(TTI, 0x3220), (kernel_ulong_t)&hptiop_itl_ops },
1639 { PCI_VDEVICE(TTI, 0x3320), (kernel_ulong_t)&hptiop_itl_ops },
1640 { PCI_VDEVICE(TTI, 0x3410), (kernel_ulong_t)&hptiop_itl_ops },
1641 { PCI_VDEVICE(TTI, 0x3510), (kernel_ulong_t)&hptiop_itl_ops },
1642 { PCI_VDEVICE(TTI, 0x3511), (kernel_ulong_t)&hptiop_itl_ops },
1643 { PCI_VDEVICE(TTI, 0x3520), (kernel_ulong_t)&hptiop_itl_ops },
1644 { PCI_VDEVICE(TTI, 0x3521), (kernel_ulong_t)&hptiop_itl_ops },
1645 { PCI_VDEVICE(TTI, 0x3522), (kernel_ulong_t)&hptiop_itl_ops },
1646 { PCI_VDEVICE(TTI, 0x3530), (kernel_ulong_t)&hptiop_itl_ops },
1647 { PCI_VDEVICE(TTI, 0x3540), (kernel_ulong_t)&hptiop_itl_ops },
1648 { PCI_VDEVICE(TTI, 0x3560), (kernel_ulong_t)&hptiop_itl_ops },
1649 { PCI_VDEVICE(TTI, 0x4210), (kernel_ulong_t)&hptiop_itl_ops },
1650 { PCI_VDEVICE(TTI, 0x4211), (kernel_ulong_t)&hptiop_itl_ops },
1651 { PCI_VDEVICE(TTI, 0x4310), (kernel_ulong_t)&hptiop_itl_ops },
1652 { PCI_VDEVICE(TTI, 0x4311), (kernel_ulong_t)&hptiop_itl_ops },
1653 { PCI_VDEVICE(TTI, 0x4320), (kernel_ulong_t)&hptiop_itl_ops },
1654 { PCI_VDEVICE(TTI, 0x4321), (kernel_ulong_t)&hptiop_itl_ops },
1655 { PCI_VDEVICE(TTI, 0x4322), (kernel_ulong_t)&hptiop_itl_ops },
1656 { PCI_VDEVICE(TTI, 0x4400), (kernel_ulong_t)&hptiop_itl_ops },
1657 { PCI_VDEVICE(TTI, 0x3120), (kernel_ulong_t)&hptiop_mv_ops },
1658 { PCI_VDEVICE(TTI, 0x3122), (kernel_ulong_t)&hptiop_mv_ops },
1659 { PCI_VDEVICE(TTI, 0x3020), (kernel_ulong_t)&hptiop_mv_ops },
1660 { PCI_VDEVICE(TTI, 0x4520), (kernel_ulong_t)&hptiop_mvfrey_ops },
1661 { PCI_VDEVICE(TTI, 0x4522), (kernel_ulong_t)&hptiop_mvfrey_ops },
1662 { PCI_VDEVICE(TTI, 0x3610), (kernel_ulong_t)&hptiop_mvfrey_ops },
1663 { PCI_VDEVICE(TTI, 0x3611), (kernel_ulong_t)&hptiop_mvfrey_ops },
1664 { PCI_VDEVICE(TTI, 0x3620), (kernel_ulong_t)&hptiop_mvfrey_ops },
1665 { PCI_VDEVICE(TTI, 0x3622), (kernel_ulong_t)&hptiop_mvfrey_ops },
1666 { PCI_VDEVICE(TTI, 0x3640), (kernel_ulong_t)&hptiop_mvfrey_ops },
1667 { PCI_VDEVICE(TTI, 0x3660), (kernel_ulong_t)&hptiop_mvfrey_ops },
1668 { PCI_VDEVICE(TTI, 0x3680), (kernel_ulong_t)&hptiop_mvfrey_ops },
1669 { PCI_VDEVICE(TTI, 0x3690), (kernel_ulong_t)&hptiop_mvfrey_ops },