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167 * Configure I/O address of 53C400A or DTC436 by writing magic numbers
213 static u8 ncr_53c400a_magic[] = { /* 53C400A & DTC436 */
487 /* wait_for_53c80_access - wait for 53C80 registers to become accessible
490 * The registers within the 53C80 logic block are inaccessible until
491 * bit 7 in the 53C400 control status register gets asserted.
506 "53c80 registers not accessible, device will be reset\n"); in wait_for_53c80_access()
517 * Perform a pseudo DMA mode receive from a 53C400 or equivalent device.
560 /* 53c80 interrupt or transfer timeout. Reset 53c400 logic. */ in generic_NCR5380_precv()
584 * Perform a pseudo DMA mode send to a 53C400 or equivalent device.
639 /* 53c80 interrupt or transfer timeout. Reset 53c400 logic. */ in generic_NCR5380_psend()
672 /* 53C400 datasheet: non-modulo-128-byte transfers should use PIO */ in generic_NCR5380_dma_xfer_len()