Lines Matching +full:data +full:- +full:enable +full:- +full:active
1 /* SPDX-License-Identifier: GPL-2.0 */
16 #define REG_SCSI_DATA 0 /* R/W: SCSI Data (with ACK) */
21 #define BSTAT_CMD BIT(3) /* Command/Data */
32 #define BCTL_CMD BIT(5) /* Command/Data */
34 #define BCTL_BUSEN BIT(7) /* Enable bus drivers */
36 #define ASTAT_IRQ BIT(0) /* Interrupt active */
50 #define REG_FSTAT 3 /* R: Adapter Status 2 (FIFO) - (@) */
55 #define REG_MCTL 3 /* W: SCSI Data Mode Control */
57 #define MCTL_ACTDEASS BIT(4) /* Active deassert of REQ and ACK */
58 #define MCTL_TARGET BIT(5) /* Enable target mode */
59 #define MCTL_FASTSYNC BIT(6) /* Enable Fast Synchronous */
60 #define MCTL_SYNC BIT(7) /* Enable Synchronous */
61 #define REG_INTCOND 4 /* R: Interrupt Condition - (@) */
73 #define ACTL_PAREN BIT(3) /* Enable SCSI Parity */
74 #define ACTL_IRQEN BIT(4) /* Enable interrupts */
77 #define ACTL_FIFOEN BIT(7) /* Enable FIFO */
79 #define REG_ACTL2 5 /* Adapter Control 2 - (@) */
80 #define ACTL2_RAMOVRLY BIT(0) /* Enable RAM overlay */
84 #define REG_SCSI_DATA_NOACK 8 /* R/W: SCSI Data (no ACK) */
86 #define ASTAT3_ACTDEASS BIT(0) /* Active deassert enabled */
99 #define CFG2_IRQEDGE BIT(2) /* Edge-triggered interrupts */
101 #define CFG2_32BIT BIT(7) /* 32-bit mode */
103 #define REG_FIFO_COUNT 14 /* R: FIFO Data Count */