Lines Matching full:outbound

243 /* outbound firmware ok */
325 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK	0x00000004 /* When clear, the General Outbound Door…
326 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK	0x00000008 /* When clear, the Outbound Post List F…
331 	** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register.
332 …** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or throug…
336 	** Set if Outbound Doorbell register bits 30:1 have a non-zero
337 	** value. This bit clears only when Outbound Doorbell bits
338 	** 30:1 are ALL clear. Only a write to the Outbound Doorbell
339 	** Clear register clears bits in the Outbound Doorbell register.
343 	** Set whenever the Outbound Post List Producer/Consumer
344 	** Register (FIFO) is not empty. It clears when the Outbound
360 	/*outbound DATA WRITE isr door bell clear*/
363 	/*outbound DATA READ isr door bell clear*/
365 	/*outbound message 0 ready*/
367 	/*outbound message cmd isr door bell clear*/
413 /*outbound DATA WRITE isr door bell clear*/
415 /*outbound message 0 ready*/
417 /*outbound message cmd isr door bell clear*/
1039 **  Outbound Interrupt Status Register - OISR
1056 **  Outbound Interrupt Mask Register - OIMR