105  * @cores: list of R5 cores within the cluster
112 	struct list_head cores;  member
299 	/* assert local reset on all applicable cores */  in k3_r5_lockstep_reset()
300 	list_for_each_entry(core, &cluster->cores, elem) {  in k3_r5_lockstep_reset()
310 	/* disable PSC modules on all applicable cores */  in k3_r5_lockstep_reset()
311 	list_for_each_entry(core, &cluster->cores, elem) {  in k3_r5_lockstep_reset()
324 	list_for_each_entry_continue_reverse(core, &cluster->cores, elem) {  in k3_r5_lockstep_reset()
329 	core = list_last_entry(&cluster->cores, struct k3_r5_core, elem);  in k3_r5_lockstep_reset()
331 	list_for_each_entry_from_reverse(core, &cluster->cores, elem) {  in k3_r5_lockstep_reset()
344 	/* enable PSC modules on all applicable cores */  in k3_r5_lockstep_release()
345 	list_for_each_entry_reverse(core, &cluster->cores, elem) {  in k3_r5_lockstep_release()
356 	/* deassert local reset on all applicable cores */  in k3_r5_lockstep_release()
357 	list_for_each_entry_reverse(core, &cluster->cores, elem) {  in k3_r5_lockstep_release()
369 	list_for_each_entry_continue(core, &cluster->cores, elem) {  in k3_r5_lockstep_release()
373 	core = list_first_entry(&cluster->cores, struct k3_r5_core, elem);  in k3_r5_lockstep_release()
375 	list_for_each_entry_from(core, &cluster->cores, elem) {  in k3_r5_lockstep_release()
432  * The R5F cores have controls for both a reset and a halt/run. The code
435  * applicable cores to allow loading into the TCMs. The .prepare() ops is
437  * by the .start() ops after loading to actually let the R5 cores run.
440  * execute code, but combines the TCMs from both cores. The resets for both
441  * cores need to be released to make this possible, as the TCMs are in general
468 		dev_err(dev, "unable to enable cores for TCM loading, ret = %d\n",  in k3_r5_rproc_prepare()
501  * resets on all applicable cores for the rproc device (depending on LockStep
503  * cores. The cores themselves are only halted in the .stop() ops, and the
508  * both cores. The access is made possible only with releasing the resets for
509  * both cores, but with only Core0 unhalted. This function re-uses the same
527 		dev_err(dev, "unable to disable cores, ret = %d\n", ret);  in k3_r5_rproc_unprepare()
539  * unhalt both the cores to start the execution - Core1 needs to be unhalted
568 	/* unhalt/run all applicable cores */  in k3_r5_rproc_start()
570 		list_for_each_entry_reverse(core, &cluster->cores, elem) {  in k3_r5_rproc_start()
577 		core0 = list_first_entry(&cluster->cores, struct k3_r5_core,  in k3_r5_rproc_start()
596 	list_for_each_entry_continue(core, &cluster->cores, elem) {  in k3_r5_rproc_start()
608  * of cores the operations are performed are also in general reverse to that
635 	/* halt all applicable cores */  in k3_r5_rproc_stop()
637 		list_for_each_entry(core, &cluster->cores, elem) {  in k3_r5_rproc_stop()
646 		core1 = list_last_entry(&cluster->cores, struct k3_r5_core,  in k3_r5_rproc_stop()
663 	list_for_each_entry_from_reverse(core, &cluster->cores, elem) {  in k3_r5_rproc_stop()
676  * no need to issue any TI-SCI commands to boot the R5F cores in IPC-only mode.
685  * The R5F detach callback is a NOP. The R5F cores are not stopped and will be
817  * the cores are halted before the .prepare() step.
828  * The function behavior is different based on the cluster mode. The R5F cores
833  * both the cores with the same settings, before reconfiguing again for
848 	core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);  in k3_r5_rproc_configure()
888 		 * permitted cores  in k3_r5_rproc_configure()
923 		 * cores are programmed symmetrically in LockStep. LockStep  in k3_r5_rproc_configure()
926 		list_for_each_entry(temp, &cluster->cores, elem) {  in k3_r5_rproc_configure()
1020 		 * RAT is programmable only by the R5F cores. Support for RAT  in k3_r5_reserved_mem_init()
1048  * cores are usable in Split-mode, but only the Core0 TCMs can be used in
1071 	core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);  in k3_r5_adjust_tcm_sizes()
1111 	core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);  in k3_r5_rproc_configure_mode()
1133 	 * Skip the waiting mechanism for sequential power-on of cores if the  in k3_r5_rproc_configure_mode()
1213 	core1 = list_last_entry(&cluster->cores, struct k3_r5_core, elem);  in k3_r5_cluster_rproc_init()
1214 	list_for_each_entry(core, &cluster->cores, elem) {  in k3_r5_cluster_rproc_init()
1284 		 * R5 cores require to be powered on sequentially, core0  in k3_r5_cluster_rproc_init()
1342 		list_first_entry(&cluster->cores, struct k3_r5_core, elem) :  in k3_r5_cluster_rproc_exit()
1343 		list_last_entry(&cluster->cores, struct k3_r5_core, elem);  in k3_r5_cluster_rproc_exit()
1345 	list_for_each_entry_from_reverse(core, &cluster->cores, elem) {  in k3_r5_cluster_rproc_exit()
1408 		 * The R5F cores can place ATCM & BTCM anywhere in its address  in k3_r5_core_of_get_internal_memories()
1622 	list_for_each_entry_safe_reverse(core, temp, &cluster->cores, elem) {  in k3_r5_cluster_of_exit()
1656 		list_add_tail(&core->elem, &cluster->cores);  in k3_r5_cluster_of_init()
1687 	INIT_LIST_HEAD(&cluster->cores);  in k3_r5_probe()
1719 				     "MCU cluster requires both R5F cores to be enabled but num_cores is set to = %d\n",  in k3_r5_probe()