15 #define RTQ2208_REG_GLOBAL_INT1			0x12
16 #define RTQ2208_REG_FLT_RECORDBUCK_CB		0x18
17 #define RTQ2208_REG_GLOBAL_INT1_MASK		0x1D
18 #define RTQ2208_REG_FLT_MASKBUCK_CB		0x1F
19 #define RTQ2208_REG_BUCK_C_CFG0			0x32
20 #define RTQ2208_REG_BUCK_B_CFG0			0x42
21 #define RTQ2208_REG_BUCK_A_CFG0			0x52
22 #define RTQ2208_REG_BUCK_D_CFG0			0x62
23 #define RTQ2208_REG_BUCK_G_CFG0			0x72
24 #define RTQ2208_REG_BUCK_F_CFG0			0x82
25 #define RTQ2208_REG_BUCK_E_CFG0			0x92
26 #define RTQ2208_REG_BUCK_H_CFG0			0xA2
27 #define RTQ2208_REG_LDO1_CFG			0xB1
28 #define RTQ2208_REG_LDO2_CFG			0xC1
29 #define RTQ2208_REG_LDO_DVS_CTRL		0xD0
30 #define RTQ2208_REG_HIDDEN_BUCKPH		0x55
31 #define RTQ2208_REG_HIDDEN_LDOCFG0		0x8F
32 #define RTQ2208_REG_HIDDEN_LDOCFG1		0x96
33 #define RTQ2208_REG_HIDDEN0			0xFE
34 #define RTQ2208_REG_HIDDEN1			0xFF
37 #define RTQ2208_BUCK_NR_MTP_SEL_MASK		GENMASK(7, 0)
38 #define RTQ2208_BUCK_EN_NR_MTP_SEL0_MASK	BIT(0)
41 #define RTQ2208_BUCK_RSPDN_MASK			GENMASK(2, 0)
44 #define RTQ2208_BUCK_EN_STR_MASK		BIT(0)
46 #define RTQ2208_EN_DIS_MASK			BIT(0)
47 #define RTQ2208_BUCK_RAMP_SEL_MASK		GENMASK(2, 0)
48 #define RTQ2208_HD_INT_MASK			BIT(0)
54 #define RTQ2208_MASK_BUCKPH_GROUP2		GENMASK(2, 0)
71 	RTQ2208_BUCK_B = 0,
85 	RTQ2208_AUTO_MODE = 0,
146 	unsigned int sel = 0, val;  in rtq2208_set_ramp_delay()
154 	 * fls(ramp_delay) - 1: doing LSB shift, let it starts from 0  in rtq2208_set_ramp_delay()
164 	 * For example, if I would like to select 16mv, the fls(ramp_delay) - 1 will be 0b010,  in rtq2208_set_ramp_delay()
165 	 * and I need to use 0b111 - sel to do the shifting  in rtq2208_set_ramp_delay()
190 	return regmap_update_bits(rdev->regmap, rdesc->suspend_config_reg, rdesc->suspend_enable_mask, 0);  in rtq2208_set_suspend_disable()
272 	unsigned char buck_clr_masks[5] = {0x33, 0x33, 0x33, 0x33, 0x33},  in rtq2208_init_irq_mask()
273 		      sts_clr_masks[2] = {0xE7, 0xF7}, sts_masks[2] = {0xE6, 0xF6};  in rtq2208_init_irq_mask()
298 	int ret = 0, i, uv_bit, ov_bit;  in rtq2208_irq_handler()
327 	for (i = 0; i < RTQ2208_LDO_MAX; i++) {  in rtq2208_irq_handler()
333 		uv_bit = (i & 1) ? 4 : 0;  in rtq2208_irq_handler()
375 	REGULATOR_LINEAR_RANGE(400000, 0, 180, 5000),
413 	desc->enable_mask = mtp_sel ? MTP_SEL_MASK(1) : MTP_SEL_MASK(0);  in rtq2208_init_regulator_desc()
415 	desc->active_discharge_off = 0;  in rtq2208_init_regulator_desc()
473 	for (i = 0; i < n_regulator; i++) {  in rtq2208_parse_regulator_dt_data()
476 		rdesc[i] = devm_kcalloc(dev, 1, sizeof(*rdesc[0]), GFP_KERNEL);  in rtq2208_parse_regulator_dt_data()
483 	return 0;  in rtq2208_parse_regulator_dt_data()
492 	bool rtq2208_used_table[RTQ2208_LDO_MAX] = {0};  in rtq2208_regulator_check()
493 	u8 entry_key[] = { 0x69, 0x01 };  in rtq2208_regulator_check()
514 	ret = regmap_write(regmap, RTQ2208_REG_HIDDEN1, 0x00);  in rtq2208_regulator_check()
518 	dev_info(dev, "BUCK Phase 0x%x\n", buck_phase);  in rtq2208_regulator_check()
522 	 * 0      -> 2P + 2P                BC           FG  in rtq2208_regulator_check()
535 	case 0:  in rtq2208_regulator_check()
551 	case 0:  in rtq2208_regulator_check()
560 	*ldo1_fixed_uV = FIELD_GET(RTQ2208_MASK_LDO1_FIXED, ldo_cfg1) ? 1200000 : 0;  in rtq2208_regulator_check()
564 		*ldo2_fixed_uV = 0;  in rtq2208_regulator_check()
573 	for (i = 0; i < RTQ2208_LDO_MAX; i++) {  in rtq2208_regulator_check()
583 	return 0;  in rtq2208_regulator_check()
589 	.max_register = 0xFF,
600 	int i, ret = 0, idx, n_regulator = 0;  in rtq2208_probe()
602 		     buck_masks[RTQ2208_BUCK_NUM_IRQ_REGS] = {0x33, 0x33, 0x33, 0x33, 0x33};  in rtq2208_probe()
630 	for (i = 0; i < n_regulator; i++) {  in rtq2208_probe()