Lines Matching full:temp
147 u32 temp; in get_umc_info_mi300() local
152 ret = amd_smn_read(0, MI300_ADDR_HASH_BANK0 + (i * 4), &temp); in get_umc_info_mi300()
156 addr_hash.bank[i].xor_enable = FIELD_GET(ADDR_HASH_XOR_EN, temp); in get_umc_info_mi300()
157 addr_hash.bank[i].col_xor = FIELD_GET(ADDR_HASH_COL_XOR, temp); in get_umc_info_mi300()
158 addr_hash.bank[i].row_xor = FIELD_GET(ADDR_HASH_ROW_XOR, temp); in get_umc_info_mi300()
161 ret = amd_smn_read(0, MI300_ADDR_HASH_PC, &temp); in get_umc_info_mi300()
165 addr_hash.pc.xor_enable = FIELD_GET(ADDR_HASH_XOR_EN, temp); in get_umc_info_mi300()
166 addr_hash.pc.col_xor = FIELD_GET(ADDR_HASH_COL_XOR, temp); in get_umc_info_mi300()
167 addr_hash.pc.row_xor = FIELD_GET(ADDR_HASH_ROW_XOR, temp); in get_umc_info_mi300()
169 ret = amd_smn_read(0, MI300_ADDR_HASH_PC2, &temp); in get_umc_info_mi300()
173 addr_hash.bank_xor = FIELD_GET(ADDR_HASH_BANK_XOR, temp); in get_umc_info_mi300()
175 ret = amd_smn_read(0, MI300_ADDR_CFG, &temp); in get_umc_info_mi300()
179 bit_shifts.num_row_hi = FIELD_GET(ADDR_CFG_NUM_ROW_HI, temp); in get_umc_info_mi300()
180 bit_shifts.num_row_lo = 10 + FIELD_GET(ADDR_CFG_NUM_ROW_LO, temp); in get_umc_info_mi300()
182 ret = amd_smn_read(0, MI300_ADDR_SEL, &temp); in get_umc_info_mi300()
186 bit_shifts.bank[0] = 5 + FIELD_GET(ADDR_SEL_BANK0, temp); in get_umc_info_mi300()
187 bit_shifts.bank[1] = 5 + FIELD_GET(ADDR_SEL_BANK1, temp); in get_umc_info_mi300()
188 bit_shifts.bank[2] = 5 + FIELD_GET(ADDR_SEL_BANK2, temp); in get_umc_info_mi300()
189 bit_shifts.bank[3] = 5 + FIELD_GET(ADDR_SEL_BANK3, temp); in get_umc_info_mi300()
191 bit_shifts.sid[0] = 5 + FIELD_GET(ADDR_SEL_BANK4, temp); in get_umc_info_mi300()
192 bit_shifts.row_lo = 12 + FIELD_GET(ADDR_SEL_ROW_LO, temp); in get_umc_info_mi300()
193 bit_shifts.row_hi = 24 + FIELD_GET(ADDR_SEL_ROW_HI, temp); in get_umc_info_mi300()
195 ret = amd_smn_read(0, MI300_COL_SEL_LO, &temp); in get_umc_info_mi300()
199 bit_shifts.col[0] = 2 + FIELD_GET(COL_SEL_LO_COL0, temp); in get_umc_info_mi300()
200 bit_shifts.col[1] = 2 + FIELD_GET(COL_SEL_LO_COL1, temp); in get_umc_info_mi300()
201 bit_shifts.col[2] = 2 + FIELD_GET(COL_SEL_LO_COL2, temp); in get_umc_info_mi300()
202 bit_shifts.col[3] = 2 + FIELD_GET(COL_SEL_LO_COL3, temp); in get_umc_info_mi300()
203 bit_shifts.col[4] = 2 + FIELD_GET(COL_SEL_LO_COL4, temp); in get_umc_info_mi300()
205 ret = amd_smn_read(0, MI300_ADDR_SEL_2, &temp); in get_umc_info_mi300()
210 bit_shifts.sid[1] = 5 + FIELD_GET(ADDR_SEL_2_BANK5, temp); in get_umc_info_mi300()
211 bit_shifts.pc = 5 + FIELD_GET(ADDR_SEL_2_CHAN, temp); in get_umc_info_mi300()
240 u32 temp; in convert_dram_to_norm_addr_mi300() local
253 temp = bitwise_xor_bits(col & addr_hash.bank[i].col_xor); in convert_dram_to_norm_addr_mi300()
254 temp ^= bitwise_xor_bits(row & addr_hash.bank[i].row_xor); in convert_dram_to_norm_addr_mi300()
255 bank ^= temp << i; in convert_dram_to_norm_addr_mi300()
260 temp = bitwise_xor_bits(col & addr_hash.pc.col_xor); in convert_dram_to_norm_addr_mi300()
261 temp ^= bitwise_xor_bits(row & addr_hash.pc.row_xor); in convert_dram_to_norm_addr_mi300()
263 temp ^= bitwise_xor_bits((bank | sid << NUM_BANK_BITS) & addr_hash.bank_xor); in convert_dram_to_norm_addr_mi300()
264 pc ^= temp; in convert_dram_to_norm_addr_mi300()
272 temp = (col >> i) & 0x1; in convert_dram_to_norm_addr_mi300()
273 addr |= temp << bit_shifts.col[i]; in convert_dram_to_norm_addr_mi300()
278 temp = (bank >> i) & 0x1; in convert_dram_to_norm_addr_mi300()
279 addr |= temp << bit_shifts.bank[i]; in convert_dram_to_norm_addr_mi300()
284 temp = (row >> i) & 0x1; in convert_dram_to_norm_addr_mi300()
285 addr |= temp << (i + bit_shifts.row_lo); in convert_dram_to_norm_addr_mi300()
290 temp = (row >> (i + bit_shifts.num_row_lo)) & 0x1; in convert_dram_to_norm_addr_mi300()
291 addr |= temp << (i + bit_shifts.row_hi); in convert_dram_to_norm_addr_mi300()
299 temp = (sid >> i) & 0x1; in convert_dram_to_norm_addr_mi300()
300 addr |= temp << bit_shifts.sid[i]; in convert_dram_to_norm_addr_mi300()