73 	struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);  in mchp_core_pwm_enable()  local
84 	channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset);  in mchp_core_pwm_enable()
88 	writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset);  in mchp_core_pwm_enable()
89 	mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm);  in mchp_core_pwm_enable()
90 	mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm;  in mchp_core_pwm_enable()
97 	if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm))  in mchp_core_pwm_enable()
98 		mchp_core_pwm->update_timestamp = ktime_add_ns(ktime_get(), period);  in mchp_core_pwm_enable()
101 static void mchp_core_pwm_wait_for_sync_update(struct mchp_core_pwm_chip *mchp_core_pwm,  in mchp_core_pwm_wait_for_sync_update()  argument
112 	if (mchp_core_pwm->sync_update_mask & (1 << channel)) {  in mchp_core_pwm_wait_for_sync_update()
117 		remaining_ns = ktime_to_ns(ktime_sub(mchp_core_pwm->update_timestamp,  in mchp_core_pwm_wait_for_sync_update()
154 	struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);  in mchp_core_pwm_apply_duty()  local
180 	writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));  in mchp_core_pwm_apply_duty()
181 	writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));  in mchp_core_pwm_apply_duty()
276 	struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);  in mchp_core_pwm_apply_locked()  local
293 	clk_rate = clk_get_rate(mchp_core_pwm->clk);  in mchp_core_pwm_apply_locked()
310 	period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm);  in mchp_core_pwm_apply_locked()
316 		hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);  in mchp_core_pwm_apply_locked()
317 		hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);  in mchp_core_pwm_apply_locked()
348 		writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);  in mchp_core_pwm_apply_locked()
349 		writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD);  in mchp_core_pwm_apply_locked()
362 	struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);  in mchp_core_pwm_apply()  local
365 	mutex_lock(&mchp_core_pwm->lock);  in mchp_core_pwm_apply()
367 	mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm);  in mchp_core_pwm_apply()
371 	mutex_unlock(&mchp_core_pwm->lock);  in mchp_core_pwm_apply()
379 	struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);  in mchp_core_pwm_get_state()  local
384 	mutex_lock(&mchp_core_pwm->lock);  in mchp_core_pwm_get_state()
386 	mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm);  in mchp_core_pwm_get_state()
388 	if (mchp_core_pwm->channel_enabled & (1 << pwm->hwpwm))  in mchp_core_pwm_get_state()
393 	rate = clk_get_rate(mchp_core_pwm->clk);  in mchp_core_pwm_get_state()
408 	prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);  in mchp_core_pwm_get_state()
409 	period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);  in mchp_core_pwm_get_state()
415 	posedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));  in mchp_core_pwm_get_state()
416 	negedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));  in mchp_core_pwm_get_state()
418 	mutex_unlock(&mchp_core_pwm->lock);  in mchp_core_pwm_get_state()
450 	struct mchp_core_pwm_chip *mchp_core_pwm;  in mchp_core_pwm_probe()  local
454 	chip = devm_pwmchip_alloc(&pdev->dev, 16, sizeof(*mchp_core_pwm));  in mchp_core_pwm_probe()
457 	mchp_core_pwm = to_mchp_core_pwm(chip);  in mchp_core_pwm_probe()
459 	mchp_core_pwm->base = devm_platform_get_and_ioremap_resource(pdev, 0, &regs);  in mchp_core_pwm_probe()
460 	if (IS_ERR(mchp_core_pwm->base))  in mchp_core_pwm_probe()
461 		return PTR_ERR(mchp_core_pwm->base);  in mchp_core_pwm_probe()
463 	mchp_core_pwm->clk = devm_clk_get_enabled(&pdev->dev, NULL);  in mchp_core_pwm_probe()
464 	if (IS_ERR(mchp_core_pwm->clk))  in mchp_core_pwm_probe()
465 		return dev_err_probe(&pdev->dev, PTR_ERR(mchp_core_pwm->clk),  in mchp_core_pwm_probe()
469 				 &mchp_core_pwm->sync_update_mask))  in mchp_core_pwm_probe()
470 		mchp_core_pwm->sync_update_mask = 0;  in mchp_core_pwm_probe()
472 	mutex_init(&mchp_core_pwm->lock);  in mchp_core_pwm_probe()
476 	mchp_core_pwm->channel_enabled = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(0));  in mchp_core_pwm_probe()
477 	mchp_core_pwm->channel_enabled |=  in mchp_core_pwm_probe()
478 		readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(1)) << 8;  in mchp_core_pwm_probe()
484 	writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD);  in mchp_core_pwm_probe()
485 	mchp_core_pwm->update_timestamp = ktime_get();  in mchp_core_pwm_probe()