Lines Matching +full:pwm +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0
18 #include <linux/pwm.h>
22 /* PWM registers and bits definitions */
44 * struct pwm_mediatek_chip - struct representing PWM chip
45 * @regs: base address of PWM chip
47 * @clk_main: the clock used by PWM core
48 * @clk_pwms: the clock used by each PWM channel
74 struct pwm_device *pwm) in pwm_mediatek_clk_enable() argument
79 ret = clk_prepare_enable(pc->clk_top); in pwm_mediatek_clk_enable()
83 ret = clk_prepare_enable(pc->clk_main); in pwm_mediatek_clk_enable()
87 ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]); in pwm_mediatek_clk_enable()
94 clk_disable_unprepare(pc->clk_main); in pwm_mediatek_clk_enable()
96 clk_disable_unprepare(pc->clk_top); in pwm_mediatek_clk_enable()
102 struct pwm_device *pwm) in pwm_mediatek_clk_disable() argument
106 clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]); in pwm_mediatek_clk_disable()
107 clk_disable_unprepare(pc->clk_main); in pwm_mediatek_clk_disable()
108 clk_disable_unprepare(pc->clk_top); in pwm_mediatek_clk_disable()
112 unsigned int num, unsigned int offset, in pwm_mediatek_writel() argument
115 writel(value, chip->regs + chip->soc->reg_offset[num] + offset); in pwm_mediatek_writel()
118 static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, in pwm_mediatek_config() argument
128 ret = pwm_mediatek_clk_enable(chip, pwm); in pwm_mediatek_config()
132 clk_rate = clk_get_rate(pc->clk_pwms[pwm->hwpwm]); in pwm_mediatek_config()
134 return -EINVAL; in pwm_mediatek_config()
137 if (pc->soc->has_ck_26m_sel) in pwm_mediatek_config()
138 writel(0, pc->regs + PWM_CK_26M_SEL); in pwm_mediatek_config()
153 pwm_mediatek_clk_disable(chip, pwm); in pwm_mediatek_config()
155 return -EINVAL; in pwm_mediatek_config()
158 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) { in pwm_mediatek_config()
160 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES in pwm_mediatek_config()
168 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); in pwm_mediatek_config()
169 pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period); in pwm_mediatek_config()
170 pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); in pwm_mediatek_config()
172 pwm_mediatek_clk_disable(chip, pwm); in pwm_mediatek_config()
177 static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm) in pwm_mediatek_enable() argument
183 ret = pwm_mediatek_clk_enable(chip, pwm); in pwm_mediatek_enable()
187 value = readl(pc->regs); in pwm_mediatek_enable()
188 value |= BIT(pwm->hwpwm); in pwm_mediatek_enable()
189 writel(value, pc->regs); in pwm_mediatek_enable()
194 static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm) in pwm_mediatek_disable() argument
199 value = readl(pc->regs); in pwm_mediatek_disable()
200 value &= ~BIT(pwm->hwpwm); in pwm_mediatek_disable()
201 writel(value, pc->regs); in pwm_mediatek_disable()
203 pwm_mediatek_clk_disable(chip, pwm); in pwm_mediatek_disable()
206 static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm, in pwm_mediatek_apply() argument
211 if (state->polarity != PWM_POLARITY_NORMAL) in pwm_mediatek_apply()
212 return -EINVAL; in pwm_mediatek_apply()
214 if (!state->enabled) { in pwm_mediatek_apply()
215 if (pwm->state.enabled) in pwm_mediatek_apply()
216 pwm_mediatek_disable(chip, pwm); in pwm_mediatek_apply()
221 err = pwm_mediatek_config(chip, pwm, state->duty_cycle, state->period); in pwm_mediatek_apply()
225 if (!pwm->state.enabled) in pwm_mediatek_apply()
226 err = pwm_mediatek_enable(chip, pwm); in pwm_mediatek_apply()
243 soc = of_device_get_match_data(&pdev->dev); in pwm_mediatek_probe()
245 chip = devm_pwmchip_alloc(&pdev->dev, soc->num_pwms, sizeof(*pc)); in pwm_mediatek_probe()
250 pc->soc = soc; in pwm_mediatek_probe()
252 pc->regs = devm_platform_ioremap_resource(pdev, 0); in pwm_mediatek_probe()
253 if (IS_ERR(pc->regs)) in pwm_mediatek_probe()
254 return PTR_ERR(pc->regs); in pwm_mediatek_probe()
256 pc->clk_pwms = devm_kmalloc_array(&pdev->dev, soc->num_pwms, in pwm_mediatek_probe()
257 sizeof(*pc->clk_pwms), GFP_KERNEL); in pwm_mediatek_probe()
258 if (!pc->clk_pwms) in pwm_mediatek_probe()
259 return -ENOMEM; in pwm_mediatek_probe()
261 pc->clk_top = devm_clk_get(&pdev->dev, "top"); in pwm_mediatek_probe()
262 if (IS_ERR(pc->clk_top)) in pwm_mediatek_probe()
263 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top), in pwm_mediatek_probe()
266 pc->clk_main = devm_clk_get(&pdev->dev, "main"); in pwm_mediatek_probe()
267 if (IS_ERR(pc->clk_main)) in pwm_mediatek_probe()
268 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main), in pwm_mediatek_probe()
271 for (i = 0; i < soc->num_pwms; i++) { in pwm_mediatek_probe()
274 snprintf(name, sizeof(name), "pwm%d", i + 1); in pwm_mediatek_probe()
276 pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name); in pwm_mediatek_probe()
277 if (IS_ERR(pc->clk_pwms[i])) in pwm_mediatek_probe()
278 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]), in pwm_mediatek_probe()
282 chip->ops = &pwm_mediatek_ops; in pwm_mediatek_probe()
284 ret = devm_pwmchip_add(&pdev->dev, chip); in pwm_mediatek_probe()
286 return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n"); in pwm_mediatek_probe()
376 { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
377 { .compatible = "mediatek,mt6795-pwm", .data = &mt6795_pwm_data },
378 { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
379 { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
380 { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
381 { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
382 { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
383 { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
384 { .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data },
385 { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
386 { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
387 { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
394 .name = "pwm-mediatek",