1 // SPDX-License-Identifier: GPL-2.0
7  *          Vineetha G. Jaya Kumaran <vineetha.g[email protected]>
10  * - Upon disabling a channel, the currently running
68  * for all valid masks (e.g. KMB_PWM_LEADIN_MASK) that they are ok.
73 	u32 buff = readl(priv->base + offset);  in keembay_pwm_update_bits()
76 	writel(buff, priv->base + offset);  in keembay_pwm_update_bits()
95 	unsigned long long high, low;  in keembay_pwm_get_state()  local
99 	clk_rate = clk_get_rate(priv->clk);  in keembay_pwm_get_state()
102 	highlow = readl(priv->base + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));  in keembay_pwm_get_state()
104 		state->enabled = true;  in keembay_pwm_get_state()
106 		state->enabled = false;  in keembay_pwm_get_state()
109 	highlow = readl(priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));  in keembay_pwm_get_state()
110 	low = FIELD_GET(KMB_PWM_LOW_MASK, highlow) * NSEC_PER_SEC;  in keembay_pwm_get_state()
112 	state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate);  in keembay_pwm_get_state()
113 	state->period = DIV_ROUND_UP_ULL(high + low, clk_rate);  in keembay_pwm_get_state()
114 	state->polarity = PWM_POLARITY_NORMAL;  in keembay_pwm_get_state()
127 	u16 high, low;  in keembay_pwm_apply()  local
129 	if (state->polarity != PWM_POLARITY_NORMAL)  in keembay_pwm_apply()
130 		return -EINVAL;  in keembay_pwm_apply()
134 	 * low time as 0 at (30:16), which is in terms of clock cycles.  in keembay_pwm_apply()
137 				KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));  in keembay_pwm_apply()
141 	if (!state->enabled) {  in keembay_pwm_apply()
143 			keembay_pwm_disable(priv, pwm->hwpwm);  in keembay_pwm_apply()
149 	 * register contain the high time and low time of waveform accordingly.  in keembay_pwm_apply()
153 	clk_rate = clk_get_rate(priv->clk);  in keembay_pwm_apply()
154 	div = clk_rate * state->duty_cycle;  in keembay_pwm_apply()
157 		return -ERANGE;  in keembay_pwm_apply()
160 	div = clk_rate * state->period;  in keembay_pwm_apply()
162 	div = div - high;  in keembay_pwm_apply()
164 		return -ERANGE;  in keembay_pwm_apply()
166 	low = div;  in keembay_pwm_apply()
169 		    FIELD_PREP(KMB_PWM_LOW_MASK, low);  in keembay_pwm_apply()
171 	writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));  in keembay_pwm_apply()
173 	if (state->enabled && !current_state.enabled)  in keembay_pwm_apply()
174 		keembay_pwm_enable(priv, pwm->hwpwm);  in keembay_pwm_apply()
186 	struct device *dev = &pdev->dev;  in keembay_pwm_probe()
196 	priv->clk = devm_clk_get(dev, NULL);  in keembay_pwm_probe()
197 	if (IS_ERR(priv->clk))  in keembay_pwm_probe()
198 		return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clock\n");  in keembay_pwm_probe()
200 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in keembay_pwm_probe()
201 	if (IS_ERR(priv->base))  in keembay_pwm_probe()
202 		return PTR_ERR(priv->base);  in keembay_pwm_probe()
204 	ret = keembay_clk_enable(dev, priv->clk);  in keembay_pwm_probe()
208 	chip->ops = &keembay_pwm_ops;  in keembay_pwm_probe()
218 	{ .compatible = "intel,keembay-pwm" },
226 		.name = "pwm-keembay",
232 MODULE_ALIAS("platform:pwm-keembay");