107 	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);  in pwm_imx27_get_state()  local
112 	ret = clk_bulk_prepare_enable(imx->clks_cnt, imx->clks);  in pwm_imx27_get_state()
116 	val = readl(imx->mmio_base + MX3_PWMCR);  in pwm_imx27_get_state()
135 	pwm_clk = clk_get_rate(imx->clks[PWM_IMX27_PER].clk);  in pwm_imx27_get_state()
136 	val = readl(imx->mmio_base + MX3_PWMPR);  in pwm_imx27_get_state()
148 		val = readl(imx->mmio_base + MX3_PWMSAR);  in pwm_imx27_get_state()
150 		val = imx->duty_cycle;  in pwm_imx27_get_state()
155 	clk_bulk_disable_unprepare(imx->clks_cnt, imx->clks);  in pwm_imx27_get_state()
162 	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);  in pwm_imx27_sw_reset()  local
167 	writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);  in pwm_imx27_sw_reset()
170 		cr = readl(imx->mmio_base + MX3_PWMCR);  in pwm_imx27_sw_reset()
181 	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);  in pwm_imx27_wait_fifo_slot()  local
187 	sr = readl(imx->mmio_base + MX3_PWMSR);  in pwm_imx27_wait_fifo_slot()
194 		sr = readl(imx->mmio_base + MX3_PWMSR);  in pwm_imx27_wait_fifo_slot()
204 	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);  in pwm_imx27_apply()  local
212 	clkrate = clk_get_rate(imx->clks[PWM_IMX27_PER].clk);  in pwm_imx27_apply()
227 	 * according to imx pwm RM, the real period value should be PERIOD  in pwm_imx27_apply()
242 		ret = clk_bulk_prepare_enable(imx->clks_cnt, imx->clks);  in pwm_imx27_apply()
249 	val = readl(imx->mmio_base + MX3_PWMPR);  in pwm_imx27_apply()
251 	cr = readl(imx->mmio_base + MX3_PWMCR);  in pwm_imx27_apply()
319 	val = FIELD_GET(MX3_PWMSR_FIFOAV, readl_relaxed(imx->mmio_base + MX3_PWMSR));  in pwm_imx27_apply()
321 	if (duty_cycles < imx->duty_cycle && (cr & MX3_PWMCR_EN)) {  in pwm_imx27_apply()
325 			writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR);  in pwm_imx27_apply()
326 			writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR);  in pwm_imx27_apply()
328 			val = readl_relaxed(imx->mmio_base + MX3_PWMCNR);  in pwm_imx27_apply()
333 			if ((val + c >= duty_cycles && val < imx->duty_cycle) ||  in pwm_imx27_apply()
335 				writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR);  in pwm_imx27_apply()
338 	writel_relaxed(duty_cycles, imx->mmio_base + MX3_PWMSAR);  in pwm_imx27_apply()
341 	writel(period_cycles, imx->mmio_base + MX3_PWMPR);  in pwm_imx27_apply()
347 	imx->duty_cycle = duty_cycles;  in pwm_imx27_apply()
361 	writel(cr, imx->mmio_base + MX3_PWMCR);  in pwm_imx27_apply()
364 		clk_bulk_disable_unprepare(imx->clks_cnt, imx->clks);  in pwm_imx27_apply()
383 	struct pwm_imx27_chip *imx;  in pwm_imx27_probe()  local
388 	chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*imx));  in pwm_imx27_probe()
391 	imx = to_pwm_imx27_chip(chip);  in pwm_imx27_probe()
393 	imx->clks_cnt = ARRAY_SIZE(pwm_imx27_clks);  in pwm_imx27_probe()
394 	for (i = 0; i < imx->clks_cnt; ++i)  in pwm_imx27_probe()
395 		imx->clks[i].id = pwm_imx27_clks[i];  in pwm_imx27_probe()
397 	ret = devm_clk_bulk_get(&pdev->dev, imx->clks_cnt, imx->clks);  in pwm_imx27_probe()
405 	imx->mmio_base = devm_platform_ioremap_resource(pdev, 0);  in pwm_imx27_probe()
406 	if (IS_ERR(imx->mmio_base))  in pwm_imx27_probe()
407 		return PTR_ERR(imx->mmio_base);  in pwm_imx27_probe()
409 	ret = clk_bulk_prepare_enable(imx->clks_cnt, imx->clks);  in pwm_imx27_probe()
414 	pwmcr = readl(imx->mmio_base + MX3_PWMCR);  in pwm_imx27_probe()
416 		clk_bulk_disable_unprepare(imx->clks_cnt, imx->clks);  in pwm_imx27_probe()