1 // SPDX-License-Identifier: GPL-2.0
8  * - When disabled the output is driven to 0 independent of the configured
74 #define MX3_PWMCR_PRESCALER_SET(x)	FIELD_PREP(MX3_PWMCR_PRESCALER, (x) - 1)
99 static inline struct pwm_imx27_chip *to_pwm_imx27_chip(struct pwm_chip *chip)  in to_pwm_imx27_chip()  argument
101 	return pwmchip_get_drvdata(chip);  in to_pwm_imx27_chip()
104 static int pwm_imx27_get_state(struct pwm_chip *chip,  in pwm_imx27_get_state()  argument
107 	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);  in pwm_imx27_get_state()
112 	ret = clk_bulk_prepare_enable(imx->clks_cnt, imx->clks);  in pwm_imx27_get_state()
116 	val = readl(imx->mmio_base + MX3_PWMCR);  in pwm_imx27_get_state()
119 		state->enabled = true;  in pwm_imx27_get_state()
121 		state->enabled = false;  in pwm_imx27_get_state()
125 		state->polarity = PWM_POLARITY_NORMAL;  in pwm_imx27_get_state()
128 		state->polarity = PWM_POLARITY_INVERSED;  in pwm_imx27_get_state()
131 		dev_warn(pwmchip_parent(chip), "can't set polarity, output disconnected");  in pwm_imx27_get_state()
135 	pwm_clk = clk_get_rate(imx->clks[PWM_IMX27_PER].clk);  in pwm_imx27_get_state()
136 	val = readl(imx->mmio_base + MX3_PWMPR);  in pwm_imx27_get_state()
141 	state->period = DIV_ROUND_UP_ULL(tmp, pwm_clk);  in pwm_imx27_get_state()
147 	if (state->enabled)  in pwm_imx27_get_state()
148 		val = readl(imx->mmio_base + MX3_PWMSAR);  in pwm_imx27_get_state()
150 		val = imx->duty_cycle;  in pwm_imx27_get_state()
153 	state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk);  in pwm_imx27_get_state()
155 	clk_bulk_disable_unprepare(imx->clks_cnt, imx->clks);  in pwm_imx27_get_state()
160 static void pwm_imx27_sw_reset(struct pwm_chip *chip)  in pwm_imx27_sw_reset()  argument
162 	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);  in pwm_imx27_sw_reset()
163 	struct device *dev = pwmchip_parent(chip);  in pwm_imx27_sw_reset()
167 	writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);  in pwm_imx27_sw_reset()
170 		cr = readl(imx->mmio_base + MX3_PWMCR);  in pwm_imx27_sw_reset()
178 static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip,  in pwm_imx27_wait_fifo_slot()  argument
181 	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);  in pwm_imx27_wait_fifo_slot()
182 	struct device *dev = pwmchip_parent(chip);  in pwm_imx27_wait_fifo_slot()
187 	sr = readl(imx->mmio_base + MX3_PWMSR);  in pwm_imx27_wait_fifo_slot()
190 		period_ms = DIV_ROUND_UP_ULL(pwm->state.period,  in pwm_imx27_wait_fifo_slot()
194 		sr = readl(imx->mmio_base + MX3_PWMSR);  in pwm_imx27_wait_fifo_slot()
200 static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,  in pwm_imx27_apply()  argument
204 	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);  in pwm_imx27_apply()
212 	clkrate = clk_get_rate(imx->clks[PWM_IMX27_PER].clk);  in pwm_imx27_apply()
213 	c = clkrate * state->period;  in pwm_imx27_apply()
221 	c = clkrate * state->duty_cycle;  in pwm_imx27_apply()
231 		period_cycles -= 2;  in pwm_imx27_apply()
239 	if (pwm->state.enabled) {  in pwm_imx27_apply()
240 		pwm_imx27_wait_fifo_slot(chip, pwm);  in pwm_imx27_apply()
242 		ret = clk_bulk_prepare_enable(imx->clks_cnt, imx->clks);  in pwm_imx27_apply()
246 		pwm_imx27_sw_reset(chip);  in pwm_imx27_apply()
249 	val = readl(imx->mmio_base + MX3_PWMPR);  in pwm_imx27_apply()
251 	cr = readl(imx->mmio_base + MX3_PWMCR);  in pwm_imx27_apply()
269 	 * the new programmed SAMPLE value, the current period will not flip  in pwm_imx27_apply()
287 	 *    |<-- old SAR -->|               |<-- new SAR -->|  in pwm_imx27_apply()
319 	val = FIELD_GET(MX3_PWMSR_FIFOAV, readl_relaxed(imx->mmio_base + MX3_PWMSR));  in pwm_imx27_apply()
321 	if (duty_cycles < imx->duty_cycle && (cr & MX3_PWMCR_EN)) {  in pwm_imx27_apply()
325 			writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR);  in pwm_imx27_apply()
326 			writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR);  in pwm_imx27_apply()
328 			val = readl_relaxed(imx->mmio_base + MX3_PWMCNR);  in pwm_imx27_apply()
333 			if ((val + c >= duty_cycles && val < imx->duty_cycle) ||  in pwm_imx27_apply()
335 				writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR);  in pwm_imx27_apply()
338 	writel_relaxed(duty_cycles, imx->mmio_base + MX3_PWMSAR);  in pwm_imx27_apply()
341 	writel(period_cycles, imx->mmio_base + MX3_PWMPR);  in pwm_imx27_apply()
347 	imx->duty_cycle = duty_cycles;  in pwm_imx27_apply()
354 	if (state->polarity == PWM_POLARITY_INVERSED)  in pwm_imx27_apply()
358 	if (state->enabled)  in pwm_imx27_apply()
361 	writel(cr, imx->mmio_base + MX3_PWMCR);  in pwm_imx27_apply()
363 	if (!state->enabled)  in pwm_imx27_apply()
364 		clk_bulk_disable_unprepare(imx->clks_cnt, imx->clks);  in pwm_imx27_apply()
375 	{ .compatible = "fsl,imx27-pwm", },
382 	struct pwm_chip *chip;  in pwm_imx27_probe()  local
388 	chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*imx));  in pwm_imx27_probe()
389 	if (IS_ERR(chip))  in pwm_imx27_probe()
390 		return PTR_ERR(chip);  in pwm_imx27_probe()
391 	imx = to_pwm_imx27_chip(chip);  in pwm_imx27_probe()
393 	imx->clks_cnt = ARRAY_SIZE(pwm_imx27_clks);  in pwm_imx27_probe()
394 	for (i = 0; i < imx->clks_cnt; ++i)  in pwm_imx27_probe()
395 		imx->clks[i].id = pwm_imx27_clks[i];  in pwm_imx27_probe()
397 	ret = devm_clk_bulk_get(&pdev->dev, imx->clks_cnt, imx->clks);  in pwm_imx27_probe()
400 		return dev_err_probe(&pdev->dev, ret,  in pwm_imx27_probe()
403 	chip->ops = &pwm_imx27_ops;  in pwm_imx27_probe()
405 	imx->mmio_base = devm_platform_ioremap_resource(pdev, 0);  in pwm_imx27_probe()
406 	if (IS_ERR(imx->mmio_base))  in pwm_imx27_probe()
407 		return PTR_ERR(imx->mmio_base);  in pwm_imx27_probe()
409 	ret = clk_bulk_prepare_enable(imx->clks_cnt, imx->clks);  in pwm_imx27_probe()
414 	pwmcr = readl(imx->mmio_base + MX3_PWMCR);  in pwm_imx27_probe()
416 		clk_bulk_disable_unprepare(imx->clks_cnt, imx->clks);  in pwm_imx27_probe()
418 	return devm_pwmchip_add(&pdev->dev, chip);  in pwm_imx27_probe()
423 		.name = "pwm-imx27",