Lines Matching +full:7 +full:- +full:bit
1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
5 * Copyright (C) 2016-2018 Mellanox Technologies
6 * Copyright (C) 2016-2018 Vadim Pasternak <[email protected]>
12 #include <linux/i2c-mux.h>
17 #include <linux/platform_data/i2c-mux-reg.h>
211 #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0)
212 #define MLXPLAT_CPLD_AGGR_MASK_LC BIT(3)
216 #define MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT BIT(0)
217 #define MLXPLAT_CPLD_AGGR_MASK_LC_RDY BIT(1)
218 #define MLXPLAT_CPLD_AGGR_MASK_LC_PG BIT(2)
219 #define MLXPLAT_CPLD_AGGR_MASK_LC_SCRD BIT(3)
220 #define MLXPLAT_CPLD_AGGR_MASK_LC_SYNC BIT(4)
221 #define MLXPLAT_CPLD_AGGR_MASK_LC_ACT BIT(5)
222 #define MLXPLAT_CPLD_AGGR_MASK_LC_SDWN BIT(6)
231 #define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2)
233 #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6)
241 #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4)
247 #define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0)
248 #define MLXPLAT_CPLD_LATCH_RST_MASK BIT(6)
249 #define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3)
250 #define MLXPLAT_CPLD_THERMAL2_PDB_MASK BIT(4)
251 #define MLXPLAT_CPLD_INTRUSION_MASK BIT(6)
252 #define MLXPLAT_CPLD_PWM_PG_MASK BIT(7)
259 #define MLXPLAT_CPLD_SYS_RESET_MASK BIT(0)
262 #define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1)
268 #define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0)
270 #define MLXPLAT_CPLD_HALT_MASK BIT(3)
271 #define MLXPLAT_CPLD_RESET_MASK GENMASK(7, 1)
297 #define MLXPLAT_CPLD_NR_NONE -1
311 #define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1)
312 #define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1))
314 #define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4)
316 #define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1)
317 #define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4))
318 #define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7))
319 #define MLXPLAT_CPLD_WD_CPBLTY_MASK (GENMASK(7, 0) & ~BIT(6))
341 /* mlxplat_priv - platform private data
342 * @pdev_i2c - i2c controller platform device
343 * @pdev_mux - array of mux platform devices
344 * @pdev_hotplug - hotplug platform devices
345 * @pdev_led - led platform devices
346 * @pdev_io_regs - register access platform devices
347 * @pdev_fan - FAN platform devices
348 * @pdev_wd - array of watchdog platform devices
395 .bit = MLXPLAT_CPLD_I2C_CAP_BIT,
420 5, MLXPLAT_CPLD_CH1 + 6, MLXPLAT_CPLD_CH1 + 7
425 5, MLXPLAT_CPLD_CH2 + 6, MLXPLAT_CPLD_CH2 + 7
430 static const int mlxplat_msn21xx_channels[] = { 1, 2, 3, 4, 5, 6, 7, 8 };
491 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
542 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
572 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
649 .mask = BIT(0),
655 .mask = BIT(1),
665 .mask = BIT(0),
671 .mask = BIT(1),
680 .mask = BIT(0),
687 .mask = BIT(1),
697 .mask = BIT(0),
703 .mask = BIT(1),
712 .mask = BIT(0),
719 .mask = BIT(1),
729 .mask = BIT(0),
736 .mask = BIT(1),
743 .mask = BIT(2),
750 .mask = BIT(3),
916 .mask = BIT(0),
922 .mask = BIT(1),
964 .mask = BIT(0),
970 .mask = BIT(1),
979 .mask = BIT(0),
986 .mask = BIT(1),
996 .mask = BIT(0),
1002 .mask = BIT(1),
1008 .mask = BIT(2),
1014 .mask = BIT(3),
1073 .mask = BIT(0),
1079 .mask = BIT(1),
1120 .mask = BIT(0),
1126 .mask = BIT(1),
1135 .mask = BIT(0),
1137 .bit = BIT(0),
1143 .mask = BIT(1),
1145 .bit = BIT(1),
1151 .mask = BIT(2),
1153 .bit = BIT(2),
1159 .mask = BIT(3),
1161 .bit = BIT(3),
1167 .mask = BIT(4),
1169 .bit = BIT(4),
1175 .mask = BIT(5),
1177 .bit = BIT(5),
1183 .mask = BIT(6),
1185 .bit = BIT(6),
1244 .mask = BIT(0),
1250 .mask = BIT(1),
1256 .mask = BIT(2),
1262 .mask = BIT(3),
1271 .mask = BIT(0),
1278 .mask = BIT(1),
1285 .mask = BIT(2),
1292 .mask = BIT(3),
1413 .mask = BIT(0),
1420 .mask = BIT(1),
1427 .mask = BIT(2),
1434 .mask = BIT(3),
1456 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1460 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1464 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1468 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1472 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1476 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1480 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1484 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1520 .mask = BIT(0),
1530 .mask = BIT(1),
1540 .mask = BIT(2),
1550 .mask = BIT(3),
1560 .mask = BIT(4),
1570 .mask = BIT(5),
1580 .mask = BIT(6),
1585 .slot = 7,
1590 .mask = BIT(7),
1591 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1592 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1594 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1603 .mask = BIT(0),
1617 .mask = BIT(1),
1631 .mask = BIT(2),
1645 .mask = BIT(3),
1659 .mask = BIT(4),
1673 .mask = BIT(5),
1687 .mask = BIT(6),
1696 .slot = 7,
1701 .mask = BIT(7),
1706 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1707 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1709 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1718 .mask = BIT(0),
1728 .mask = BIT(1),
1738 .mask = BIT(2),
1748 .mask = BIT(3),
1758 .mask = BIT(4),
1768 .mask = BIT(5),
1778 .mask = BIT(6),
1783 .slot = 7,
1788 .mask = BIT(7),
1789 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1790 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1792 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1801 .mask = BIT(0),
1811 .mask = BIT(1),
1821 .mask = BIT(2),
1831 .mask = BIT(3),
1841 .mask = BIT(4),
1851 .mask = BIT(5),
1861 .mask = BIT(6),
1866 .slot = 7,
1871 .mask = BIT(7),
1872 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1873 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1875 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1884 .mask = BIT(0),
1894 .mask = BIT(1),
1904 .mask = BIT(2),
1914 .mask = BIT(3),
1924 .mask = BIT(4),
1934 .mask = BIT(5),
1944 .mask = BIT(6),
1949 .slot = 7,
1954 .mask = BIT(7),
1955 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1956 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1958 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1967 .mask = BIT(0),
1977 .mask = BIT(1),
1987 .mask = BIT(2),
1997 .mask = BIT(3),
2007 .mask = BIT(4),
2017 .mask = BIT(5),
2027 .mask = BIT(6),
2032 .slot = 7,
2037 .mask = BIT(7),
2038 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
2039 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
2041 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
2050 .mask = BIT(0),
2060 .mask = BIT(1),
2070 .mask = BIT(2),
2080 .mask = BIT(3),
2090 .mask = BIT(4),
2100 .mask = BIT(5),
2110 .mask = BIT(6),
2115 .slot = 7,
2120 .mask = BIT(7),
2121 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
2122 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
2124 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
2287 .mask = BIT(0),
2293 .mask = BIT(1),
2302 .mask = BIT(0),
2308 .mask = BIT(1),
2379 dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button"); in mlxplat_mlxcpld_l1_switch_pwr_events_handler()
2411 err = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ®val); in mlxplat_mlxcpld_l1_switch_intrusion_events_handler()
2416 dev_info(&mlxplat_dev->dev, "Detected intrusion - system latch is opened"); in mlxplat_mlxcpld_l1_switch_intrusion_events_handler()
2417 err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, in mlxplat_mlxcpld_l1_switch_intrusion_events_handler()
2420 dev_info(&mlxplat_dev->dev, "System latch is properly closed"); in mlxplat_mlxcpld_l1_switch_intrusion_events_handler()
2421 err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, in mlxplat_mlxcpld_l1_switch_intrusion_events_handler()
2432 dev_err(&mlxplat_dev->dev, "Register access failed"); in mlxplat_mlxcpld_l1_switch_intrusion_events_handler()
2726 .bit = BIT(0),
2733 .bit = BIT(0),
2740 .bit = BIT(1),
2747 .bit = BIT(1),
2754 .bit = BIT(2),
2761 .bit = BIT(2),
2768 .bit = BIT(3),
2775 .bit = BIT(3),
2782 .bit = BIT(4),
2789 .bit = BIT(4),
2796 .bit = BIT(5),
2803 .bit = BIT(5),
2810 .bit = BIT(6),
2817 .bit = BIT(6),
2932 .bit = BIT(0),
2939 .bit = BIT(0),
2946 .bit = BIT(1),
2953 .bit = BIT(1),
2960 .bit = BIT(2),
2967 .bit = BIT(2),
2974 .bit = BIT(3),
2981 .bit = BIT(3),
2988 .bit = BIT(4),
2995 .bit = BIT(4),
3002 .bit = BIT(5),
3009 .bit = BIT(5),
3016 .bit = BIT(6),
3023 .bit = BIT(6),
3074 .bit = BIT(0),
3081 .bit = BIT(0),
3088 .bit = BIT(1),
3095 .bit = BIT(1),
3102 .bit = BIT(2),
3109 .bit = BIT(2),
3116 .bit = BIT(3),
3123 .bit = BIT(3),
3130 .bit = BIT(4),
3137 .bit = BIT(4),
3144 .bit = BIT(5),
3151 .bit = BIT(5),
3170 .bit = GENMASK(7, 0),
3176 .bit = GENMASK(7, 0),
3182 .bit = GENMASK(15, 0),
3189 .bit = GENMASK(15, 0),
3196 .bit = GENMASK(7, 0),
3202 .bit = GENMASK(7, 0),
3208 .mask = GENMASK(7, 0) & ~BIT(0),
3214 .mask = GENMASK(7, 0) & ~BIT(1),
3220 .mask = GENMASK(7, 0) & ~BIT(2),
3226 .mask = GENMASK(7, 0) & ~BIT(3),
3232 .mask = GENMASK(7, 0) & ~BIT(4),
3238 .mask = GENMASK(7, 0) & ~BIT(5),
3244 .mask = GENMASK(7, 0) & ~BIT(6),
3250 .mask = GENMASK(7, 0) & ~BIT(7),
3256 .mask = GENMASK(7, 0) & ~BIT(0),
3262 .mask = GENMASK(7, 0) & ~BIT(1),
3268 .mask = GENMASK(7, 0) & ~BIT(2),
3274 .mask = GENMASK(7, 0) & ~BIT(3),
3280 .mask = GENMASK(7, 0) & ~BIT(6),
3287 .bit = 1,
3302 .bit = GENMASK(7, 0),
3308 .bit = GENMASK(7, 0),
3314 .bit = GENMASK(15, 0),
3321 .bit = GENMASK(15, 0),
3328 .bit = GENMASK(7, 0),
3334 .bit = GENMASK(7, 0),
3340 .mask = GENMASK(7, 0) & ~BIT(0),
3346 .mask = GENMASK(7, 0) & ~BIT(1),
3352 .mask = GENMASK(7, 0) & ~BIT(2),
3358 .mask = GENMASK(7, 0) & ~BIT(3),
3364 .mask = GENMASK(7, 0) & ~BIT(4),
3370 .mask = GENMASK(7, 0) & ~BIT(5),
3376 .mask = GENMASK(7, 0) & ~BIT(6),
3382 .mask = GENMASK(7, 0) & ~BIT(6),
3388 .mask = GENMASK(7, 0) & ~BIT(0),
3394 .mask = GENMASK(7, 0) & ~BIT(1),
3400 .mask = GENMASK(7, 0) & ~BIT(2),
3406 .mask = GENMASK(7, 0) & ~BIT(3),
3412 .mask = GENMASK(7, 0) & ~BIT(6),
3419 .bit = 1,
3434 .bit = GENMASK(7, 0),
3440 .bit = GENMASK(7, 0),
3446 .bit = GENMASK(7, 0),
3452 .bit = GENMASK(7, 0),
3458 .bit = GENMASK(7, 0),
3464 .bit = GENMASK(15, 0),
3471 .bit = GENMASK(15, 0),
3478 .bit = GENMASK(15, 0),
3485 .bit = GENMASK(15, 0),
3492 .bit = GENMASK(15, 0),
3499 .bit = GENMASK(7, 0),
3505 .bit = GENMASK(7, 0),
3511 .bit = GENMASK(7, 0),
3517 .bit = GENMASK(7, 0),
3523 .bit = GENMASK(7, 0),
3529 .mask = GENMASK(7, 0) & ~BIT(3),
3535 .mask = GENMASK(7, 0) & ~BIT(2),
3541 .mask = GENMASK(7, 0) & ~BIT(6),
3547 .mask = GENMASK(7, 0) & ~BIT(7),
3553 .mask = GENMASK(7, 0) & ~BIT(1),
3560 .mask = GENMASK(7, 0) & ~BIT(6),
3566 .mask = GENMASK(7, 0) & ~BIT(7),
3572 .mask = GENMASK(7, 0) & ~BIT(4),
3579 .mask = GENMASK(7, 0) & ~BIT(5),
3586 .mask = GENMASK(7, 0) & ~BIT(0),
3592 .mask = GENMASK(7, 0) & ~BIT(1),
3598 .mask = GENMASK(7, 0) & ~BIT(2),
3604 .mask = GENMASK(7, 0) & ~BIT(3),
3610 .mask = GENMASK(7, 0) & ~BIT(5),
3616 .mask = GENMASK(7, 0) & ~BIT(6),
3622 .mask = GENMASK(7, 0) & ~BIT(7),
3628 .mask = GENMASK(7, 0) & ~BIT(0),
3634 .mask = GENMASK(7, 0) & ~BIT(3),
3640 .mask = GENMASK(7, 0) & ~BIT(4),
3646 .mask = GENMASK(7, 0) & ~BIT(5),
3652 .mask = GENMASK(7, 0) & ~BIT(6),
3658 .mask = GENMASK(7, 0) & ~BIT(0),
3664 .mask = GENMASK(7, 0) & ~BIT(1),
3670 .mask = GENMASK(7, 0) & ~BIT(2),
3676 .mask = GENMASK(7, 0) & ~BIT(3),
3682 .mask = GENMASK(7, 0) & ~BIT(5),
3688 .mask = GENMASK(7, 0) & ~BIT(6),
3694 .mask = GENMASK(7, 0) & ~BIT(7),
3700 .mask = GENMASK(7, 0) & ~BIT(0),
3706 .mask = GENMASK(7, 0) & ~BIT(1),
3712 .mask = GENMASK(7, 0) & ~BIT(2),
3718 .mask = GENMASK(7, 0) & ~BIT(3),
3724 .mask = GENMASK(7, 0) & ~BIT(5),
3730 .mask = GENMASK(7, 0) & ~BIT(6),
3737 .bit = 1,
3743 .mask = GENMASK(7, 0) & ~BIT(4),
3749 .bit = GENMASK(7, 0),
3755 .bit = GENMASK(7, 0),
3761 .bit = GENMASK(7, 0),
3767 .bit = GENMASK(7, 0),
3774 .bit = 1,
3781 .bit = 1,
3787 .bit = GENMASK(7, 0),
3793 .mask = GENMASK(7, 0) & ~BIT(4),
3799 .mask = GENMASK(7, 0) & ~BIT(5),
3805 .mask = GENMASK(7, 0) & ~BIT(6),
3811 .mask = GENMASK(7, 0) & ~BIT(7),
3818 .bit = 5,
3824 .mask = GENMASK(7, 0) & ~BIT(0),
3831 .mask = GENMASK(7, 0) & ~BIT(3),
3837 .mask = GENMASK(7, 0) & ~BIT(4),
3843 .mask = GENMASK(7, 0) & ~BIT(0),
3849 .mask = GENMASK(7, 0) & ~BIT(1),
3855 .mask = GENMASK(7, 0) & ~BIT(2),
3861 .mask = GENMASK(7, 0) & ~BIT(4),
3867 .mask = GENMASK(7, 0) & ~BIT(5),
3873 .mask = GENMASK(7, 0) & ~BIT(6),
3879 .mask = GENMASK(7, 0) & ~BIT(7),
3885 .mask = GENMASK(7, 0),
3886 .bit = 1,
3892 .bit = GENMASK(7, 0),
3898 .bit = GENMASK(7, 0),
3904 .bit = GENMASK(7, 0),
3910 .bit = GENMASK(7, 0),
3925 .bit = GENMASK(7, 0),
3931 .bit = GENMASK(7, 0),
3937 .bit = GENMASK(7, 0),
3943 .bit = GENMASK(7, 0),
3949 .bit = GENMASK(15, 0),
3956 .bit = GENMASK(15, 0),
3963 .bit = GENMASK(15, 0),
3970 .bit = GENMASK(15, 0),
3977 .bit = GENMASK(7, 0),
3983 .bit = GENMASK(7, 0),
3989 .bit = GENMASK(7, 0),
3995 .bit = GENMASK(7, 0),
4001 .mask = GENMASK(7, 0) & ~BIT(0),
4007 .mask = GENMASK(7, 0) & ~BIT(1),
4013 .mask = GENMASK(7, 0) & ~BIT(2),
4019 .mask = GENMASK(7, 0) & ~BIT(3),
4025 .mask = GENMASK(7, 0) & ~BIT(4),
4031 .mask = GENMASK(7, 0) & ~BIT(5),
4037 .mask = GENMASK(7, 0) & ~BIT(6),
4043 .mask = GENMASK(7, 0) & ~BIT(7),
4049 .mask = GENMASK(7, 0) & ~BIT(0),
4055 .mask = GENMASK(7, 0) & ~BIT(1),
4061 .mask = GENMASK(7, 0) & ~BIT(2),
4067 .mask = GENMASK(7, 0) & ~BIT(3),
4073 .mask = GENMASK(7, 0) & ~BIT(5),
4079 .mask = GENMASK(7, 0) & ~BIT(0),
4085 .mask = GENMASK(7, 0) & ~BIT(2),
4091 .mask = GENMASK(7, 0) & ~BIT(3),
4097 .mask = GENMASK(7, 0) & ~BIT(4),
4103 .mask = GENMASK(7, 0) & ~BIT(5),
4109 .mask = GENMASK(7, 0) & ~BIT(7),
4115 .mask = GENMASK(7, 0) & ~BIT(0),
4121 .mask = GENMASK(7, 0) & ~BIT(2),
4127 .mask = GENMASK(7, 0) & ~BIT(3),
4133 .mask = GENMASK(7, 0) & ~BIT(4),
4139 .mask = GENMASK(7, 0) & ~BIT(5),
4145 .mask = GENMASK(7, 0) & ~BIT(7),
4151 .mask = GENMASK(7, 0) & ~BIT(4),
4157 .mask = GENMASK(7, 0) & ~BIT(5),
4163 .mask = GENMASK(7, 0) & ~BIT(6),
4169 .mask = GENMASK(7, 0) & ~BIT(7),
4176 .bit = 5,
4182 .mask = GENMASK(7, 0) & ~BIT(3),
4188 .mask = GENMASK(7, 0) & ~BIT(4),
4194 .mask = GENMASK(7, 0) & ~BIT(5),
4200 .mask = GENMASK(7, 0) & ~BIT(0),
4206 .mask = GENMASK(7, 0) & ~BIT(1),
4212 .mask = GENMASK(7, 0) & ~BIT(2),
4218 .mask = GENMASK(7, 0) & ~BIT(3),
4224 .mask = GENMASK(7, 0) & ~BIT(4),
4230 .mask = GENMASK(7, 0) & ~BIT(5),
4236 .mask = GENMASK(7, 0) & ~BIT(6),
4242 .mask = GENMASK(7, 0) & ~BIT(7),
4248 .mask = GENMASK(7, 0) & ~BIT(0),
4254 .mask = GENMASK(7, 0) & ~BIT(1),
4260 .mask = GENMASK(7, 0) & ~BIT(2),
4266 .mask = GENMASK(7, 0) & ~BIT(3),
4272 .mask = GENMASK(7, 0) & ~BIT(4),
4278 .mask = GENMASK(7, 0) & ~BIT(5),
4284 .mask = GENMASK(7, 0) & ~BIT(6),
4290 .mask = GENMASK(7, 0) & ~BIT(7),
4297 .bit = 1,
4303 .mask = GENMASK(7, 0) & ~BIT(5),
4309 .mask = GENMASK(7, 0) & ~BIT(5),
4316 .bit = 1,
4322 .bit = GENMASK(7, 0),
4328 .mask = GENMASK(7, 0) & ~BIT(0),
4334 .mask = GENMASK(7, 0) & ~BIT(1),
4340 .mask = GENMASK(7, 0) & ~BIT(2),
4346 .mask = GENMASK(7, 0) & ~BIT(3),
4352 .mask = GENMASK(7, 0) & ~BIT(4),
4358 .mask = GENMASK(7, 0) & ~BIT(5),
4364 .mask = GENMASK(7, 0) & ~BIT(6),
4370 .mask = GENMASK(7, 0) & ~BIT(7),
4376 .bit = GENMASK(7, 0),
4382 .bit = GENMASK(7, 0),
4388 .bit = GENMASK(7, 0),
4394 .bit = GENMASK(7, 0),
4409 .bit = GENMASK(7, 0),
4415 .bit = GENMASK(15, 0),
4422 .bit = GENMASK(7, 0),
4428 .mask = GENMASK(7, 0) & ~BIT(2),
4434 .mask = GENMASK(7, 0) & ~BIT(4),
4440 .mask = GENMASK(7, 0) & ~BIT(3),
4446 .mask = GENMASK(7, 0) & ~BIT(4),
4452 .mask = GENMASK(7, 0) & ~BIT(5),
4458 .mask = GENMASK(7, 0) & ~BIT(6),
4464 .mask = GENMASK(7, 0) & ~BIT(0),
4470 .mask = GENMASK(7, 0) & ~BIT(1),
4476 .mask = GENMASK(7, 0) & ~BIT(2),
4482 .mask = GENMASK(7, 0) & ~BIT(3),
4488 .mask = GENMASK(7, 0) & ~BIT(5),
4494 .mask = GENMASK(7, 0) & ~BIT(6),
4500 .mask = GENMASK(7, 0) & ~BIT(7),
4506 .mask = GENMASK(7, 0) & ~BIT(2),
4512 .mask = GENMASK(7, 0) & ~BIT(3),
4518 .mask = GENMASK(7, 0) & ~BIT(0),
4524 .mask = GENMASK(7, 0) & ~BIT(4),
4530 .mask = GENMASK(7, 0) & ~BIT(6),
4536 .mask = GENMASK(7, 0) & ~BIT(4),
4542 .mask = GENMASK(7, 0) & ~BIT(5),
4548 .mask = GENMASK(7, 0) & ~BIT(6),
4554 .mask = GENMASK(7, 0) & ~BIT(7),
4561 .bit = 5,
4567 .mask = GENMASK(7, 0) & ~BIT(3),
4573 .mask = GENMASK(7, 0) & ~BIT(4),
4579 .mask = GENMASK(7, 0) & ~BIT(0),
4585 .bit = GENMASK(7, 0),
4591 .bit = GENMASK(7, 0),
4597 .bit = GENMASK(7, 0),
4603 .bit = GENMASK(7, 0),
4634 .mask = GENMASK(7, 0),
4636 .bit = BIT(0),
4643 .mask = GENMASK(7, 0),
4645 .bit = BIT(1),
4651 .mask = GENMASK(7, 0),
4653 .bit = BIT(2),
4659 .mask = GENMASK(7, 0),
4661 .bit = BIT(3),
4667 .mask = GENMASK(7, 0),
4669 .bit = BIT(4),
4675 .mask = GENMASK(7, 0),
4677 .bit = BIT(5),
4683 .mask = GENMASK(7, 0),
4685 .bit = BIT(6),
4691 .mask = GENMASK(7, 0),
4693 .bit = BIT(7),
4699 .mask = GENMASK(7, 0),
4701 .bit = BIT(0),
4707 .mask = GENMASK(7, 0),
4709 .bit = BIT(1),
4715 .mask = GENMASK(7, 0),
4717 .bit = BIT(2),
4723 .mask = GENMASK(7, 0),
4725 .bit = BIT(3),
4731 .mask = GENMASK(7, 0),
4733 .bit = BIT(4),
4738 .mask = GENMASK(7, 0),
4740 .bit = BIT(5),
4762 .bit = 0,
4774 .bit = 0,
4779 .mask = GENMASK(7, 0) & ~BIT(6),
4780 .bit = 6,
4789 .bit = 4,
4801 .bit = 1,
4810 .identity = "mlx-wdt-main",
4816 .identity = "mlx-wdt-aux",
4828 .bit = 0,
4845 .bit = 0,
4850 .mask = GENMASK(7, 0) & ~BIT(6),
4851 .bit = 6,
4860 .bit = 4,
4877 .bit = 4,
4886 .identity = "mlx-wdt-main",
4892 .identity = "mlx-wdt-aux",
4897 * Can be on all systems. It's differentiated by WD capability bit.
4906 .bit = 0,
4923 .bit = 0,
4928 .mask = GENMASK(7, 0) & ~BIT(6),
4929 .bit = 6,
4938 .bit = 4,
4955 .bit = 4,
4964 .identity = "mlx-wdt-main",
4970 .identity = "mlx-wdt-aux",
5446 *val = ioread8(ctx->base + reg); in mlxplat_mlxcpld_reg_read()
5455 iowrite8(val, ctx->base + reg); in mlxplat_mlxcpld_reg_write()
5544 [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"),
5566 ret = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, ®val); in mlxplat_reboot_notifier()
5569 regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, in mlxplat_reboot_notifier()
5586 regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, MLXPLAT_CPLD_HALT_MASK); in mlxplat_poweroff()
5592 mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, -1, in mlxplat_register_platform_device()
5614 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_default_matched()
5615 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_default_matched()
5637 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_default_wc_matched()
5638 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_default_wc_matched()
5660 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_default_eth_wc_blade_matched()
5661 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_default_eth_wc_blade_matched()
5685 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_msn21xx_matched()
5686 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_msn21xx_matched()
5708 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_msn274x_matched()
5709 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_msn274x_matched()
5731 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_msn201x_matched()
5732 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_msn201x_matched()
5754 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_qmb7xx_matched()
5755 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_qmb7xx_matched()
5780 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; in mlxplat_dmi_comex_matched()
5805 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_ng400_matched()
5806 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_ng400_matched()
5826 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR; in mlxplat_dmi_modular_matched()
5846 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_chassis_blade_matched()
5847 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_chassis_blade_matched()
5868 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_rack_switch_matched()
5869 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_rack_switch_matched()
5889 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_ng800_matched()
5890 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_ng800_matched()
5910 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_l1_switch_matched()
5911 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_l1_switch_matched()
6124 return -ENODEV; in mlxplat_mlxcpld_verify_bus_topology()
6129 shift = *nr - mlxplat_mux_data[i].parent; in mlxplat_mlxcpld_verify_bus_topology()
6135 mlxplat_hotplug->shift_nr = shift; in mlxplat_mlxcpld_verify_bus_topology()
6166 mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev, in mlxplat_lpc_cpld_device_init()
6169 err = -ENOMEM; in mlxplat_lpc_cpld_device_init()
6196 return -ENODEV; in mlxplat_pci_fpga_device_init()
6200 dev_err(&pci_dev->dev, "pci_enable_device failed with error %d\n", err); in mlxplat_pci_fpga_device_init()
6206 dev_err(&pci_dev->dev, "pci_request_regions failed with error %d\n", err); in mlxplat_pci_fpga_device_init()
6210 err = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(64)); in mlxplat_pci_fpga_device_init()
6212 err = dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32)); in mlxplat_pci_fpga_device_init()
6214 dev_err(&pci_dev->dev, "dma_set_mask failed with error %d\n", err); in mlxplat_pci_fpga_device_init()
6221 pci_mem_addr = devm_ioremap(&pci_dev->dev, pci_resource_start(pci_dev, 0), in mlxplat_pci_fpga_device_init()
6224 dev_err(&mlxplat_dev->dev, "ioremap failed\n"); in mlxplat_pci_fpga_device_init()
6225 err = -EIO; in mlxplat_pci_fpga_device_init()
6301 if (err == -ENODEV) in mlxplat_logicdev_init()
6321 mlxplat_hotplug->regmap = priv->regmap; in mlxplat_platdevs_init()
6322 if (priv->irq_fpga) in mlxplat_platdevs_init()
6323 mlxplat_hotplug->irq = priv->irq_fpga; in mlxplat_platdevs_init()
6324 priv->pdev_hotplug = in mlxplat_platdevs_init()
6325 platform_device_register_resndata(&mlxplat_dev->dev, in mlxplat_platdevs_init()
6326 "mlxreg-hotplug", PLATFORM_DEVID_NONE, in mlxplat_platdevs_init()
6327 priv->hotplug_resources, in mlxplat_platdevs_init()
6328 priv->hotplug_resources_size, in mlxplat_platdevs_init()
6330 if (IS_ERR(priv->pdev_hotplug)) { in mlxplat_platdevs_init()
6331 err = PTR_ERR(priv->pdev_hotplug); in mlxplat_platdevs_init()
6338 mlxplat_led->regmap = priv->regmap; in mlxplat_platdevs_init()
6339 priv->pdev_led = in mlxplat_platdevs_init()
6340 platform_device_register_resndata(&mlxplat_dev->dev, "leds-mlxreg", in mlxplat_platdevs_init()
6343 if (IS_ERR(priv->pdev_led)) { in mlxplat_platdevs_init()
6344 err = PTR_ERR(priv->pdev_led); in mlxplat_platdevs_init()
6351 mlxplat_regs_io->regmap = priv->regmap; in mlxplat_platdevs_init()
6352 priv->pdev_io_regs = platform_device_register_resndata(&mlxplat_dev->dev, in mlxplat_platdevs_init()
6353 "mlxreg-io", in mlxplat_platdevs_init()
6357 if (IS_ERR(priv->pdev_io_regs)) { in mlxplat_platdevs_init()
6358 err = PTR_ERR(priv->pdev_io_regs); in mlxplat_platdevs_init()
6365 mlxplat_fan->regmap = priv->regmap; in mlxplat_platdevs_init()
6366 priv->pdev_fan = platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-fan", in mlxplat_platdevs_init()
6370 if (IS_ERR(priv->pdev_fan)) { in mlxplat_platdevs_init()
6371 err = PTR_ERR(priv->pdev_fan); in mlxplat_platdevs_init()
6377 err = mlxplat_mlxcpld_check_wd_capability(priv->regmap); in mlxplat_platdevs_init()
6382 mlxplat_wd_data[i]->regmap = priv->regmap; in mlxplat_platdevs_init()
6383 priv->pdev_wd[i] = in mlxplat_platdevs_init()
6384 platform_device_register_resndata(&mlxplat_dev->dev, "mlx-wdt", i, in mlxplat_platdevs_init()
6387 if (IS_ERR(priv->pdev_wd[i])) { in mlxplat_platdevs_init()
6388 err = PTR_ERR(priv->pdev_wd[i]); in mlxplat_platdevs_init()
6397 while (--i >= 0) in mlxplat_platdevs_init()
6398 platform_device_unregister(priv->pdev_wd[i]); in mlxplat_platdevs_init()
6401 platform_device_unregister(priv->pdev_io_regs); in mlxplat_platdevs_init()
6404 platform_device_unregister(priv->pdev_led); in mlxplat_platdevs_init()
6407 platform_device_unregister(priv->pdev_hotplug); in mlxplat_platdevs_init()
6416 for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--) in mlxplat_platdevs_exit()
6417 platform_device_unregister(priv->pdev_wd[i]); in mlxplat_platdevs_exit()
6418 if (priv->pdev_fan) in mlxplat_platdevs_exit()
6419 platform_device_unregister(priv->pdev_fan); in mlxplat_platdevs_exit()
6420 if (priv->pdev_io_regs) in mlxplat_platdevs_exit()
6421 platform_device_unregister(priv->pdev_io_regs); in mlxplat_platdevs_exit()
6422 if (priv->pdev_led) in mlxplat_platdevs_exit()
6423 platform_device_unregister(priv->pdev_led); in mlxplat_platdevs_exit()
6424 if (priv->pdev_hotplug) in mlxplat_platdevs_exit()
6425 platform_device_unregister(priv->pdev_hotplug); in mlxplat_platdevs_exit()
6441 if (!priv->pdev_i2c) { in mlxplat_i2c_mux_topology_init()
6442 priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_NOTIFIED; in mlxplat_i2c_mux_topology_init()
6446 priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED; in mlxplat_i2c_mux_topology_init()
6448 priv->pdev_mux[i] = platform_device_register_resndata(&priv->pdev_i2c->dev, in mlxplat_i2c_mux_topology_init()
6449 "i2c-mux-reg", i, NULL, 0, in mlxplat_i2c_mux_topology_init()
6452 if (IS_ERR(priv->pdev_mux[i])) { in mlxplat_i2c_mux_topology_init()
6453 err = PTR_ERR(priv->pdev_mux[i]); in mlxplat_i2c_mux_topology_init()
6461 while (--i >= 0) in mlxplat_i2c_mux_topology_init()
6462 platform_device_unregister(priv->pdev_mux[i]); in mlxplat_i2c_mux_topology_init()
6470 for (i = mlxplat_mux_num - 1; i >= 0 ; i--) { in mlxplat_i2c_mux_topology_exit()
6471 if (priv->pdev_mux[i]) in mlxplat_i2c_mux_topology_exit()
6472 platform_device_unregister(priv->pdev_mux[i]); in mlxplat_i2c_mux_topology_exit()
6494 nr = (nr == mlxplat_max_adap_num) ? -1 : nr; in mlxplat_i2c_main_init()
6495 mlxplat_i2c->regmap = priv->regmap; in mlxplat_i2c_main_init()
6496 mlxplat_i2c->handle = priv; in mlxplat_i2c_main_init()
6498 /* Set mapped base address of I2C-LPC bridge over PCIe */ in mlxplat_i2c_main_init()
6500 mlxplat_i2c->addr = i2c_bridge_addr; in mlxplat_i2c_main_init()
6501 priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld", in mlxplat_i2c_main_init()
6502 nr, priv->hotplug_resources, in mlxplat_i2c_main_init()
6503 priv->hotplug_resources_size, in mlxplat_i2c_main_init()
6505 if (IS_ERR(priv->pdev_i2c)) { in mlxplat_i2c_main_init()
6506 err = PTR_ERR(priv->pdev_i2c); in mlxplat_i2c_main_init()
6510 if (priv->i2c_main_init_status == MLXPLAT_I2C_MAIN_BUS_NOTIFIED) { in mlxplat_i2c_main_init()
6519 platform_device_unregister(priv->pdev_i2c); in mlxplat_i2c_main_init()
6529 if (priv->pdev_i2c) in mlxplat_i2c_main_exit()
6530 platform_device_unregister(priv->pdev_i2c); in mlxplat_i2c_main_exit()
6541 acpi_dev = ACPI_COMPANION(&pdev->dev); in mlxplat_probe()
6545 return -ENODEV; in mlxplat_probe()
6553 priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv), in mlxplat_probe()
6556 err = -ENOMEM; in mlxplat_probe()
6560 priv->hotplug_resources = hotplug_resources; in mlxplat_probe()
6561 priv->hotplug_resources_size = hotplug_resources_size; in mlxplat_probe()
6562 priv->irq_fpga = irq_fpga; in mlxplat_probe()
6567 priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL, in mlxplat_probe()
6570 if (IS_ERR(priv->regmap)) { in mlxplat_probe()
6571 err = PTR_ERR(priv->regmap); in mlxplat_probe()
6576 for (i = 0; i < mlxplat_regmap_config->num_reg_defaults; i++) { in mlxplat_probe()
6577 err = regmap_write(priv->regmap, in mlxplat_probe()
6578 mlxplat_regmap_config->reg_defaults[i].reg, in mlxplat_probe()
6579 mlxplat_regmap_config->reg_defaults[i].def); in mlxplat_probe()
6589 regcache_mark_dirty(priv->regmap); in mlxplat_probe()
6590 err = regcache_sync(priv->regmap); in mlxplat_probe()
6646 return -ENODEV; in mlxplat_init()