Lines Matching +full:pins +full:- +full:are +full:- +full:numbered

1 /* SPDX-License-Identifier: GPL-2.0-only */
47 	/* argument: Integer, range is HW-dependant */
49 	/* argument: Integer, range is HW-dependant */
51 	/* argument: Integer, range is HW-dependant */
53 	/* argument: Integer, range is HW-dependant */
55 	/* argument: Integer, range is HW-dependant */
75  * struct tegra_function - Tegra pinctrl mux function
87  * struct tegra_pingroup - Tegra pin group
89  * @pins		An array of pin IDs included in this pin group.
90  * @npins		The number of entries in @pins.
97  * @pupd_reg:		Pull-up/down register offset.
98  * @pupd_bank:		Pull-up/down register bank.
99  * @pupd_bit:		Pull-up/down register bit.
100  * @tri_reg:		Tri-state register offset.
101  * @tri_bank:		Tri-state register bank.
102  * @tri_bit:		Tri-state register bit.
103  * @einput_bit:		Enable-input register bit.
104  * @odrain_bit:		Open-drain register bit.
128  * -1 in a *_reg field means that feature is unsupported for this group.
129  * *_bank and *_reg values are irrelevant when *_reg is -1.
130  * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature.
132  * A representation of a group of pins (possibly just one pin) in the Tegra
135  * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
141 	const unsigned *pins;  member
178  * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration
179  * @ngpios:	The number of GPIO pins the pin controller HW affects.
180  * @pins:	An array describing all pins the pin controller affects.
181  *		All pins which are also GPIOs must be listed first within the
182  *		array, and be numbered identically to the GPIO controller's
184  * @npins:	The numbmer of entries in @pins.
193 	const struct pinctrl_pin_desc *pins;  member