Lines Matching +full:gpio +full:- +full:bank +full:- +full:widths
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
22 #include <linux/gpio/driver.h>
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
70 * enum pud_index - Possible index values to access the pud_val array.
84 * enum eint_type - possible external interrupt types.
85 * @EINT_TYPE_NONE: bank does not support external interrupts
86 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
87 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
88 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
90 * Samsung GPIO controller groups all the available pins into banks. The pins
91 * in a pin bank can support external gpio interrupts or external wakeup
93 * difference between external gpio and external wakeup interrupts is that
104 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
125 * struct samsung_pin_bank_type: pin bank type description
126 * @fld_width: widths of configuration bitfields (0 if unavailable)
135 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
136 * @type: type of the bank (register offsets and bitfield widths)
137 * @pctl_offset: starting offset of the pin-bank registers.
138 * @pctl_res_idx: index of base address for pin-bank registers.
139 * @nr_pins: number of pins included in this bank.
141 * @eint_type: type of the external interrupt supported by the bank.
143 * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
144 * @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank.
145 * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
146 * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
147 * @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset.
148 * @name: name to be prefixed for each pin in this pin bank.
167 * struct samsung_pin_bank: represent a controller pin-bank.
168 * @type: type of the bank (register offsets and bitfield widths)
169 * @pctl_base: base address of the pin-bank registers
170 * @pctl_offset: starting offset of the pin-bank registers.
171 * @nr_pins: number of pins included in this bank.
172 * @eint_base: base address of the pin-bank EINT registers.
174 * @eint_type: type of the external interrupt supported by the bank.
176 * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
177 * @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank.
178 * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
179 * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
180 * @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset.
181 * @name: name to be prefixed for each pin in this pin bank.
182 * @id: id of the bank, propagated to the pin range.
183 * @pin_base: starting pin number of the bank.
184 * @soc_priv: per-bank private data for SoC-specific code.
185 * @of_node: OF node of the bank.
187 * @irq_domain: IRQ domain of the bank.
188 * @gpio_chip: GPIO chip of the bank.
189 * @grange: linux gpio pin range supported by this bank.
190 * @irq_chip: link to irq chip for external gpio and wakeup interrupts.
191 * @slock: spinlock protecting bank registers
225 * struct samsung_retention_data: runtime pin-bank retention control data.
229 * @refcnt: atomic counter if retention control affects more than one bank.
245 * struct samsung_retention_data: represent a pin-bank retention control data.
249 * @refcnt: atomic counter if retention control affects more than one bank.
267 * @eint_gpio_init: platform specific callback to setup the external gpio
296 * to each bank samsung_pin_bank->pctl_base and used on legacy
300 * @irq: interrpt number used by the controller to notify gpio interrupts.