Lines Matching +full:controller +full:- +full:specific

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25  * enum pincfg_type - possible pin configuration types supported.
46  * packed together into a 16-bits. The upper 8-bits represent the configuration
47  * type and the lower 8-bits hold the value of the configuration type.
70  * enum pud_index - Possible index values to access the pud_val array.
84  * enum eint_type - possible external interrupt types.
90  * Samsung GPIO controller groups all the available pins into banks. The pins
104 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
135  * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
137  * @pctl_offset: starting offset of the pin-bank registers.
138  * @pctl_res_idx: index of base address for pin-bank registers.
143  * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
144  * @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank.
145  * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
146  * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
147  * @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset.
167  * struct samsung_pin_bank: represent a controller pin-bank.
169  * @pctl_base: base address of the pin-bank registers
170  * @pctl_offset: starting offset of the pin-bank registers.
172  * @eint_base: base address of the pin-bank EINT registers.
176  * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
177  * @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank.
178  * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
179  * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
180  * @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset.
184  * @soc_priv: per-bank private data for SoC-specific code.
186  * @drvdata: link to controller driver data
225  * struct samsung_retention_data: runtime pin-bank retention control data.
231  * @enable: platform specific callback to enter retention mode.
232  * @disable: platform specific callback to exit retention mode.
245  * struct samsung_retention_data: represent a pin-bank retention control data.
250  * @init: platform specific callback to initialize retention control.
262  * struct samsung_pin_ctrl: represent a pin controller.
263  * @pin_banks: list of pin banks included in this controller.
267  * @eint_gpio_init: platform specific callback to setup the external gpio
268  *	interrupts for the controller.
269  * @eint_wkup_init: platform specific callback to setup the external wakeup
270  *	interrupts for the controller.
271  * @suspend: platform specific suspend callback, executed during pin controller
273  * @resume: platform specific resume callback, executed during pin controller
295  * @virt_base: register base address of the controller; this will be equal
296  *             to each bank samsung_pin_bank->pctl_base and used on legacy
299  * @dev: device instance representing the controller.
300  * @irq: interrpt number used by the controller to notify gpio interrupts.
302  * @ctrl: pin controller instance managed by the driver.
303  * @pctl: pin controller descriptor registered with the pinctrl subsystem.
309  * @nr_pins: number of pins supported by the controller.
311  * @suspend: platform specific suspend callback, executed during pin controller
313  * @resume: platform specific resume callback, executed during pin controller
343  * struct samsung_pinctrl_of_match_data: OF match device specific configuration data.
344  * @ctrl: array of pin controller data.
379 /* list of all exported SoC specific data */