Lines Matching +full:ssbi +full:- +full:gpio
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/gpio/driver.h>
18 #include <linux/pinctrl/pinconf-generic.h>
23 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
26 #include "../pinctrl-utils.h"
45 /* GPIO registers */
60 * struct pm8xxx_pin_data - dynamic configuration for a pin
65 * @open_drain: output buffer configured as open-drain (vs push-pull)
70 * @output_strength: selector of output-strength
100 {"qcom,drive-strength", PM8XXX_QCOM_DRIVE_STRENGH, 0},
101 {"qcom,pull-up-strength", PM8XXX_QCOM_PULL_UP_STRENGTH, 0},
106 PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true),
134 ret = regmap_write(pctrl->regmap, pin->reg, val); in pm8xxx_read_bank()
136 dev_err(pctrl->dev, "failed to select bank %d\n", bank); in pm8xxx_read_bank()
140 ret = regmap_read(pctrl->regmap, pin->reg, &val); in pm8xxx_read_bank()
142 dev_err(pctrl->dev, "failed to read register %d\n", bank); in pm8xxx_read_bank()
159 ret = regmap_write(pctrl->regmap, pin->reg, val); in pm8xxx_write_bank()
161 dev_err(pctrl->dev, "failed to write register\n"); in pm8xxx_write_bank()
170 return pctrl->npins; in pm8xxx_get_groups_count()
187 *pins = &pctrl->desc.pins[group].number; in pm8xxx_get_group_pins()
220 *num_groups = pctrl->npins; in pm8xxx_get_function_groups()
229 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data; in pm8xxx_pinmux_set_mux()
232 pin->function = function; in pm8xxx_pinmux_set_mux()
233 val = pin->function << 1; in pm8xxx_pinmux_set_mux()
252 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_pin_config_get()
258 if (pin->bias != PM8XXX_GPIO_BIAS_NP) in pm8xxx_pin_config_get()
259 return -EINVAL; in pm8xxx_pin_config_get()
263 if (pin->bias != PM8XXX_GPIO_BIAS_PD) in pm8xxx_pin_config_get()
264 return -EINVAL; in pm8xxx_pin_config_get()
268 if (pin->bias > PM8XXX_GPIO_BIAS_PU_1P5_30) in pm8xxx_pin_config_get()
269 return -EINVAL; in pm8xxx_pin_config_get()
273 arg = pin->pull_up_strength; in pm8xxx_pin_config_get()
276 if (!pin->disable) in pm8xxx_pin_config_get()
277 return -EINVAL; in pm8xxx_pin_config_get()
281 if (pin->mode != PM8XXX_GPIO_MODE_INPUT) in pm8xxx_pin_config_get()
282 return -EINVAL; in pm8xxx_pin_config_get()
286 if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT) in pm8xxx_pin_config_get()
287 arg = pin->output_value; in pm8xxx_pin_config_get()
292 arg = pin->power_source; in pm8xxx_pin_config_get()
295 arg = pin->output_strength; in pm8xxx_pin_config_get()
298 if (pin->open_drain) in pm8xxx_pin_config_get()
299 return -EINVAL; in pm8xxx_pin_config_get()
303 if (!pin->open_drain) in pm8xxx_pin_config_get()
304 return -EINVAL; in pm8xxx_pin_config_get()
308 return -EINVAL; in pm8xxx_pin_config_get()
322 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_pin_config_set()
335 pin->bias = PM8XXX_GPIO_BIAS_NP; in pm8xxx_pin_config_set()
337 pin->disable = 0; in pm8xxx_pin_config_set()
341 pin->bias = PM8XXX_GPIO_BIAS_PD; in pm8xxx_pin_config_set()
343 pin->disable = 0; in pm8xxx_pin_config_set()
348 dev_err(pctrl->dev, "invalid pull-up strength\n"); in pm8xxx_pin_config_set()
349 return -EINVAL; in pm8xxx_pin_config_set()
351 pin->pull_up_strength = arg; in pm8xxx_pin_config_set()
354 pin->bias = pin->pull_up_strength; in pm8xxx_pin_config_set()
356 pin->disable = 0; in pm8xxx_pin_config_set()
360 pin->disable = 1; in pm8xxx_pin_config_set()
364 pin->mode = PM8XXX_GPIO_MODE_INPUT; in pm8xxx_pin_config_set()
368 pin->mode = PM8XXX_GPIO_MODE_OUTPUT; in pm8xxx_pin_config_set()
369 pin->output_value = !!arg; in pm8xxx_pin_config_set()
373 pin->power_source = arg; in pm8xxx_pin_config_set()
378 dev_err(pctrl->dev, "invalid drive strength\n"); in pm8xxx_pin_config_set()
379 return -EINVAL; in pm8xxx_pin_config_set()
381 pin->output_strength = arg; in pm8xxx_pin_config_set()
385 pin->open_drain = 0; in pm8xxx_pin_config_set()
389 pin->open_drain = 1; in pm8xxx_pin_config_set()
393 dev_err(pctrl->dev, in pm8xxx_pin_config_set()
396 return -EINVAL; in pm8xxx_pin_config_set()
401 val = pin->power_source << 1; in pm8xxx_pin_config_set()
407 val = pin->mode << 2; in pm8xxx_pin_config_set()
408 val |= pin->open_drain << 1; in pm8xxx_pin_config_set()
409 val |= pin->output_value; in pm8xxx_pin_config_set()
414 val = pin->bias << 1; in pm8xxx_pin_config_set()
419 val = pin->output_strength << 2; in pm8xxx_pin_config_set()
420 val |= pin->disable; in pm8xxx_pin_config_set()
425 val = pin->function << 1; in pm8xxx_pin_config_set()
431 if (!pin->inverted) in pm8xxx_pin_config_set()
457 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_gpio_direction_input()
460 pin->mode = PM8XXX_GPIO_MODE_INPUT; in pm8xxx_gpio_direction_input()
461 val = pin->mode << 2; in pm8xxx_gpio_direction_input()
473 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_gpio_direction_output()
476 pin->mode = PM8XXX_GPIO_MODE_OUTPUT; in pm8xxx_gpio_direction_output()
477 pin->output_value = !!value; in pm8xxx_gpio_direction_output()
479 val = pin->mode << 2; in pm8xxx_gpio_direction_output()
480 val |= pin->open_drain << 1; in pm8xxx_gpio_direction_output()
481 val |= pin->output_value; in pm8xxx_gpio_direction_output()
491 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_gpio_get()
495 if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) in pm8xxx_gpio_get()
496 return pin->output_value; in pm8xxx_gpio_get()
498 irq = chip->to_irq(chip, offset); in pm8xxx_gpio_get()
505 ret = -EINVAL; in pm8xxx_gpio_get()
513 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_gpio_set()
516 pin->output_value = !!value; in pm8xxx_gpio_set()
518 val = pin->mode << 2; in pm8xxx_gpio_set()
519 val |= pin->open_drain << 1; in pm8xxx_gpio_set()
520 val |= pin->output_value; in pm8xxx_gpio_set()
529 if (chip->of_gpio_n_cells < 2) in pm8xxx_gpio_of_xlate()
530 return -EINVAL; in pm8xxx_gpio_of_xlate()
533 *flags = gpio_desc->args[1]; in pm8xxx_gpio_of_xlate()
535 return gpio_desc->args[0] - PM8XXX_GPIO_PHYSICAL_OFFSET; in pm8xxx_gpio_of_xlate()
545 unsigned gpio) in pm8xxx_gpio_dbg_show_one() argument
548 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_gpio_dbg_show_one()
554 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", in pm8xxx_gpio_dbg_show_one()
555 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull" in pm8xxx_gpio_dbg_show_one()
558 "push-pull", "open-drain" in pm8xxx_gpio_dbg_show_one()
564 seq_printf(s, " gpio%-2d:", offset + PM8XXX_GPIO_PHYSICAL_OFFSET); in pm8xxx_gpio_dbg_show_one()
565 if (pin->disable) { in pm8xxx_gpio_dbg_show_one()
566 seq_puts(s, " ---"); in pm8xxx_gpio_dbg_show_one()
568 seq_printf(s, " %-4s", modes[pin->mode]); in pm8xxx_gpio_dbg_show_one()
569 seq_printf(s, " %-7s", pm8xxx_gpio_functions[pin->function]); in pm8xxx_gpio_dbg_show_one()
570 seq_printf(s, " VIN%d", pin->power_source); in pm8xxx_gpio_dbg_show_one()
571 seq_printf(s, " %-27s", biases[pin->bias]); in pm8xxx_gpio_dbg_show_one()
572 seq_printf(s, " %-10s", buffer_types[pin->open_drain]); in pm8xxx_gpio_dbg_show_one()
573 seq_printf(s, " %-4s", str_high_low(pin->output_value)); in pm8xxx_gpio_dbg_show_one()
574 seq_printf(s, " %-7s", strengths[pin->output_strength]); in pm8xxx_gpio_dbg_show_one()
575 if (pin->inverted) in pm8xxx_gpio_dbg_show_one()
582 unsigned gpio = chip->base; in pm8xxx_gpio_dbg_show() local
585 for (i = 0; i < chip->ngpio; i++, gpio++) { in pm8xxx_gpio_dbg_show()
586 pm8xxx_gpio_dbg_show_one(s, NULL, chip, i, gpio); in pm8xxx_gpio_dbg_show()
614 pin->power_source = (val >> 1) & 0x7; in pm8xxx_pin_populate()
620 pin->mode = (val >> 2) & 0x3; in pm8xxx_pin_populate()
621 pin->open_drain = !!(val & BIT(1)); in pm8xxx_pin_populate()
622 pin->output_value = val & BIT(0); in pm8xxx_pin_populate()
628 pin->bias = (val >> 1) & 0x7; in pm8xxx_pin_populate()
629 if (pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30) in pm8xxx_pin_populate()
630 pin->pull_up_strength = pin->bias; in pm8xxx_pin_populate()
632 pin->pull_up_strength = PM8XXX_GPIO_BIAS_PU_30; in pm8xxx_pin_populate()
638 pin->output_strength = (val >> 2) & 0x3; in pm8xxx_pin_populate()
639 pin->disable = val & BIT(0); in pm8xxx_pin_populate()
645 pin->function = (val >> 1) & 0x7; in pm8xxx_pin_populate()
651 pin->inverted = !(val & BIT(3)); in pm8xxx_pin_populate()
671 .name = "ssbi-gpio",
687 struct pm8xxx_gpio *pctrl = container_of(domain->host_data, in pm8xxx_domain_translate()
690 if (fwspec->param_count != 2 || fwspec->param[0] < 1 || in pm8xxx_domain_translate()
691 fwspec->param[0] > pctrl->chip.ngpio) in pm8xxx_domain_translate()
692 return -EINVAL; in pm8xxx_domain_translate()
694 *hwirq = fwspec->param[0] - PM8XXX_GPIO_PHYSICAL_OFFSET; in pm8xxx_domain_translate()
695 *type = fwspec->param[1]; in pm8xxx_domain_translate()
719 { .compatible = "qcom,pm8018-gpio", .data = (void *) 6 },
720 { .compatible = "qcom,pm8038-gpio", .data = (void *) 12 },
721 { .compatible = "qcom,pm8058-gpio", .data = (void *) 44 },
722 { .compatible = "qcom,pm8917-gpio", .data = (void *) 38 },
723 { .compatible = "qcom,pm8921-gpio", .data = (void *) 44 },
738 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in pm8xxx_gpio_probe()
740 return -ENOMEM; in pm8xxx_gpio_probe()
742 pctrl->dev = &pdev->dev; in pm8xxx_gpio_probe()
743 pctrl->npins = (uintptr_t) device_get_match_data(&pdev->dev); in pm8xxx_gpio_probe()
745 pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL); in pm8xxx_gpio_probe()
746 if (!pctrl->regmap) { in pm8xxx_gpio_probe()
747 dev_err(&pdev->dev, "parent regmap unavailable\n"); in pm8xxx_gpio_probe()
748 return -ENXIO; in pm8xxx_gpio_probe()
751 pctrl->desc = pm8xxx_pinctrl_desc; in pm8xxx_gpio_probe()
752 pctrl->desc.npins = pctrl->npins; in pm8xxx_gpio_probe()
754 pins = devm_kcalloc(&pdev->dev, in pm8xxx_gpio_probe()
755 pctrl->desc.npins, in pm8xxx_gpio_probe()
759 return -ENOMEM; in pm8xxx_gpio_probe()
761 pin_data = devm_kcalloc(&pdev->dev, in pm8xxx_gpio_probe()
762 pctrl->desc.npins, in pm8xxx_gpio_probe()
766 return -ENOMEM; in pm8xxx_gpio_probe()
768 for (i = 0; i < pctrl->desc.npins; i++) { in pm8xxx_gpio_probe()
779 pctrl->desc.pins = pins; in pm8xxx_gpio_probe()
781 pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_gpio_bindings); in pm8xxx_gpio_probe()
782 pctrl->desc.custom_params = pm8xxx_gpio_bindings; in pm8xxx_gpio_probe()
784 pctrl->desc.custom_conf_items = pm8xxx_conf_items; in pm8xxx_gpio_probe()
787 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in pm8xxx_gpio_probe()
788 if (IS_ERR(pctrl->pctrl)) { in pm8xxx_gpio_probe()
789 dev_err(&pdev->dev, "couldn't register pm8xxx gpio driver\n"); in pm8xxx_gpio_probe()
790 return PTR_ERR(pctrl->pctrl); in pm8xxx_gpio_probe()
793 pctrl->chip = pm8xxx_gpio_template; in pm8xxx_gpio_probe()
794 pctrl->chip.base = -1; in pm8xxx_gpio_probe()
795 pctrl->chip.parent = &pdev->dev; in pm8xxx_gpio_probe()
796 pctrl->chip.of_gpio_n_cells = 2; in pm8xxx_gpio_probe()
797 pctrl->chip.label = dev_name(pctrl->dev); in pm8xxx_gpio_probe()
798 pctrl->chip.ngpio = pctrl->npins; in pm8xxx_gpio_probe()
800 parent_node = of_irq_find_parent(pctrl->dev->of_node); in pm8xxx_gpio_probe()
802 return -ENXIO; in pm8xxx_gpio_probe()
807 return -ENXIO; in pm8xxx_gpio_probe()
809 girq = &pctrl->chip.irq; in pm8xxx_gpio_probe()
811 girq->default_type = IRQ_TYPE_NONE; in pm8xxx_gpio_probe()
812 girq->handler = handle_level_irq; in pm8xxx_gpio_probe()
813 girq->fwnode = dev_fwnode(pctrl->dev); in pm8xxx_gpio_probe()
814 girq->parent_domain = parent_domain; in pm8xxx_gpio_probe()
815 girq->child_to_parent_hwirq = pm8xxx_child_to_parent_hwirq; in pm8xxx_gpio_probe()
816 girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; in pm8xxx_gpio_probe()
817 girq->child_offset_to_irq = pm8xxx_child_offset_to_irq; in pm8xxx_gpio_probe()
818 girq->child_irq_domain_ops.translate = pm8xxx_domain_translate; in pm8xxx_gpio_probe()
820 ret = gpiochip_add_data(&pctrl->chip, pctrl); in pm8xxx_gpio_probe()
822 dev_err(&pdev->dev, "failed register gpiochip\n"); in pm8xxx_gpio_probe()
827 * For DeviceTree-supported systems, the gpio core checks the in pm8xxx_gpio_probe()
828 * pinctrl's device node for the "gpio-ranges" property. in pm8xxx_gpio_probe()
833 * files which don't set the "gpio-ranges" property or systems that in pm8xxx_gpio_probe()
836 if (!of_property_present(pctrl->dev->of_node, "gpio-ranges")) { in pm8xxx_gpio_probe()
837 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), in pm8xxx_gpio_probe()
838 0, 0, pctrl->chip.ngpio); in pm8xxx_gpio_probe()
840 dev_err(pctrl->dev, "failed to add pin range\n"); in pm8xxx_gpio_probe()
847 dev_dbg(&pdev->dev, "Qualcomm pm8xxx gpio driver probed\n"); in pm8xxx_gpio_probe()
852 gpiochip_remove(&pctrl->chip); in pm8xxx_gpio_probe()
861 gpiochip_remove(&pctrl->chip); in pm8xxx_gpio_remove()
866 .name = "qcom-ssbi-gpio",
876 MODULE_DESCRIPTION("Qualcomm PM8xxx GPIO driver");