44  * @pctrl:          pinctrl handle.
64 	struct pinctrl_dev *pctrl;  member
87 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
90 	return readl(pctrl->regs[g->tile] + g->name##_reg); \
92 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
95 	writel(val, pctrl->regs[g->tile] + g->name##_reg); \
104 static void msm_ack_intr_status(struct msm_pinctrl *pctrl,  in MSM_ACCESSOR()
109 	msm_writel_intr_status(val, pctrl, g);  in MSM_ACCESSOR()
114 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_get_groups_count()  local
116 	return pctrl->soc->ngroups;  in msm_get_groups_count()
122 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_get_group_name()  local
124 	return pctrl->soc->groups[group].grp.name;  in msm_get_group_name()
132 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_get_group_pins()  local
134 	*pins = pctrl->soc->groups[group].grp.pins;  in msm_get_group_pins()
135 	*num_pins = pctrl->soc->groups[group].grp.npins;  in msm_get_group_pins()
149 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_pinmux_request()  local
150 	struct gpio_chip *chip = &pctrl->chip;  in msm_pinmux_request()
157 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_get_functions_count()  local
159 	return pctrl->soc->nfunctions;  in msm_get_functions_count()
165 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_get_function_name()  local
167 	return pctrl->soc->functions[function].name;  in msm_get_function_name()
175 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_get_function_groups()  local
177 	*groups = pctrl->soc->functions[function].groups;  in msm_get_function_groups()
178 	*num_groups = pctrl->soc->functions[function].ngroups;  in msm_get_function_groups()
186 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_pinmux_set_mux()  local
187 	struct gpio_chip *gc = &pctrl->chip;  in msm_pinmux_set_mux()
190 	unsigned int gpio_func = pctrl->soc->gpio_func;  in msm_pinmux_set_mux()
191 	unsigned int egpio_func = pctrl->soc->egpio_func;  in msm_pinmux_set_mux()
197 	g = &pctrl->soc->groups[group];  in msm_pinmux_set_mux()
219 	    !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux))  in msm_pinmux_set_mux()
222 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_pinmux_set_mux()
224 	val = msm_readl_ctl(pctrl, g);  in msm_pinmux_set_mux()
233 	    !test_and_set_bit(group, pctrl->ever_gpio)) {  in msm_pinmux_set_mux()
234 		u32 io_val = msm_readl_io(pctrl, g);  in msm_pinmux_set_mux()
238 				msm_writel_io(io_val | BIT(g->out_bit), pctrl, g);  in msm_pinmux_set_mux()
241 				msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g);  in msm_pinmux_set_mux()
256 	msm_writel_ctl(val, pctrl, g);  in msm_pinmux_set_mux()
258 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_pinmux_set_mux()
261 	    test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) {  in msm_pinmux_set_mux()
266 		if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))  in msm_pinmux_set_mux()
269 			msm_ack_intr_status(pctrl, g);  in msm_pinmux_set_mux()
281 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_pinmux_request_gpio()  local
282 	const struct msm_pingroup *g = &pctrl->soc->groups[offset];  in msm_pinmux_request_gpio()
288 	return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset);  in msm_pinmux_request_gpio()
300 static int msm_config_reg(struct msm_pinctrl *pctrl,  in msm_config_reg()  argument
354 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_config_group_get()  local
363 	if (!gpiochip_line_is_valid(&pctrl->chip, group))  in msm_config_group_get()
366 	g = &pctrl->soc->groups[group];  in msm_config_group_get()
368 	ret = msm_config_reg(pctrl, g, param, &mask, &bit);  in msm_config_group_get()
372 	val = msm_readl_ctl(pctrl, g);  in msm_config_group_get()
388 		if (pctrl->soc->pull_no_keeper)  in msm_config_group_get()
396 		if (pctrl->soc->pull_no_keeper)  in msm_config_group_get()
419 		val = msm_readl_io(pctrl, g);  in msm_config_group_get()
441 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_config_group_set()  local
451 	g = &pctrl->soc->groups[group];  in msm_config_group_set()
457 		ret = msm_config_reg(pctrl, g, param, &mask, &bit);  in msm_config_group_set()
470 			if (pctrl->soc->pull_no_keeper)  in msm_config_group_set()
476 			if (pctrl->soc->pull_no_keeper)  in msm_config_group_set()
495 			raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_config_group_set()
496 			val = msm_readl_io(pctrl, g);  in msm_config_group_set()
501 			msm_writel_io(val, pctrl, g);  in msm_config_group_set()
502 			raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_config_group_set()
539 			dev_err(pctrl->dev, "Unsupported config parameter: %x\n",  in msm_config_group_set()
546 			dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);  in msm_config_group_set()
550 		raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_config_group_set()
551 		val = msm_readl_ctl(pctrl, g);  in msm_config_group_set()
554 		msm_writel_ctl(val, pctrl, g);  in msm_config_group_set()
555 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_config_group_set()
570 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);  in msm_gpio_direction_input()  local
574 	g = &pctrl->soc->groups[offset];  in msm_gpio_direction_input()
576 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_gpio_direction_input()
578 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_direction_input()
580 	msm_writel_ctl(val, pctrl, g);  in msm_gpio_direction_input()
582 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_gpio_direction_input()
590 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);  in msm_gpio_direction_output()  local
594 	g = &pctrl->soc->groups[offset];  in msm_gpio_direction_output()
596 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_gpio_direction_output()
598 	val = msm_readl_io(pctrl, g);  in msm_gpio_direction_output()
603 	msm_writel_io(val, pctrl, g);  in msm_gpio_direction_output()
605 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_direction_output()
607 	msm_writel_ctl(val, pctrl, g);  in msm_gpio_direction_output()
609 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_gpio_direction_output()
616 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);  in msm_gpio_get_direction()  local
620 	g = &pctrl->soc->groups[offset];  in msm_gpio_get_direction()
622 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_get_direction()
631 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);  in msm_gpio_get()  local
634 	g = &pctrl->soc->groups[offset];  in msm_gpio_get()
636 	val = msm_readl_io(pctrl, g);  in msm_gpio_get()
643 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);  in msm_gpio_set()  local
647 	g = &pctrl->soc->groups[offset];  in msm_gpio_set()
649 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_gpio_set()
651 	val = msm_readl_io(pctrl, g);  in msm_gpio_set()
656 	msm_writel_io(val, pctrl, g);  in msm_gpio_set()
658 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_gpio_set()
670 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);  in msm_gpio_dbg_show_one()  local
695 	g = &pctrl->soc->groups[offset];  in msm_gpio_dbg_show_one()
696 	ctl_reg = msm_readl_ctl(pctrl, g);  in msm_gpio_dbg_show_one()
697 	io_reg = msm_readl_io(pctrl, g);  in msm_gpio_dbg_show_one()
704 	if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present))  in msm_gpio_dbg_show_one()
720 	if (pctrl->soc->pull_no_keeper)  in msm_gpio_dbg_show_one()
744 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_init_valid_mask()  local
747 	const int *reserved = pctrl->soc->reserved_gpios;  in msm_gpio_init_valid_mask()
754 				dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");  in msm_gpio_init_valid_mask()
764 	len = ret = device_property_count_u16(pctrl->dev, "gpios");  in msm_gpio_init_valid_mask()
775 	ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);  in msm_gpio_init_valid_mask()
777 		dev_err(pctrl->dev, "could not read list of GPIOs\n");  in msm_gpio_init_valid_mask()
821 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,  in msm_gpio_update_dual_edge_pos()  argument
830 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
832 		pol = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_update_dual_edge_pos()
834 		msm_writel_intr_cfg(pol, pctrl, g);  in msm_gpio_update_dual_edge_pos()
836 		val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
837 		intstat = msm_readl_intr_status(pctrl, g);  in msm_gpio_update_dual_edge_pos()
841 	dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",  in msm_gpio_update_dual_edge_pos()
848 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_mask()  local
856 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs))  in msm_gpio_irq_mask()
859 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_mask()
861 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_gpio_irq_mask()
863 	val = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_mask()
888 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_mask()
890 	clear_bit(d->hwirq, pctrl->enabled_irqs);  in msm_gpio_irq_mask()
892 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_gpio_irq_mask()
898 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_unmask()  local
906 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs))  in msm_gpio_irq_unmask()
909 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_unmask()
911 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_gpio_irq_unmask()
913 	val = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_unmask()
916 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_unmask()
918 	set_bit(d->hwirq, pctrl->enabled_irqs);  in msm_gpio_irq_unmask()
920 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_gpio_irq_unmask()
926 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_enable()  local
933 	if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))  in msm_gpio_irq_enable()
940 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_disable()  local
945 	if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))  in msm_gpio_irq_disable()
963 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_update_dual_edge_parent()  local
964 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_update_dual_edge_parent()
970 	val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_parent()
983 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_parent()
994 	dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n");  in msm_gpio_update_dual_edge_parent()
1000 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_ack()  local
1004 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {  in msm_gpio_irq_ack()
1005 		if (test_bit(d->hwirq, pctrl->dual_edge_irqs))  in msm_gpio_irq_ack()
1010 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_ack()
1012 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_gpio_irq_ack()
1014 	msm_ack_intr_status(pctrl, g);  in msm_gpio_irq_ack()
1016 	if (test_bit(d->hwirq, pctrl->dual_edge_irqs))  in msm_gpio_irq_ack()
1017 		msm_gpio_update_dual_edge_pos(pctrl, g, d);  in msm_gpio_irq_ack()
1019 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_gpio_irq_ack()
1034 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_needs_dual_edge_parent_workaround()  local
1037 	       pctrl->soc->wakeirq_dual_edge_errata && d->parent_data &&  in msm_gpio_needs_dual_edge_parent_workaround()
1038 	       test_bit(d->hwirq, pctrl->skip_wake_irqs);  in msm_gpio_needs_dual_edge_parent_workaround()
1044 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_set_type()  local
1051 		set_bit(d->hwirq, pctrl->dual_edge_irqs);  in msm_gpio_irq_set_type()
1060 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {  in msm_gpio_irq_set_type()
1061 		clear_bit(d->hwirq, pctrl->dual_edge_irqs);  in msm_gpio_irq_set_type()
1066 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_set_type()
1068 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_gpio_irq_set_type()
1074 		set_bit(d->hwirq, pctrl->dual_edge_irqs);  in msm_gpio_irq_set_type()
1076 		clear_bit(d->hwirq, pctrl->dual_edge_irqs);  in msm_gpio_irq_set_type()
1085 	if (pctrl->intr_target_use_scm) {  in msm_gpio_irq_set_type()
1086 		u32 addr = pctrl->phys_base[0] + g->intr_target_reg;  in msm_gpio_irq_set_type()
1095 			dev_err(pctrl->dev,  in msm_gpio_irq_set_type()
1099 		val = msm_readl_intr_target(pctrl, g);  in msm_gpio_irq_set_type()
1102 		msm_writel_intr_target(val, pctrl, g);  in msm_gpio_irq_set_type()
1110 	val = oldval = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_set_type()
1158 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_set_type()
1168 		msm_ack_intr_status(pctrl, g);  in msm_gpio_irq_set_type()
1170 	if (test_bit(d->hwirq, pctrl->dual_edge_irqs))  in msm_gpio_irq_set_type()
1171 		msm_gpio_update_dual_edge_pos(pctrl, g, d);  in msm_gpio_irq_set_type()
1173 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_gpio_irq_set_type()
1186 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_set_wake()  local
1194 	if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))  in msm_gpio_irq_set_wake()
1197 	return irq_set_irq_wake(pctrl->irq, on);  in msm_gpio_irq_set_wake()
1203 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_reqres()  local
1204 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_reqres()
1211 	ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq);  in msm_gpio_irq_reqres()
1239 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) {  in msm_gpio_irq_reqres()
1242 		raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_gpio_irq_reqres()
1244 		intr_cfg = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_reqres()
1247 			msm_writel_intr_cfg(intr_cfg, pctrl, g);  in msm_gpio_irq_reqres()
1250 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_gpio_irq_reqres()
1262 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_relres()  local
1263 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_relres()
1267 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) {  in msm_gpio_irq_relres()
1270 		raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_gpio_irq_relres()
1272 		intr_cfg = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_relres()
1275 			msm_writel_intr_cfg(intr_cfg, pctrl, g);  in msm_gpio_irq_relres()
1278 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_gpio_irq_relres()
1289 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_set_affinity()  local
1291 	if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))  in msm_gpio_irq_set_affinity()
1300 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_set_vcpu_affinity()  local
1302 	if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))  in msm_gpio_irq_set_vcpu_affinity()
1312 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_handler()  local
1324 	for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {  in msm_gpio_irq_handler()
1325 		g = &pctrl->soc->groups[i];  in msm_gpio_irq_handler()
1326 		val = msm_readl_intr_status(pctrl, g);  in msm_gpio_irq_handler()
1346 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_wakeirq()  local
1353 	for (i = 0; i < pctrl->soc->nwakeirq_map; i++) {  in msm_gpio_wakeirq()
1354 		map = &pctrl->soc->wakeirq_map[i];  in msm_gpio_wakeirq()
1364 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)  in msm_gpio_needs_valid_mask()  argument
1366 	if (pctrl->soc->reserved_gpios)  in msm_gpio_needs_valid_mask()
1369 	return device_property_count_u16(pctrl->dev, "gpios") > 0;  in msm_gpio_needs_valid_mask()
1392 static int msm_gpio_init(struct msm_pinctrl *pctrl)  in msm_gpio_init()  argument
1397 	unsigned gpio, ngpio = pctrl->soc->ngpios;  in msm_gpio_init()
1404 	chip = &pctrl->chip;  in msm_gpio_init()
1407 	chip->label = dev_name(pctrl->dev);  in msm_gpio_init()
1408 	chip->parent = pctrl->dev;  in msm_gpio_init()
1410 	if (msm_gpio_needs_valid_mask(pctrl))  in msm_gpio_init()
1413 	np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0);  in msm_gpio_init()
1426 		for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) {  in msm_gpio_init()
1427 			gpio = pctrl->soc->wakeirq_map[i].gpio;  in msm_gpio_init()
1428 			set_bit(gpio, pctrl->skip_wake_irqs);  in msm_gpio_init()
1435 	girq->fwnode = dev_fwnode(pctrl->dev);  in msm_gpio_init()
1437 	girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),  in msm_gpio_init()
1443 	girq->parents[0] = pctrl->irq;  in msm_gpio_init()
1445 	ret = gpiochip_add_data(&pctrl->chip, pctrl);  in msm_gpio_init()
1447 		dev_err(pctrl->dev, "Failed register gpiochip\n");  in msm_gpio_init()
1461 	if (!of_property_present(pctrl->dev->of_node, "gpio-ranges")) {  in msm_gpio_init()
1462 		ret = gpiochip_add_pin_range(&pctrl->chip,  in msm_gpio_init()
1463 			dev_name(pctrl->dev), 0, 0, chip->ngpio);  in msm_gpio_init()
1465 			dev_err(pctrl->dev, "Failed to add pin range\n");  in msm_gpio_init()
1466 			gpiochip_remove(&pctrl->chip);  in msm_gpio_init()
1477 	struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);  in msm_ps_hold_restart()  local
1479 	writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);  in msm_ps_hold_restart()
1491 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)  in msm_pinctrl_setup_pm_reset()  argument
1494 	const struct pinfunction *func = pctrl->soc->functions;  in msm_pinctrl_setup_pm_reset()
1496 	for (i = 0; i < pctrl->soc->nfunctions; i++)  in msm_pinctrl_setup_pm_reset()
1498 			pctrl->restart_nb.notifier_call = msm_ps_hold_restart;  in msm_pinctrl_setup_pm_reset()
1499 			pctrl->restart_nb.priority = 128;  in msm_pinctrl_setup_pm_reset()
1500 			if (register_restart_handler(&pctrl->restart_nb))  in msm_pinctrl_setup_pm_reset()
1501 				dev_err(pctrl->dev,  in msm_pinctrl_setup_pm_reset()
1503 			poweroff_pctrl = pctrl;  in msm_pinctrl_setup_pm_reset()
1511 	struct msm_pinctrl *pctrl = dev_get_drvdata(dev);  in msm_pinctrl_suspend()  local
1513 	return pinctrl_force_sleep(pctrl->pctrl);  in msm_pinctrl_suspend()
1518 	struct msm_pinctrl *pctrl = dev_get_drvdata(dev);  in msm_pinctrl_resume()  local
1520 	return pinctrl_force_default(pctrl->pctrl);  in msm_pinctrl_resume()
1531 	struct msm_pinctrl *pctrl;  in msm_pinctrl_probe()  local
1536 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);  in msm_pinctrl_probe()
1537 	if (!pctrl)  in msm_pinctrl_probe()
1540 	pctrl->dev = &pdev->dev;  in msm_pinctrl_probe()
1541 	pctrl->soc = soc_data;  in msm_pinctrl_probe()
1542 	pctrl->chip = msm_gpio_template;  in msm_pinctrl_probe()
1543 	pctrl->intr_target_use_scm = of_device_is_compatible(  in msm_pinctrl_probe()
1544 					pctrl->dev->of_node,  in msm_pinctrl_probe()
1547 	raw_spin_lock_init(&pctrl->lock);  in msm_pinctrl_probe()
1553 			pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res);  in msm_pinctrl_probe()
1554 			if (IS_ERR(pctrl->regs[i]))  in msm_pinctrl_probe()
1555 				return PTR_ERR(pctrl->regs[i]);  in msm_pinctrl_probe()
1558 		pctrl->regs[0] = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in msm_pinctrl_probe()
1559 		if (IS_ERR(pctrl->regs[0]))  in msm_pinctrl_probe()
1560 			return PTR_ERR(pctrl->regs[0]);  in msm_pinctrl_probe()
1562 		pctrl->phys_base[0] = res->start;  in msm_pinctrl_probe()
1565 	msm_pinctrl_setup_pm_reset(pctrl);  in msm_pinctrl_probe()
1567 	pctrl->irq = platform_get_irq(pdev, 0);  in msm_pinctrl_probe()
1568 	if (pctrl->irq < 0)  in msm_pinctrl_probe()
1569 		return pctrl->irq;  in msm_pinctrl_probe()
1571 	pctrl->desc.owner = THIS_MODULE;  in msm_pinctrl_probe()
1572 	pctrl->desc.pctlops = &msm_pinctrl_ops;  in msm_pinctrl_probe()
1573 	pctrl->desc.pmxops = &msm_pinmux_ops;  in msm_pinctrl_probe()
1574 	pctrl->desc.confops = &msm_pinconf_ops;  in msm_pinctrl_probe()
1575 	pctrl->desc.name = dev_name(&pdev->dev);  in msm_pinctrl_probe()
1576 	pctrl->desc.pins = pctrl->soc->pins;  in msm_pinctrl_probe()
1577 	pctrl->desc.npins = pctrl->soc->npins;  in msm_pinctrl_probe()
1579 	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);  in msm_pinctrl_probe()
1580 	if (IS_ERR(pctrl->pctrl)) {  in msm_pinctrl_probe()
1582 		return PTR_ERR(pctrl->pctrl);  in msm_pinctrl_probe()
1585 	ret = msm_gpio_init(pctrl);  in msm_pinctrl_probe()
1589 	platform_set_drvdata(pdev, pctrl);  in msm_pinctrl_probe()
1599 	struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);  in msm_pinctrl_remove()  local
1601 	gpiochip_remove(&pctrl->chip);  in msm_pinctrl_remove()
1603 	unregister_restart_handler(&pctrl->restart_nb);  in msm_pinctrl_remove()