Lines Matching +full:- +full:g +full:-
1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <linux/pinctrl/pinconf-generic.h>
33 #include "../pinctrl-utils.h"
35 #include "pinctrl-msm.h"
42 * struct msm_pinctrl - state for a pinctrl-msm device
88 const struct msm_pingroup *g) \
90 return readl(pctrl->regs[g->tile] + g->name##_reg); \
93 const struct msm_pingroup *g) \
95 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
105 const struct msm_pingroup *g) in MSM_ACCESSOR()
107 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; in MSM_ACCESSOR()
109 msm_writel_intr_status(val, pctrl, g); in MSM_ACCESSOR()
116 return pctrl->soc->ngroups; in msm_get_groups_count()
124 return pctrl->soc->groups[group].grp.name; in msm_get_group_name()
134 *pins = pctrl->soc->groups[group].grp.pins; in msm_get_group_pins()
135 *num_pins = pctrl->soc->groups[group].grp.npins; in msm_get_group_pins()
150 struct gpio_chip *chip = &pctrl->chip; in msm_pinmux_request()
152 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL; in msm_pinmux_request()
159 return pctrl->soc->nfunctions; in msm_get_functions_count()
167 return pctrl->soc->functions[function].name; in msm_get_function_name()
177 *groups = pctrl->soc->functions[function].groups; in msm_get_function_groups()
178 *num_groups = pctrl->soc->functions[function].ngroups; in msm_get_function_groups()
187 struct gpio_chip *gc = &pctrl->chip; in msm_pinmux_set_mux()
188 unsigned int irq = irq_find_mapping(gc->irq.domain, group); in msm_pinmux_set_mux()
190 unsigned int gpio_func = pctrl->soc->gpio_func; in msm_pinmux_set_mux()
191 unsigned int egpio_func = pctrl->soc->egpio_func; in msm_pinmux_set_mux()
192 const struct msm_pingroup *g; in msm_pinmux_set_mux() local
197 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
198 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); in msm_pinmux_set_mux()
200 for (i = 0; i < g->nfuncs; i++) { in msm_pinmux_set_mux()
201 if (g->funcs[i] == function) in msm_pinmux_set_mux()
205 if (WARN_ON(i == g->nfuncs)) in msm_pinmux_set_mux()
206 return -EINVAL; in msm_pinmux_set_mux()
219 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux)) in msm_pinmux_set_mux()
222 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_pinmux_set_mux()
224 val = msm_readl_ctl(pctrl, g); in msm_pinmux_set_mux()
232 if (i == gpio_func && (val & BIT(g->oe_bit)) && in msm_pinmux_set_mux()
233 !test_and_set_bit(group, pctrl->ever_gpio)) { in msm_pinmux_set_mux()
234 u32 io_val = msm_readl_io(pctrl, g); in msm_pinmux_set_mux()
236 if (io_val & BIT(g->in_bit)) { in msm_pinmux_set_mux()
237 if (!(io_val & BIT(g->out_bit))) in msm_pinmux_set_mux()
238 msm_writel_io(io_val | BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
240 if (io_val & BIT(g->out_bit)) in msm_pinmux_set_mux()
241 msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
246 if (val & BIT(g->egpio_present)) in msm_pinmux_set_mux()
247 val &= ~BIT(g->egpio_enable); in msm_pinmux_set_mux()
250 val |= i << g->mux_bit; in msm_pinmux_set_mux()
252 if (egpio_func && val & BIT(g->egpio_present)) in msm_pinmux_set_mux()
253 val |= BIT(g->egpio_enable); in msm_pinmux_set_mux()
256 msm_writel_ctl(val, pctrl, g); in msm_pinmux_set_mux()
258 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_pinmux_set_mux()
261 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) { in msm_pinmux_set_mux()
266 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_pinmux_set_mux()
269 msm_ack_intr_status(pctrl, g); in msm_pinmux_set_mux()
282 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio() local
285 if (!g->nfuncs) in msm_pinmux_request_gpio()
288 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset); in msm_pinmux_request_gpio()
301 const struct msm_pingroup *g, in msm_config_reg() argument
311 *bit = g->pull_bit; in msm_config_reg()
313 if (g->i2c_pull_bit) in msm_config_reg()
314 *mask |= BIT(g->i2c_pull_bit) >> *bit; in msm_config_reg()
317 *bit = g->od_bit; in msm_config_reg()
321 *bit = g->drv_bit; in msm_config_reg()
327 *bit = g->oe_bit; in msm_config_reg()
331 return -ENOTSUPP; in msm_config_reg()
353 const struct msm_pingroup *g; in msm_config_group_get() local
363 if (!gpiochip_line_is_valid(&pctrl->chip, group)) in msm_config_group_get()
364 return -EINVAL; in msm_config_group_get()
366 g = &pctrl->soc->groups[group]; in msm_config_group_get()
368 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_get()
372 val = msm_readl_ctl(pctrl, g); in msm_config_group_get()
379 return -EINVAL; in msm_config_group_get()
384 return -EINVAL; in msm_config_group_get()
388 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
389 return -ENOTSUPP; in msm_config_group_get()
392 return -EINVAL; in msm_config_group_get()
396 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
398 else if (arg & BIT(g->i2c_pull_bit)) in msm_config_group_get()
403 return -EINVAL; in msm_config_group_get()
406 /* Pin is not open-drain */ in msm_config_group_get()
408 return -EINVAL; in msm_config_group_get()
417 return -EINVAL; in msm_config_group_get()
419 val = msm_readl_io(pctrl, g); in msm_config_group_get()
420 arg = !!(val & BIT(g->in_bit)); in msm_config_group_get()
424 return -EINVAL; in msm_config_group_get()
427 return -ENOTSUPP; in msm_config_group_get()
440 const struct msm_pingroup *g; in msm_config_group_set() local
451 g = &pctrl->soc->groups[group]; in msm_config_group_set()
457 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_set()
470 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
471 return -ENOTSUPP; in msm_config_group_set()
476 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
478 else if (g->i2c_pull_bit && arg == MSM_I2C_STRONG_PULL_UP) in msm_config_group_set()
479 arg = BIT(g->i2c_pull_bit) | MSM_PULL_UP; in msm_config_group_set()
489 arg = -1; in msm_config_group_set()
491 arg = (arg / 2) - 1; in msm_config_group_set()
495 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
496 val = msm_readl_io(pctrl, g); in msm_config_group_set()
498 val |= BIT(g->out_bit); in msm_config_group_set()
500 val &= ~BIT(g->out_bit); in msm_config_group_set()
501 msm_writel_io(val, pctrl, g); in msm_config_group_set()
502 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
510 * actually be a no-op. in msm_config_group_set()
522 * no-op. However, for historical reasons and to in msm_config_group_set()
528 * that "input-enable" and "input-disable" in a device in msm_config_group_set()
539 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", in msm_config_group_set()
541 return -EINVAL; in msm_config_group_set()
544 /* Range-check user-supplied value */ in msm_config_group_set()
546 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); in msm_config_group_set()
547 return -EINVAL; in msm_config_group_set()
550 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
551 val = msm_readl_ctl(pctrl, g); in msm_config_group_set()
554 msm_writel_ctl(val, pctrl, g); in msm_config_group_set()
555 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
569 const struct msm_pingroup *g; in msm_gpio_direction_input() local
574 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
576 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_input()
578 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_input()
579 val &= ~BIT(g->oe_bit); in msm_gpio_direction_input()
580 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_input()
582 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_input()
589 const struct msm_pingroup *g; in msm_gpio_direction_output() local
594 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
596 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_output()
598 val = msm_readl_io(pctrl, g); in msm_gpio_direction_output()
600 val |= BIT(g->out_bit); in msm_gpio_direction_output()
602 val &= ~BIT(g->out_bit); in msm_gpio_direction_output()
603 msm_writel_io(val, pctrl, g); in msm_gpio_direction_output()
605 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_output()
606 val |= BIT(g->oe_bit); in msm_gpio_direction_output()
607 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_output()
609 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_output()
617 const struct msm_pingroup *g; in msm_gpio_get_direction() local
620 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
622 val = msm_readl_ctl(pctrl, g); in msm_gpio_get_direction()
624 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT : in msm_gpio_get_direction()
630 const struct msm_pingroup *g; in msm_gpio_get() local
634 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
636 val = msm_readl_io(pctrl, g); in msm_gpio_get()
637 return !!(val & BIT(g->in_bit)); in msm_gpio_get()
642 const struct msm_pingroup *g; in msm_gpio_set() local
647 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
649 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_set()
651 val = msm_readl_io(pctrl, g); in msm_gpio_set()
653 val |= BIT(g->out_bit); in msm_gpio_set()
655 val &= ~BIT(g->out_bit); in msm_gpio_set()
656 msm_writel_io(val, pctrl, g); in msm_gpio_set()
658 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_set()
669 const struct msm_pingroup *g; in msm_gpio_dbg_show_one() local
695 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
696 ctl_reg = msm_readl_ctl(pctrl, g); in msm_gpio_dbg_show_one()
697 io_reg = msm_readl_io(pctrl, g); in msm_gpio_dbg_show_one()
699 is_out = !!(ctl_reg & BIT(g->oe_bit)); in msm_gpio_dbg_show_one()
700 func = (ctl_reg >> g->mux_bit) & 7; in msm_gpio_dbg_show_one()
701 drive = (ctl_reg >> g->drv_bit) & 7; in msm_gpio_dbg_show_one()
702 pull = (ctl_reg >> g->pull_bit) & 3; in msm_gpio_dbg_show_one()
704 if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present)) in msm_gpio_dbg_show_one()
705 egpio_enable = !(ctl_reg & BIT(g->egpio_enable)); in msm_gpio_dbg_show_one()
708 val = !!(io_reg & BIT(g->out_bit)); in msm_gpio_dbg_show_one()
710 val = !!(io_reg & BIT(g->in_bit)); in msm_gpio_dbg_show_one()
713 seq_printf(s, " %-8s: egpio\n", g->grp.name); in msm_gpio_dbg_show_one()
717 seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in"); in msm_gpio_dbg_show_one()
718 seq_printf(s, " %-4s func%d", str_high_low(val), func); in msm_gpio_dbg_show_one()
720 if (pctrl->soc->pull_no_keeper) in msm_gpio_dbg_show_one()
729 unsigned gpio = chip->base; in msm_gpio_dbg_show()
732 for (i = 0; i < chip->ngpio; i++, gpio++) in msm_gpio_dbg_show()
747 const int *reserved = pctrl->soc->reserved_gpios; in msm_gpio_init_valid_mask()
750 /* Remove driver-provided reserved GPIOs from valid_mask */ in msm_gpio_init_valid_mask()
754 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); in msm_gpio_init_valid_mask()
755 return -EINVAL; in msm_gpio_init_valid_mask()
764 len = ret = device_property_count_u16(pctrl->dev, "gpios"); in msm_gpio_init_valid_mask()
769 return -EINVAL; in msm_gpio_init_valid_mask()
773 return -ENOMEM; in msm_gpio_init_valid_mask()
775 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); in msm_gpio_init_valid_mask()
777 dev_err(pctrl->dev, "could not read list of GPIOs\n"); in msm_gpio_init_valid_mask()
801 /* For dual-edge interrupts in software, since some hardware has no
805 * settings of both-edge irq lines to try and catch the next edge.
808 * - the status bit goes high, indicating that an edge was caught, or
809 * - the input value of the gpio doesn't change during the attempt.
814 * The do-loop tries to sledge-hammer closed the timing hole between
815 * the initial value-read and the polarity-write - if the line value changes
822 const struct msm_pingroup *g, in msm_gpio_update_dual_edge_pos() argument
830 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
832 pol = msm_readl_intr_cfg(pctrl, g); in msm_gpio_update_dual_edge_pos()
833 pol ^= BIT(g->intr_polarity_bit); in msm_gpio_update_dual_edge_pos()
834 msm_writel_intr_cfg(pol, pctrl, g); in msm_gpio_update_dual_edge_pos()
836 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
837 intstat = msm_readl_intr_status(pctrl, g); in msm_gpio_update_dual_edge_pos()
840 } while (loop_limit-- > 0); in msm_gpio_update_dual_edge_pos()
841 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", in msm_gpio_update_dual_edge_pos()
849 const struct msm_pingroup *g; in msm_gpio_irq_mask() local
853 if (d->parent_data) in msm_gpio_irq_mask()
856 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_mask()
859 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
861 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_mask()
863 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_mask()
869 * for level type irq). The 'non-raw' status enable bit causes the in msm_gpio_irq_mask()
878 * enabled all the time causes level interrupts to re-latch into the in msm_gpio_irq_mask()
885 val &= ~BIT(g->intr_raw_status_bit); in msm_gpio_irq_mask()
887 val &= ~BIT(g->intr_enable_bit); in msm_gpio_irq_mask()
888 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_mask()
890 clear_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_mask()
892 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_mask()
899 const struct msm_pingroup *g; in msm_gpio_irq_unmask() local
903 if (d->parent_data) in msm_gpio_irq_unmask()
906 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_unmask()
909 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
911 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_unmask()
913 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_unmask()
914 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_unmask()
915 val |= BIT(g->intr_enable_bit); in msm_gpio_irq_unmask()
916 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_unmask()
918 set_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_unmask()
920 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_unmask()
928 gpiochip_enable_irq(gc, d->hwirq); in msm_gpio_irq_enable()
930 if (d->parent_data) in msm_gpio_irq_enable()
933 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_enable()
942 if (d->parent_data) in msm_gpio_irq_disable()
945 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_disable()
948 gpiochip_disable_irq(gc, d->hwirq); in msm_gpio_irq_disable()
952 * msm_gpio_update_dual_edge_parent() - Prime next edge for IRQs handled by parent.
964 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_update_dual_edge_parent() local
970 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
983 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
993 } while (loop_limit-- > 0); in msm_gpio_update_dual_edge_parent()
994 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n"); in msm_gpio_update_dual_edge_parent()
1001 const struct msm_pingroup *g; in msm_gpio_irq_ack() local
1004 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_ack()
1005 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
1010 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
1012 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_ack()
1014 msm_ack_intr_status(pctrl, g); in msm_gpio_irq_ack()
1016 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
1017 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_ack()
1019 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_ack()
1024 d = d->parent_data; in msm_gpio_irq_eoi()
1027 d->chip->irq_eoi(d); in msm_gpio_irq_eoi()
1037 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data && in msm_gpio_needs_dual_edge_parent_workaround()
1038 test_bit(d->hwirq, pctrl->skip_wake_irqs); in msm_gpio_needs_dual_edge_parent_workaround()
1045 const struct msm_pingroup *g; in msm_gpio_irq_set_type() local
1051 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1057 if (d->parent_data) in msm_gpio_irq_set_type()
1060 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_set_type()
1061 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1066 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
1068 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1073 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) in msm_gpio_irq_set_type()
1074 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1076 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1082 if (g->intr_target_width) in msm_gpio_irq_set_type()
1083 intr_target_mask = GENMASK(g->intr_target_width - 1, 0); in msm_gpio_irq_set_type()
1085 if (pctrl->intr_target_use_scm) { in msm_gpio_irq_set_type()
1086 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; in msm_gpio_irq_set_type()
1090 val &= ~(intr_target_mask << g->intr_target_bit); in msm_gpio_irq_set_type()
1091 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1095 dev_err(pctrl->dev, in msm_gpio_irq_set_type()
1097 d->hwirq); in msm_gpio_irq_set_type()
1099 val = msm_readl_intr_target(pctrl, g); in msm_gpio_irq_set_type()
1100 val &= ~(intr_target_mask << g->intr_target_bit); in msm_gpio_irq_set_type()
1101 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1102 msm_writel_intr_target(val, pctrl, g); in msm_gpio_irq_set_type()
1110 val = oldval = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_set_type()
1111 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
1112 if (g->intr_detection_width == 2) { in msm_gpio_irq_set_type()
1113 val &= ~(3 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1114 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1117 val |= 1 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1118 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1121 val |= 2 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1122 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1125 val |= 3 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1126 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1131 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1134 } else if (g->intr_detection_width == 1) { in msm_gpio_irq_set_type()
1135 val &= ~(1 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1136 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1139 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1140 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1143 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1146 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1147 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1152 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1158 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_set_type()
1164 * also still have a non-matching interrupt latched, so clear whenever in msm_gpio_irq_set_type()
1168 msm_ack_intr_status(pctrl, g); in msm_gpio_irq_set_type()
1170 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_set_type()
1171 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_set_type()
1173 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1194 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_wake()
1197 return irq_set_irq_wake(pctrl->irq, on); in msm_gpio_irq_set_wake()
1204 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_reqres() local
1208 if (!try_module_get(gc->owner)) in msm_gpio_irq_reqres()
1209 return -ENODEV; in msm_gpio_irq_reqres()
1211 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); in msm_gpio_irq_reqres()
1214 msm_gpio_direction_input(gc, d->hwirq); in msm_gpio_irq_reqres()
1216 if (gpiochip_lock_as_irq(gc, d->hwirq)) { in msm_gpio_irq_reqres()
1217 dev_err(gc->parent, in msm_gpio_irq_reqres()
1219 d->hwirq); in msm_gpio_irq_reqres()
1220 ret = -EINVAL; in msm_gpio_irq_reqres()
1225 * The disable / clear-enable workaround we do in msm_pinmux_set_mux() in msm_gpio_irq_reqres()
1229 irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY); in msm_gpio_irq_reqres()
1239 if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { in msm_gpio_irq_reqres()
1242 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_reqres()
1244 intr_cfg = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_reqres()
1245 if (intr_cfg & BIT(g->intr_wakeup_present_bit)) { in msm_gpio_irq_reqres()
1246 intr_cfg |= BIT(g->intr_wakeup_enable_bit); in msm_gpio_irq_reqres()
1247 msm_writel_intr_cfg(intr_cfg, pctrl, g); in msm_gpio_irq_reqres()
1250 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_reqres()
1255 module_put(gc->owner); in msm_gpio_irq_reqres()
1263 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_relres() local
1267 if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { in msm_gpio_irq_relres()
1270 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_relres()
1272 intr_cfg = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_relres()
1273 if (intr_cfg & BIT(g->intr_wakeup_present_bit)) { in msm_gpio_irq_relres()
1274 intr_cfg &= ~BIT(g->intr_wakeup_enable_bit); in msm_gpio_irq_relres()
1275 msm_writel_intr_cfg(intr_cfg, pctrl, g); in msm_gpio_irq_relres()
1278 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_relres()
1281 gpiochip_unlock_as_irq(gc, d->hwirq); in msm_gpio_irq_relres()
1282 module_put(gc->owner); in msm_gpio_irq_relres()
1291 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_affinity()
1294 return -EINVAL; in msm_gpio_irq_set_affinity()
1302 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_vcpu_affinity()
1305 return -EINVAL; in msm_gpio_irq_set_vcpu_affinity()
1311 const struct msm_pingroup *g; in msm_gpio_irq_handler() local
1324 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { in msm_gpio_irq_handler()
1325 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
1326 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_handler()
1327 if (val & BIT(g->intr_status_bit)) { in msm_gpio_irq_handler()
1328 generic_handle_domain_irq(gc->irq.domain, i); in msm_gpio_irq_handler()
1353 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_wakeirq()
1354 map = &pctrl->soc->wakeirq_map[i]; in msm_gpio_wakeirq()
1355 if (map->gpio == child) { in msm_gpio_wakeirq()
1356 *parent = map->wakeirq; in msm_gpio_wakeirq()
1366 if (pctrl->soc->reserved_gpios) in msm_gpio_needs_valid_mask()
1369 return device_property_count_u16(pctrl->dev, "gpios") > 0; in msm_gpio_needs_valid_mask()
1397 unsigned gpio, ngpio = pctrl->soc->ngpios; in msm_gpio_init()
1402 return -EINVAL; in msm_gpio_init()
1404 chip = &pctrl->chip; in msm_gpio_init()
1405 chip->base = -1; in msm_gpio_init()
1406 chip->ngpio = ngpio; in msm_gpio_init()
1407 chip->label = dev_name(pctrl->dev); in msm_gpio_init()
1408 chip->parent = pctrl->dev; in msm_gpio_init()
1409 chip->owner = THIS_MODULE; in msm_gpio_init()
1411 chip->init_valid_mask = msm_gpio_init_valid_mask; in msm_gpio_init()
1413 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); in msm_gpio_init()
1415 chip->irq.parent_domain = irq_find_matching_host(np, in msm_gpio_init()
1418 if (!chip->irq.parent_domain) in msm_gpio_init()
1419 return -EPROBE_DEFER; in msm_gpio_init()
1420 chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq; in msm_gpio_init()
1425 skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain); in msm_gpio_init()
1426 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_init()
1427 gpio = pctrl->soc->wakeirq_map[i].gpio; in msm_gpio_init()
1428 set_bit(gpio, pctrl->skip_wake_irqs); in msm_gpio_init()
1432 girq = &chip->irq; in msm_gpio_init()
1434 girq->parent_handler = msm_gpio_irq_handler; in msm_gpio_init()
1435 girq->fwnode = dev_fwnode(pctrl->dev); in msm_gpio_init()
1436 girq->num_parents = 1; in msm_gpio_init()
1437 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), in msm_gpio_init()
1439 if (!girq->parents) in msm_gpio_init()
1440 return -ENOMEM; in msm_gpio_init()
1441 girq->default_type = IRQ_TYPE_NONE; in msm_gpio_init()
1442 girq->handler = handle_bad_irq; in msm_gpio_init()
1443 girq->parents[0] = pctrl->irq; in msm_gpio_init()
1445 ret = gpiochip_add_data(&pctrl->chip, pctrl); in msm_gpio_init()
1447 dev_err(pctrl->dev, "Failed register gpiochip\n"); in msm_gpio_init()
1452 * For DeviceTree-supported systems, the gpio core checks the in msm_gpio_init()
1453 * pinctrl's device node for the "gpio-ranges" property. in msm_gpio_init()
1458 * files which don't set the "gpio-ranges" property or systems that in msm_gpio_init()
1461 if (!of_property_present(pctrl->dev->of_node, "gpio-ranges")) { in msm_gpio_init()
1462 ret = gpiochip_add_pin_range(&pctrl->chip, in msm_gpio_init()
1463 dev_name(pctrl->dev), 0, 0, chip->ngpio); in msm_gpio_init()
1465 dev_err(pctrl->dev, "Failed to add pin range\n"); in msm_gpio_init()
1466 gpiochip_remove(&pctrl->chip); in msm_gpio_init()
1479 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); in msm_ps_hold_restart()
1488 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); in msm_ps_hold_poweroff()
1494 const struct pinfunction *func = pctrl->soc->functions; in msm_pinctrl_setup_pm_reset()
1496 for (i = 0; i < pctrl->soc->nfunctions; i++) in msm_pinctrl_setup_pm_reset()
1498 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; in msm_pinctrl_setup_pm_reset()
1499 pctrl->restart_nb.priority = 128; in msm_pinctrl_setup_pm_reset()
1500 if (register_restart_handler(&pctrl->restart_nb)) in msm_pinctrl_setup_pm_reset()
1501 dev_err(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1513 return pinctrl_force_sleep(pctrl->pctrl); in msm_pinctrl_suspend()
1520 return pinctrl_force_default(pctrl->pctrl); in msm_pinctrl_resume()
1536 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in msm_pinctrl_probe()
1538 return -ENOMEM; in msm_pinctrl_probe()
1540 pctrl->dev = &pdev->dev; in msm_pinctrl_probe()
1541 pctrl->soc = soc_data; in msm_pinctrl_probe()
1542 pctrl->chip = msm_gpio_template; in msm_pinctrl_probe()
1543 pctrl->intr_target_use_scm = of_device_is_compatible( in msm_pinctrl_probe()
1544 pctrl->dev->of_node, in msm_pinctrl_probe()
1545 "qcom,ipq8064-pinctrl"); in msm_pinctrl_probe()
1547 raw_spin_lock_init(&pctrl->lock); in msm_pinctrl_probe()
1549 if (soc_data->tiles) { in msm_pinctrl_probe()
1550 for (i = 0; i < soc_data->ntiles; i++) { in msm_pinctrl_probe()
1552 soc_data->tiles[i]); in msm_pinctrl_probe()
1553 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1554 if (IS_ERR(pctrl->regs[i])) in msm_pinctrl_probe()
1555 return PTR_ERR(pctrl->regs[i]); in msm_pinctrl_probe()
1558 pctrl->regs[0] = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in msm_pinctrl_probe()
1559 if (IS_ERR(pctrl->regs[0])) in msm_pinctrl_probe()
1560 return PTR_ERR(pctrl->regs[0]); in msm_pinctrl_probe()
1562 pctrl->phys_base[0] = res->start; in msm_pinctrl_probe()
1567 pctrl->irq = platform_get_irq(pdev, 0); in msm_pinctrl_probe()
1568 if (pctrl->irq < 0) in msm_pinctrl_probe()
1569 return pctrl->irq; in msm_pinctrl_probe()
1571 pctrl->desc.owner = THIS_MODULE; in msm_pinctrl_probe()
1572 pctrl->desc.pctlops = &msm_pinctrl_ops; in msm_pinctrl_probe()
1573 pctrl->desc.pmxops = &msm_pinmux_ops; in msm_pinctrl_probe()
1574 pctrl->desc.confops = &msm_pinconf_ops; in msm_pinctrl_probe()
1575 pctrl->desc.name = dev_name(&pdev->dev); in msm_pinctrl_probe()
1576 pctrl->desc.pins = pctrl->soc->pins; in msm_pinctrl_probe()
1577 pctrl->desc.npins = pctrl->soc->npins; in msm_pinctrl_probe()
1579 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in msm_pinctrl_probe()
1580 if (IS_ERR(pctrl->pctrl)) { in msm_pinctrl_probe()
1581 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); in msm_pinctrl_probe()
1582 return PTR_ERR(pctrl->pctrl); in msm_pinctrl_probe()
1591 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); in msm_pinctrl_probe()
1601 gpiochip_remove(&pctrl->chip); in msm_pinctrl_remove()
1603 unregister_restart_handler(&pctrl->restart_nb); in msm_pinctrl_remove()