Lines Matching full:clr
188 u32 clr, set; in sgpio_configure_bitstream() local
192 clr = SGPIO_LUTON_PORT_WIDTH; in sgpio_configure_bitstream()
197 clr = SGPIO_OCELOT_PORT_WIDTH; in sgpio_configure_bitstream()
202 clr = SGPIO_SPARX5_PORT_WIDTH; in sgpio_configure_bitstream()
209 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set); in sgpio_configure_bitstream()
214 u32 clr, set; in sgpio_configure_clock() local
218 clr = SGPIO_LUTON_CLK_FREQ; in sgpio_configure_clock()
222 clr = SGPIO_OCELOT_CLK_FREQ; in sgpio_configure_clock()
226 clr = SGPIO_SPARX5_CLK_FREQ; in sgpio_configure_clock()
232 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set); in sgpio_configure_clock()
291 u32 clr, set; in sgpio_output_set() local
296 clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit)); in sgpio_output_set()
300 clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit)); in sgpio_output_set()
304 clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit)); in sgpio_output_set()
311 ret = regmap_update_bits_check(priv->regs, reg, clr | set, set, in sgpio_output_set()