Lines Matching +full:13 +full:e10
133 #define H21 13
134 #define H21_DESC SIG_DESC_SET(SCU80, 13)
298 #define GPIE2_DESC SIG_DESC_SET(SCU8C, 13)
516 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
518 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
520 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
626 SIG_EXPR_LIST_DECL_SINGLE(R4, VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13));
896 SIG_DESC_SET(SCU88, 13), COND2);
1017 #define E10 143 macro
1018 SIG_EXPR_LIST_DECL_SINGLE(E10, MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31));
1019 PIN_DECL_1(E10, GPIOR7, MDIO1);
1021 FUNC_GROUP_DECL(MDIO1, D8, E10);
1233 SIG_EXPR_LIST_DECL_SINGLE(A4, GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13));
1449 SSSF_PIN_DECL(M19, GPIOY5, SDA1, SIG_DESC_SET(SCUA4, 13));
1867 #define USB11BHID_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 0, 0 }
1868 #define USB2BD_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 1, 0 }
1869 #define USB2BH1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 2, 0 }
1870 #define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 }
1995 ASPEED_PINCTRL_PIN(E10),
2487 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AA19, E10, SCU8C, 17),
2488 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, AA19, E10, SCU8C, 17),
2557 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B4, C4, SCU90, 13),
2558 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B4, C4, SCU90, 13),
2583 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G3, G3, SCUA8, 13),
2584 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G3, G3, SCUA8, 13),
2758 !(desc->mask & (BIT(22) | BIT(21) | BIT(13) | BIT(12)))) in aspeed_g5_sig_expr_set()