Lines Matching +full:rom +full:- +full:15 +full:h
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #include <linux/bitops.h>
6 #include <linux/init.h>
7 #include <linux/io.h>
8 #include <linux/kernel.h>
9 #include <linux/mutex.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12 #include <linux/pinctrl/pinctrl.h>
13 #include <linux/pinctrl/pinmux.h>
14 #include <linux/pinctrl/pinconf.h>
15 #include <linux/pinctrl/pinconf-generic.h>
16 #include <linux/string.h>
17 #include <linux/types.h>
19 #include "../core.h"
20 #include "../pinctrl-utils.h"
21 #include "pinmux-aspeed.h"
22 #include "pinctrl-aspeed.h"
32 * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
35 * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
44 #define SCU80 0x80 /* Multi-function Pin Control #1 */
45 #define SCU84 0x84 /* Multi-function Pin Control #2 */
46 #define SCU88 0x88 /* Multi-function Pin Control #3 */
47 #define SCU8C 0x8C /* Multi-function Pin Control #4 */
48 #define SCU90 0x90 /* Multi-function Pin Control #5 */
49 #define SCU94 0x94 /* Multi-function Pin Control #6 */
50 #define SCUA0 0xA0 /* Multi-function Pin Control #7 */
51 #define SCUA4 0xA4 /* Multi-function Pin Control #8 */
52 #define SCUA8 0xA8 /* Multi-function Pin Control #9 */
53 #define SCUAC 0xAC /* Multi-function Pin Control #10 */
153 #define E18 15
155 SIG_DESC_SET(SCU80, 15),
159 SIG_DESC_SET(SCU80, 15),
304 #define GPIE6_DESC SIG_DESC_SET(SCU8C, 15)
419 SIG_EXPR_DECL_SINGLE(SIOSCI, SIOSCI, SIG_DESC_SET(SCUA4, 15));
637 SSSF_PIN_DECL(T1, GPIOJ7, DDCDAT, SIG_DESC_SET(SCU84, 15));
1009 SIG_DESC_SET(SCU88, 15));
1092 * it is only mentioned in one location. Particularly, the Multi-function Pins
1132 SIG_EXPR_LIST_DECL(ROMA24, ROM,
1136 SIG_EXPR_LIST_ALIAS(V21, ROMA24, ROM);
1145 SIG_EXPR_LIST_DECL(ROMA25, ROM,
1149 SIG_EXPR_LIST_ALIAS(W22, ROMA25, ROM);
1168 SIG_EXPR_LIST_DECL(ROMD4, ROM,
1172 SIG_EXPR_LIST_ALIAS(U21, ROMD4, ROM);
1183 SIG_EXPR_LIST_DECL(ROMD5, ROM,
1187 SIG_EXPR_LIST_ALIAS(T19, ROMD5, ROM);
1198 SIG_EXPR_LIST_DECL(ROMD6, ROM,
1202 SIG_EXPR_LIST_ALIAS(V22, ROMD6, ROM);
1213 SIG_EXPR_LIST_DECL(ROMD7, ROM,
1217 SIG_EXPR_LIST_ALIAS(U20, ROMD7, ROM);
1229 SIG_EXPR_LIST_DECL(ROMOE, ROM,
1233 SIG_EXPR_LIST_ALIAS(R18, ROMOE, ROM);
1242 SIG_EXPR_LIST_DECL(ROMWE, ROM,
1246 SIG_EXPR_LIST_ALIAS(N21, ROMWE, ROM);
1254 SIG_EXPR_LIST_DECL(ROMA22, ROM,
1258 SIG_EXPR_LIST_ALIAS(L22, ROMA22, ROM);
1267 SIG_EXPR_LIST_DECL(ROMA23, ROM,
1271 SIG_EXPR_LIST_ALIAS(K18, ROMA23, ROM);
1392 SIG_EXPR_LIST_DECL_SINGLE(B11, GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15));
1900 /* Note we account for GPIOY4-GPIOY7 even though they're not valid, thus 216
1901 * pins becomes 220. Four additional non-GPIO-capable pins are present for USB.
2473 /* GPIOs T[0-5] (RGMII1 Tx pins) */
2478 /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
2483 /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
2487 /* GPIOs V[2-7] (RGMII2 Rx pins) */
2488 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C9, C8, SCU90, 15),
2489 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C9, C8, SCU90, 15),
2491 /* ADC pull-downs (SCUA8[19:4]) */
2514 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N4, N4, SCUA8, 15),
2515 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N4, N4, SCUA8, 15),
2528 * banks D and E is handled by the GPIO driver - GPIO passthrough is
2529 * treated like any other non-GPIO mux function. There is a catch
2532 * fully support pass-through debounce.
2551 for (i = 0; i < expr->ndescs; i++) { in aspeed_g4_sig_expr_set()
2552 const struct aspeed_sig_desc *desc = &expr->descs[i]; in aspeed_g4_sig_expr_set()
2553 u32 pattern = enable ? desc->enable : desc->disable; in aspeed_g4_sig_expr_set()
2554 u32 val = (pattern << __ffs(desc->mask)); in aspeed_g4_sig_expr_set()
2556 if (!ctx->maps[desc->ip]) in aspeed_g4_sig_expr_set()
2557 return -ENODEV; in aspeed_g4_sig_expr_set()
2560 * Strap registers are configured in hardware or by early-boot in aspeed_g4_sig_expr_set()
2561 * firmware. Treat them as read-only despite that we can write in aspeed_g4_sig_expr_set()
2563 * deconfigured and is the reason we re-evaluate after writing in aspeed_g4_sig_expr_set()
2566 * We make two exceptions to the read-only rule: in aspeed_g4_sig_expr_set()
2568 * - The passthrough mode of GPIO ports D and E are commonly in aspeed_g4_sig_expr_set()
2569 * used with front-panel buttons to allow normal operation in aspeed_g4_sig_expr_set()
2572 * disabled for the BMC to control host power-on and reset. in aspeed_g4_sig_expr_set()
2574 * - The operating mode of the SPI1 interface is simply in aspeed_g4_sig_expr_set()
2578 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 && in aspeed_g4_sig_expr_set()
2579 !(desc->mask & (BIT(22) | BIT(21) | BIT(13) | BIT(12)))) in aspeed_g4_sig_expr_set()
2582 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2) in aspeed_g4_sig_expr_set()
2585 ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg, in aspeed_g4_sig_expr_set()
2586 desc->mask, val); in aspeed_g4_sig_expr_set()
2597 return -EPERM; in aspeed_g4_sig_expr_set()
2604 { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
2605 { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
2657 .name = "aspeed-g4-pinctrl",
2677 { .compatible = "aspeed,ast2400-pinctrl", },
2679 * The aspeed,g4-pinctrl compatible has been removed the from the
2682 { .compatible = "aspeed,g4-pinctrl", },
2689 .name = "aspeed-g4-pinctrl",