Lines Matching +full:13 +full:e10
141 #define H19 13
142 #define H19_DESC SIG_DESC_SET(SCU80, 13)
302 #define GPIE2_DESC SIG_DESC_SET(SCU8C, 13)
530 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
532 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
534 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
631 SSSF_PIN_DECL(U2, GPIOJ5, VGAVS, SIG_DESC_SET(SCU84, 13));
999 SIG_DESC_SET(SCU88, 13));
1377 SIG_EXPR_LIST_DECL_SINGLE(D11, GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13));
1407 #define E10 169 macro
1408 SIG_EXPR_LIST_DECL_SINGLE(E10, GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17));
1409 SIG_EXPR_LIST_DECL_SINGLE(E10, RMII1RXER, RMII1, RMII1_DESC);
1410 SIG_EXPR_LIST_DECL_SINGLE(E10, RGMII1RXD3, RGMII1);
1411 PIN_DECL_(E10, SIG_EXPR_LIST_PTR(E10, GPIOV1),
1412 SIG_EXPR_LIST_PTR(E10, RMII1RXER),
1413 SIG_EXPR_LIST_PTR(E10, RGMII1RXD3));
1458 E10);
1460 E10);
2004 ASPEED_PINCTRL_PIN(E10),
2484 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E11, E10, SCU90, 13),
2485 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E11, E10, SCU90, 13),
2510 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M1, M1, SCUA8, 13),
2511 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M1, M1, SCUA8, 13),
2579 !(desc->mask & (BIT(22) | BIT(21) | BIT(13) | BIT(12)))) in aspeed_g4_sig_expr_set()