353 struct wiz {  struct
398 static int wiz_reset(struct wiz *wiz)  in wiz_reset()  argument
402 	ret = regmap_field_write(wiz->por_en, 0x1);  in wiz_reset()
408 	ret = regmap_field_write(wiz->por_en, 0x0);  in wiz_reset()
415 static int wiz_p_mac_div_sel(struct wiz *wiz)  in wiz_p_mac_div_sel()  argument
417 	u32 num_lanes = wiz->num_lanes;  in wiz_p_mac_div_sel()
422 		if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII ||  in wiz_p_mac_div_sel()
423 		    wiz->lane_phy_type[i] == PHY_TYPE_QSGMII ||  in wiz_p_mac_div_sel()
424 		    wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {  in wiz_p_mac_div_sel()
425 			ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);  in wiz_p_mac_div_sel()
429 			ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2);  in wiz_p_mac_div_sel()
438 static int wiz_mode_select(struct wiz *wiz)  in wiz_mode_select()  argument
440 	u32 num_lanes = wiz->num_lanes;  in wiz_mode_select()
446 		if (wiz->lane_phy_type[i] == PHY_TYPE_DP) {  in wiz_mode_select()
448 		} else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {  in wiz_mode_select()
450 		} else if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {  in wiz_mode_select()
451 			ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3);  in wiz_mode_select()
452 			ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3);  in wiz_mode_select()
453 			ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x2);  in wiz_mode_select()
459 		ret = regmap_field_write(wiz->p_standard_mode[i], mode);  in wiz_mode_select()
467 static int wiz_init_raw_interface(struct wiz *wiz, bool enable)  in wiz_init_raw_interface()  argument
469 	u32 num_lanes = wiz->num_lanes;  in wiz_init_raw_interface()
474 		ret = regmap_field_write(wiz->p_align[i], enable);  in wiz_init_raw_interface()
478 		ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);  in wiz_init_raw_interface()
486 static int wiz_init(struct wiz *wiz)  in wiz_init()  argument
488 	struct device *dev = wiz->dev;  in wiz_init()
491 	ret = wiz_reset(wiz);  in wiz_init()
493 		dev_err(dev, "WIZ reset failed\n");  in wiz_init()
497 	ret = wiz_mode_select(wiz);  in wiz_init()
499 		dev_err(dev, "WIZ mode select failed\n");  in wiz_init()
503 	ret = wiz_p_mac_div_sel(wiz);  in wiz_init()
509 	ret = wiz_init_raw_interface(wiz, true);  in wiz_init()
511 		dev_err(dev, "WIZ interface initialization failed\n");  in wiz_init()
518 static int wiz_regfield_init(struct wiz *wiz)  in wiz_regfield_init()  argument
520 	struct regmap *regmap = wiz->regmap;  in wiz_regfield_init()
521 	struct regmap *scm_regmap = wiz->regmap; /* updated later to scm_regmap if applicable */  in wiz_regfield_init()
522 	int num_lanes = wiz->num_lanes;  in wiz_regfield_init()
523 	struct device *dev = wiz->dev;  in wiz_regfield_init()
524 	const struct wiz_data *data = wiz->data;  in wiz_regfield_init()
527 	wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);  in wiz_regfield_init()
528 	if (IS_ERR(wiz->por_en)) {  in wiz_regfield_init()
530 		return PTR_ERR(wiz->por_en);  in wiz_regfield_init()
533 	wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,  in wiz_regfield_init()
535 	if (IS_ERR(wiz->phy_reset_n)) {  in wiz_regfield_init()
537 		return PTR_ERR(wiz->phy_reset_n);  in wiz_regfield_init()
540 	wiz->pma_cmn_refclk_int_mode =  in wiz_regfield_init()
542 	if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {  in wiz_regfield_init()
544 		return PTR_ERR(wiz->pma_cmn_refclk_int_mode);  in wiz_regfield_init()
547 	wiz->pma_cmn_refclk_mode =  in wiz_regfield_init()
549 	if (IS_ERR(wiz->pma_cmn_refclk_mode)) {  in wiz_regfield_init()
551 		return PTR_ERR(wiz->pma_cmn_refclk_mode);  in wiz_regfield_init()
554 	wiz->div_sel_field[CMN_REFCLK_DIG_DIV] =  in wiz_regfield_init()
556 	if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) {  in wiz_regfield_init()
558 		return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]);  in wiz_regfield_init()
562 		wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] =  in wiz_regfield_init()
565 		if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) {  in wiz_regfield_init()
567 			return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]);  in wiz_regfield_init()
571 	if (wiz->scm_regmap) {  in wiz_regfield_init()
572 		scm_regmap = wiz->scm_regmap;  in wiz_regfield_init()
573 		wiz->sup_legacy_clk_override =  in wiz_regfield_init()
575 		if (IS_ERR(wiz->sup_legacy_clk_override)) {  in wiz_regfield_init()
577 			return PTR_ERR(wiz->sup_legacy_clk_override);  in wiz_regfield_init()
581 	wiz->mux_sel_field[PLL0_REFCLK] =  in wiz_regfield_init()
583 	if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) {  in wiz_regfield_init()
585 		return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]);  in wiz_regfield_init()
588 	wiz->mux_sel_field[PLL1_REFCLK] =  in wiz_regfield_init()
590 	if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) {  in wiz_regfield_init()
592 		return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);  in wiz_regfield_init()
595 	wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, scm_regmap,  in wiz_regfield_init()
597 	if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) {  in wiz_regfield_init()
599 		return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]);  in wiz_regfield_init()
603 		wiz->pma_cmn_refclk1_int_mode =  in wiz_regfield_init()
605 		if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) {  in wiz_regfield_init()
607 			return PTR_ERR(wiz->pma_cmn_refclk1_int_mode);  in wiz_regfield_init()
612 		wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,  in wiz_regfield_init()
614 		if (IS_ERR(wiz->p_enable[i])) {  in wiz_regfield_init()
616 			return PTR_ERR(wiz->p_enable[i]);  in wiz_regfield_init()
619 		wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,  in wiz_regfield_init()
621 		if (IS_ERR(wiz->p_align[i])) {  in wiz_regfield_init()
623 			return PTR_ERR(wiz->p_align[i]);  in wiz_regfield_init()
626 		wiz->p_raw_auto_start[i] =  in wiz_regfield_init()
628 		if (IS_ERR(wiz->p_raw_auto_start[i])) {  in wiz_regfield_init()
631 			return PTR_ERR(wiz->p_raw_auto_start[i]);  in wiz_regfield_init()
634 		wiz->p_standard_mode[i] =  in wiz_regfield_init()
636 		if (IS_ERR(wiz->p_standard_mode[i])) {  in wiz_regfield_init()
639 			return PTR_ERR(wiz->p_standard_mode[i]);  in wiz_regfield_init()
642 		wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]);  in wiz_regfield_init()
643 		if (IS_ERR(wiz->p0_fullrt_div[i])) {  in wiz_regfield_init()
645 			return PTR_ERR(wiz->p0_fullrt_div[i]);  in wiz_regfield_init()
648 		wiz->p0_mac_src_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_mac_src_sel[i]);  in wiz_regfield_init()
649 		if (IS_ERR(wiz->p0_mac_src_sel[i])) {  in wiz_regfield_init()
651 			return PTR_ERR(wiz->p0_mac_src_sel[i]);  in wiz_regfield_init()
654 		wiz->p0_rxfclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_rxfclk_sel[i]);  in wiz_regfield_init()
655 		if (IS_ERR(wiz->p0_rxfclk_sel[i])) {  in wiz_regfield_init()
657 			return PTR_ERR(wiz->p0_rxfclk_sel[i]);  in wiz_regfield_init()
660 		wiz->p0_refclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_refclk_sel[i]);  in wiz_regfield_init()
661 		if (IS_ERR(wiz->p0_refclk_sel[i])) {  in wiz_regfield_init()
663 			return PTR_ERR(wiz->p0_refclk_sel[i]);  in wiz_regfield_init()
666 		wiz->p_mac_div_sel0[i] =  in wiz_regfield_init()
668 		if (IS_ERR(wiz->p_mac_div_sel0[i])) {  in wiz_regfield_init()
671 			return PTR_ERR(wiz->p_mac_div_sel0[i]);  in wiz_regfield_init()
674 		wiz->p_mac_div_sel1[i] =  in wiz_regfield_init()
676 		if (IS_ERR(wiz->p_mac_div_sel1[i])) {  in wiz_regfield_init()
679 			return PTR_ERR(wiz->p_mac_div_sel1[i]);  in wiz_regfield_init()
683 	wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,  in wiz_regfield_init()
685 	if (IS_ERR(wiz->typec_ln10_swap)) {  in wiz_regfield_init()
687 		return PTR_ERR(wiz->typec_ln10_swap);  in wiz_regfield_init()
690 	wiz->typec_ln23_swap = devm_regmap_field_alloc(dev, regmap,  in wiz_regfield_init()
692 	if (IS_ERR(wiz->typec_ln23_swap)) {  in wiz_regfield_init()
694 		return PTR_ERR(wiz->typec_ln23_swap);  in wiz_regfield_init()
697 	wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);  in wiz_regfield_init()
698 	if (IS_ERR(wiz->phy_en_refclk)) {  in wiz_regfield_init()
700 		return PTR_ERR(wiz->phy_en_refclk);  in wiz_regfield_init()
741 static int wiz_phy_en_refclk_register(struct wiz *wiz)  in wiz_phy_en_refclk_register()  argument
744 	struct device *dev = wiz->dev;  in wiz_phy_en_refclk_register()
768 	wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk;  in wiz_phy_en_refclk_register()
778 	wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk;  in wiz_phy_en_refclk_register()
809 static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field,  in wiz_mux_clk_register()  argument
812 	struct device *dev = wiz->dev;  in wiz_mux_clk_register()
832 		clk = wiz->input_clks[mux_sel->parents[i]];  in wiz_mux_clk_register()
862 	wiz->output_clks[clk_index] = clk;  in wiz_mux_clk_register()
870 static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node,  in wiz_mux_of_clk_register()  argument
873 	struct device *dev = wiz->dev;  in wiz_mux_of_clk_register()
965 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node,  in wiz_div_clk_register()  argument
969 	struct device *dev = wiz->dev;  in wiz_div_clk_register()
1013 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)  in wiz_clock_cleanup()  argument
1015 	const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;  in wiz_clock_cleanup()
1016 	struct device *dev = wiz->dev;  in wiz_clock_cleanup()
1020 	switch (wiz->type) {  in wiz_clock_cleanup()
1037 	for (i = 0; i < wiz->clk_div_sel_num; i++) {  in wiz_clock_cleanup()
1043 	of_clk_del_provider(wiz->dev->of_node);  in wiz_clock_cleanup()
1046 static int wiz_clock_register(struct wiz *wiz)  in wiz_clock_register()  argument
1048 	const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;  in wiz_clock_register()
1049 	struct device *dev = wiz->dev;  in wiz_clock_register()
1057 		ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index);  in wiz_clock_register()
1064 	ret = wiz_phy_en_refclk_register(wiz);  in wiz_clock_register()
1070 	wiz->clk_data.clks = wiz->output_clks;  in wiz_clock_register()
1071 	wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS;  in wiz_clock_register()
1072 	ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data);  in wiz_clock_register()
1079 static void wiz_clock_init(struct wiz *wiz)  in wiz_clock_init()  argument
1083 	rate = clk_get_rate(wiz->input_clks[WIZ_CORE_REFCLK]);  in wiz_clock_init()
1085 		regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);  in wiz_clock_init()
1087 		regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);  in wiz_clock_init()
1089 	switch (wiz->type) {  in wiz_clock_init()
1094 			regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2);  in wiz_clock_init()
1097 			regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3);  in wiz_clock_init()
1100 			regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0);  in wiz_clock_init()
1108 	if (wiz->input_clks[WIZ_CORE_REFCLK1]) {  in wiz_clock_init()
1109 		rate = clk_get_rate(wiz->input_clks[WIZ_CORE_REFCLK1]);  in wiz_clock_init()
1111 			regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1);  in wiz_clock_init()
1113 			regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3);  in wiz_clock_init()
1116 	rate = clk_get_rate(wiz->input_clks[WIZ_EXT_REFCLK]);  in wiz_clock_init()
1118 		regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);  in wiz_clock_init()
1120 		regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);  in wiz_clock_init()
1123 static int wiz_clock_probe(struct wiz *wiz, struct device_node *node)  in wiz_clock_probe()  argument
1125 	const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;  in wiz_clock_probe()
1126 	struct device *dev = wiz->dev;  in wiz_clock_probe()
1138 	wiz->input_clks[WIZ_CORE_REFCLK] = clk;  in wiz_clock_probe()
1140 	if (wiz->data->pma_cmn_refclk1_int_mode) {  in wiz_clock_probe()
1146 		wiz->input_clks[WIZ_CORE_REFCLK1] = clk;  in wiz_clock_probe()
1154 	wiz->input_clks[WIZ_EXT_REFCLK] = clk;  in wiz_clock_probe()
1156 	wiz_clock_init(wiz);  in wiz_clock_probe()
1158 	switch (wiz->type) {  in wiz_clock_probe()
1163 		ret = wiz_clock_register(wiz);  in wiz_clock_probe()
1165 			return dev_err_probe(dev, ret, "Failed to register wiz clocks\n");  in wiz_clock_probe()
1180 		ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i],  in wiz_clock_probe()
1191 	for (i = 0; i < wiz->clk_div_sel_num; i++) {  in wiz_clock_probe()
1199 		ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i],  in wiz_clock_probe()
1211 	wiz_clock_cleanup(wiz, node);  in wiz_clock_probe()
1220 	struct wiz *wiz = dev_get_drvdata(dev);  in wiz_phy_reset_assert()  local
1224 		ret = regmap_field_write(wiz->phy_reset_n, false);  in wiz_phy_reset_assert()
1228 	ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);  in wiz_phy_reset_assert()
1232 static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)  in wiz_phy_fullrt_div()  argument
1234 	switch (wiz->type) {  in wiz_phy_fullrt_div()
1236 		if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)  in wiz_phy_fullrt_div()
1237 			return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);  in wiz_phy_fullrt_div()
1245 		if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)  in wiz_phy_fullrt_div()
1246 			return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);  in wiz_phy_fullrt_div()
1258 	struct wiz *wiz = dev_get_drvdata(dev);  in wiz_phy_reset_deassert()  local
1263 		if (wiz->gpio_typec_dir) {  in wiz_phy_reset_deassert()
1264 			if (wiz->typec_dir_delay)  in wiz_phy_reset_deassert()
1265 				msleep_interruptible(wiz->typec_dir_delay);  in wiz_phy_reset_deassert()
1267 			if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))  in wiz_phy_reset_deassert()
1268 				regmap_field_write(wiz->typec_ln10_swap, 1);  in wiz_phy_reset_deassert()
1270 				regmap_field_write(wiz->typec_ln10_swap, 0);  in wiz_phy_reset_deassert()
1276 			u32 num_lanes = wiz->num_lanes;  in wiz_phy_reset_deassert()
1280 				if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) {  in wiz_phy_reset_deassert()
1281 					switch (wiz->master_lane_num[i]) {  in wiz_phy_reset_deassert()
1283 						regmap_field_write(wiz->typec_ln10_swap, 1);  in wiz_phy_reset_deassert()
1286 						regmap_field_write(wiz->typec_ln23_swap, 1);  in wiz_phy_reset_deassert()
1297 		ret = regmap_field_write(wiz->phy_reset_n, true);  in wiz_phy_reset_deassert()
1301 	ret = wiz_phy_fullrt_div(wiz, id - 1);  in wiz_phy_reset_deassert()
1305 	if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)  in wiz_phy_reset_deassert()
1306 		ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);  in wiz_phy_reset_deassert()
1308 		ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);  in wiz_phy_reset_deassert()
1384 		.compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data,
1387 		.compatible = "ti,j721e-wiz-10g", .data = &j721e_10g_data,
1390 		.compatible = "ti,am64-wiz-10g", .data = &am64_10g_data,
1393 		.compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data,
1396 		.compatible = "ti,j784s4-wiz-10g", .data = &j784s4_10g_data,
1399 		.compatible = "ti,j721s2-wiz-10g", .data = &j721s2_10g_data,
1405 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)  in wiz_get_lane_phy_types()  argument
1437 			wiz->master_lane_num[i] = reg;  in wiz_get_lane_phy_types()
1438 			wiz->lane_phy_type[i] = phy_type;  in wiz_get_lane_phy_types()
1456 	struct wiz *wiz;  in wiz_probe()  local
1461 	wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL);  in wiz_probe()
1462 	if (!wiz)  in wiz_probe()
1471 	wiz->data = data;  in wiz_probe()
1472 	wiz->type = data->type;  in wiz_probe()
1499 	wiz->scm_regmap = syscon_regmap_lookup_by_phandle(node, "ti,scm");  in wiz_probe()
1500 	if (IS_ERR(wiz->scm_regmap)) {  in wiz_probe()
1501 		if (wiz->type == J7200_WIZ_10G) {  in wiz_probe()
1507 		wiz->scm_regmap = NULL;  in wiz_probe()
1522 	wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",  in wiz_probe()
1524 	if (IS_ERR(wiz->gpio_typec_dir)) {  in wiz_probe()
1525 		ret = PTR_ERR(wiz->gpio_typec_dir);  in wiz_probe()
1532 	if (wiz->gpio_typec_dir) {  in wiz_probe()
1534 					   &wiz->typec_dir_delay);  in wiz_probe()
1542 			wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN;  in wiz_probe()
1544 		if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN ||  in wiz_probe()
1545 		    wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) {  in wiz_probe()
1552 	ret = wiz_get_lane_phy_types(dev, wiz);  in wiz_probe()
1556 	wiz->dev = dev;  in wiz_probe()
1557 	wiz->regmap = regmap;  in wiz_probe()
1558 	wiz->num_lanes = num_lanes;  in wiz_probe()
1559 	wiz->clk_mux_sel = data->clk_mux_sel;  in wiz_probe()
1560 	wiz->clk_div_sel = clk_div_sel;  in wiz_probe()
1561 	wiz->clk_div_sel_num = data->clk_div_sel_num;  in wiz_probe()
1563 	platform_set_drvdata(pdev, wiz);  in wiz_probe()
1565 	ret = wiz_regfield_init(wiz);  in wiz_probe()
1572 	if (wiz->scm_regmap)  in wiz_probe()
1573 		regmap_field_write(wiz->sup_legacy_clk_override, 1);  in wiz_probe()
1575 	phy_reset_dev = &wiz->wiz_phy_reset_dev;  in wiz_probe()
1596 	ret = wiz_clock_probe(wiz, node);  in wiz_probe()
1602 	for (i = 0; i < wiz->num_lanes; i++) {  in wiz_probe()
1603 		regmap_field_read(wiz->p_enable[i], &val);  in wiz_probe()
1611 		ret = wiz_init(wiz);  in wiz_probe()
1613 			dev_err(dev, "WIZ initialization failed\n");  in wiz_probe()
1624 	wiz->serdes_pdev = serdes_pdev;  in wiz_probe()
1630 	wiz_clock_cleanup(wiz, node);  in wiz_probe()
1647 	struct wiz *wiz;  in wiz_remove()  local
1649 	wiz = dev_get_drvdata(dev);  in wiz_remove()
1650 	serdes_pdev = wiz->serdes_pdev;  in wiz_remove()
1653 	wiz_clock_cleanup(wiz, node);  in wiz_remove()
1661 	struct wiz *wiz = dev_get_drvdata(dev);  in wiz_resume_noirq()  local
1665 	if (wiz->sup_legacy_clk_override)  in wiz_resume_noirq()
1666 		regmap_field_write(wiz->sup_legacy_clk_override, 1);  in wiz_resume_noirq()
1668 	wiz_clock_init(wiz);  in wiz_resume_noirq()
1670 	ret = wiz_init(wiz);  in wiz_resume_noirq()
1672 		dev_err(dev, "WIZ initialization failed\n");  in wiz_resume_noirq()
1679 	wiz_clock_cleanup(wiz, node);  in wiz_resume_noirq()
1690 		.name	= "wiz",
1698 MODULE_DESCRIPTION("TI J721E WIZ driver");