1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (c) 2016-2022, NVIDIA CORPORATION.  All rights reserved.
18 #include "xusb.h"
21 #define HS_CURR_LEVEL_PADX_SHIFT(x)	((x) ? (11 + (x - 1) * 6) : 0)
31 /* XUSB PADCTL registers */
121 /* XUSB AO registers */
274 	/* padctl context */
280 	writel(value, priv->ao_regs + offset);  in ao_writel()
285 	return readl(priv->ao_regs + offset);  in ao_readl()
289 to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl)  in to_tegra186_xusb_padctl()  argument
291 	return container_of(padctl, struct tegra186_xusb_padctl, base);  in to_tegra186_xusb_padctl()
304 		return ERR_PTR(-ENOMEM);  in tegra186_usb2_lane_probe()
306 	INIT_LIST_HEAD(&usb2->base.list);  in tegra186_usb2_lane_probe()
307 	usb2->base.soc = &pad->soc->lanes[index];  in tegra186_usb2_lane_probe()
308 	usb2->base.index = index;  in tegra186_usb2_lane_probe()
309 	usb2->base.pad = pad;  in tegra186_usb2_lane_probe()
310 	usb2->base.np = np;  in tegra186_usb2_lane_probe()
312 	err = tegra_xusb_lane_parse_dt(&usb2->base, np);  in tegra186_usb2_lane_probe()
318 	return &usb2->base;  in tegra186_usb2_lane_probe()
331 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_enable_phy_sleepwalk()  local
332 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);  in tegra186_utmi_enable_phy_sleepwalk()
333 	unsigned int index = lane->index;  in tegra186_utmi_enable_phy_sleepwalk()
336 	mutex_lock(&padctl->lock);  in tegra186_utmi_enable_phy_sleepwalk()
413 	/* setup the pull-ups and pull-downs of the signals during the four  in tegra186_utmi_enable_phy_sleepwalk()
424 		/* J state: D+/D- = high/low, K state: D+/D- = low/high */  in tegra186_utmi_enable_phy_sleepwalk()
428 		if (padctl->soc->supports_lp_cfg_en)  in tegra186_utmi_enable_phy_sleepwalk()
433 		/* J state: D+/D- = low/high, K state: D+/D- = high/low */  in tegra186_utmi_enable_phy_sleepwalk()
437 		if (padctl->soc->supports_lp_cfg_en)  in tegra186_utmi_enable_phy_sleepwalk()
472 	mutex_unlock(&padctl->lock);  in tegra186_utmi_enable_phy_sleepwalk()
479 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_disable_phy_sleepwalk()  local
480 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);  in tegra186_utmi_disable_phy_sleepwalk()
481 	unsigned int index = lane->index;  in tegra186_utmi_disable_phy_sleepwalk()
484 	mutex_lock(&padctl->lock);  in tegra186_utmi_disable_phy_sleepwalk()
491 	/* switch the electric control of the USB2.0 pad to XUSB vcore logic */  in tegra186_utmi_disable_phy_sleepwalk()
503 	if (padctl->soc->supports_lp_cfg_en) {  in tegra186_utmi_disable_phy_sleepwalk()
520 	mutex_unlock(&padctl->lock);  in tegra186_utmi_disable_phy_sleepwalk()
527 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_enable_phy_wake()  local
528 	unsigned int index = lane->index;  in tegra186_utmi_enable_phy_wake()
531 	mutex_lock(&padctl->lock);  in tegra186_utmi_enable_phy_wake()
533 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra186_utmi_enable_phy_wake()
536 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra186_utmi_enable_phy_wake()
540 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra186_utmi_enable_phy_wake()
543 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra186_utmi_enable_phy_wake()
545 	mutex_unlock(&padctl->lock);  in tegra186_utmi_enable_phy_wake()
552 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_disable_phy_wake()  local
553 	unsigned int index = lane->index;  in tegra186_utmi_disable_phy_wake()
556 	mutex_lock(&padctl->lock);  in tegra186_utmi_disable_phy_wake()
558 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra186_utmi_disable_phy_wake()
561 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra186_utmi_disable_phy_wake()
565 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra186_utmi_disable_phy_wake()
568 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra186_utmi_disable_phy_wake()
570 	mutex_unlock(&padctl->lock);  in tegra186_utmi_disable_phy_wake()
577 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_phy_remote_wake_detected()  local
578 	unsigned int index = lane->index;  in tegra186_utmi_phy_remote_wake_detected()
581 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra186_utmi_phy_remote_wake_detected()
599 static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl)  in tegra186_utmi_bias_pad_power_on()  argument
601 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);  in tegra186_utmi_bias_pad_power_on()
602 	struct device *dev = padctl->dev;  in tegra186_utmi_bias_pad_power_on()
606 	mutex_lock(&padctl->lock);  in tegra186_utmi_bias_pad_power_on()
608 	if (priv->bias_pad_enable++ > 0) {  in tegra186_utmi_bias_pad_power_on()
609 		mutex_unlock(&padctl->lock);  in tegra186_utmi_bias_pad_power_on()
613 	err = clk_prepare_enable(priv->usb2_trk_clk);  in tegra186_utmi_bias_pad_power_on()
617 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);  in tegra186_utmi_bias_pad_power_on()
622 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);  in tegra186_utmi_bias_pad_power_on()
624 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);  in tegra186_utmi_bias_pad_power_on()
627 	value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch);  in tegra186_utmi_bias_pad_power_on()
628 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);  in tegra186_utmi_bias_pad_power_on()
632 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);  in tegra186_utmi_bias_pad_power_on()
634 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);  in tegra186_utmi_bias_pad_power_on()
636 	if (padctl->soc->poll_trk_completed) {  in tegra186_utmi_bias_pad_power_on()
637 		err = padctl_readl_poll(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1,  in tegra186_utmi_bias_pad_power_on()
646 		value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);  in tegra186_utmi_bias_pad_power_on()
648 		padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);  in tegra186_utmi_bias_pad_power_on()
653 	if (padctl->soc->trk_hw_mode) {  in tegra186_utmi_bias_pad_power_on()
654 		value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);  in tegra186_utmi_bias_pad_power_on()
657 		padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);  in tegra186_utmi_bias_pad_power_on()
659 		clk_disable_unprepare(priv->usb2_trk_clk);  in tegra186_utmi_bias_pad_power_on()
662 	mutex_unlock(&padctl->lock);  in tegra186_utmi_bias_pad_power_on()
665 static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl)  in tegra186_utmi_bias_pad_power_off()  argument
667 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);  in tegra186_utmi_bias_pad_power_off()
670 	mutex_lock(&padctl->lock);  in tegra186_utmi_bias_pad_power_off()
672 	if (WARN_ON(priv->bias_pad_enable == 0)) {  in tegra186_utmi_bias_pad_power_off()
673 		mutex_unlock(&padctl->lock);  in tegra186_utmi_bias_pad_power_off()
677 	if (--priv->bias_pad_enable > 0) {  in tegra186_utmi_bias_pad_power_off()
678 		mutex_unlock(&padctl->lock);  in tegra186_utmi_bias_pad_power_off()
682 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);  in tegra186_utmi_bias_pad_power_off()
684 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);  in tegra186_utmi_bias_pad_power_off()
686 	if (padctl->soc->trk_hw_mode) {  in tegra186_utmi_bias_pad_power_off()
687 		value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);  in tegra186_utmi_bias_pad_power_off()
689 		padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);  in tegra186_utmi_bias_pad_power_off()
690 		clk_disable_unprepare(priv->usb2_trk_clk);  in tegra186_utmi_bias_pad_power_off()
693 	mutex_unlock(&padctl->lock);  in tegra186_utmi_bias_pad_power_off()
699 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_pad_power_on()  local
701 	struct device *dev = padctl->dev;  in tegra186_utmi_pad_power_on()
702 	unsigned int index = lane->index;  in tegra186_utmi_pad_power_on()
708 	port = tegra_xusb_find_usb2_port(padctl, index);  in tegra186_utmi_pad_power_on()
716 	tegra186_utmi_bias_pad_power_on(padctl);  in tegra186_utmi_pad_power_on()
720 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));  in tegra186_utmi_pad_power_on()
722 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));  in tegra186_utmi_pad_power_on()
724 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));  in tegra186_utmi_pad_power_on()
726 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));  in tegra186_utmi_pad_power_on()
732 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_pad_power_down()  local
733 	unsigned int index = lane->index;  in tegra186_utmi_pad_power_down()
739 	dev_dbg(padctl->dev, "power down UTMI pad %u\n", index);  in tegra186_utmi_pad_power_down()
741 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));  in tegra186_utmi_pad_power_down()
743 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));  in tegra186_utmi_pad_power_down()
745 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));  in tegra186_utmi_pad_power_down()
747 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));  in tegra186_utmi_pad_power_down()
751 	tegra186_utmi_bias_pad_power_off(padctl);  in tegra186_utmi_pad_power_down()
754 static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,  in tegra186_xusb_padctl_vbus_override()  argument
759 	dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");  in tegra186_xusb_padctl_vbus_override()
761 	value = padctl_readl(padctl, USB2_VBUS_ID);  in tegra186_xusb_padctl_vbus_override()
771 	padctl_writel(padctl, value, USB2_VBUS_ID);  in tegra186_xusb_padctl_vbus_override()
776 static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,  in tegra186_xusb_padctl_id_override()  argument
781 	dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");  in tegra186_xusb_padctl_id_override()
783 	value = padctl_readl(padctl, USB2_VBUS_ID);  in tegra186_xusb_padctl_id_override()
788 			padctl_writel(padctl, value, USB2_VBUS_ID);  in tegra186_xusb_padctl_id_override()
791 			value = padctl_readl(padctl, USB2_VBUS_ID);  in tegra186_xusb_padctl_id_override()
801 	padctl_writel(padctl, value, USB2_VBUS_ID);  in tegra186_xusb_padctl_id_override()
810 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_phy_set_mode()  local
811 	struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,  in tegra186_utmi_phy_set_mode()
812 								lane->index);  in tegra186_utmi_phy_set_mode()
815 	mutex_lock(&padctl->lock);  in tegra186_utmi_phy_set_mode()
817 	dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);  in tegra186_utmi_phy_set_mode()
821 			tegra186_xusb_padctl_id_override(padctl, true);  in tegra186_utmi_phy_set_mode()
823 			err = regulator_enable(port->supply);  in tegra186_utmi_phy_set_mode()
825 			tegra186_xusb_padctl_vbus_override(padctl, true);  in tegra186_utmi_phy_set_mode()
832 			if (regulator_is_enabled(port->supply))  in tegra186_utmi_phy_set_mode()
833 				regulator_disable(port->supply);  in tegra186_utmi_phy_set_mode()
835 			tegra186_xusb_padctl_id_override(padctl, false);  in tegra186_utmi_phy_set_mode()
836 			tegra186_xusb_padctl_vbus_override(padctl, false);  in tegra186_utmi_phy_set_mode()
840 	mutex_unlock(&padctl->lock);  in tegra186_utmi_phy_set_mode()
849 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_phy_power_on()  local
850 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);  in tegra186_utmi_phy_power_on()
852 	unsigned int index = lane->index;  in tegra186_utmi_phy_power_on()
853 	struct device *dev = padctl->dev;  in tegra186_utmi_phy_power_on()
856 	port = tegra_xusb_find_usb2_port(padctl, index);  in tegra186_utmi_phy_power_on()
859 		return -ENODEV;  in tegra186_utmi_phy_power_on()
862 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);  in tegra186_utmi_phy_power_on()
865 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);  in tegra186_utmi_phy_power_on()
867 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);  in tegra186_utmi_phy_power_on()
870 	if (port->mode == USB_DR_MODE_UNKNOWN)  in tegra186_utmi_phy_power_on()
872 	else if (port->mode == USB_DR_MODE_PERIPHERAL)  in tegra186_utmi_phy_power_on()
874 	else if (port->mode == USB_DR_MODE_HOST)  in tegra186_utmi_phy_power_on()
876 	else if (port->mode == USB_DR_MODE_OTG)  in tegra186_utmi_phy_power_on()
879 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);  in tegra186_utmi_phy_power_on()
881 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));  in tegra186_utmi_phy_power_on()
886 	if (usb2->hs_curr_level_offset) {  in tegra186_utmi_phy_power_on()
889 		hs_current_level = (int)priv->calib.hs_curr_level[index] +  in tegra186_utmi_phy_power_on()
890 						usb2->hs_curr_level_offset;  in tegra186_utmi_phy_power_on()
899 		value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]);  in tegra186_utmi_phy_power_on()
902 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));  in tegra186_utmi_phy_power_on()
904 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));  in tegra186_utmi_phy_power_on()
906 	value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj);  in tegra186_utmi_phy_power_on()
908 	value |= RPD_CTRL(priv->calib.rpd_ctrl);  in tegra186_utmi_phy_power_on()
909 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));  in tegra186_utmi_phy_power_on()
926 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_phy_init()  local
928 	unsigned int index = lane->index;  in tegra186_utmi_phy_init()
929 	struct device *dev = padctl->dev;  in tegra186_utmi_phy_init()
933 	port = tegra_xusb_find_usb2_port(padctl, index);  in tegra186_utmi_phy_init()
936 		return -ENODEV;  in tegra186_utmi_phy_init()
939 	if (port->mode == USB_DR_MODE_OTG ||  in tegra186_utmi_phy_init()
940 	    port->mode == USB_DR_MODE_PERIPHERAL) {  in tegra186_utmi_phy_init()
942 		reg = padctl_readl(padctl, USB2_VBUS_ID);  in tegra186_utmi_phy_init()
946 		padctl_writel(padctl, reg, USB2_VBUS_ID);  in tegra186_utmi_phy_init()
949 	if (port->supply && port->mode == USB_DR_MODE_HOST) {  in tegra186_utmi_phy_init()
950 		err = regulator_enable(port->supply);  in tegra186_utmi_phy_init()
964 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_phy_exit()  local
966 	unsigned int index = lane->index;  in tegra186_utmi_phy_exit()
967 	struct device *dev = padctl->dev;  in tegra186_utmi_phy_exit()
970 	port = tegra_xusb_find_usb2_port(padctl, index);  in tegra186_utmi_phy_exit()
973 		return -ENODEV;  in tegra186_utmi_phy_exit()
976 	if (port->supply && port->mode == USB_DR_MODE_HOST) {  in tegra186_utmi_phy_exit()
977 		err = regulator_disable(port->supply);  in tegra186_utmi_phy_exit()
998 tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl,  in tegra186_usb2_pad_probe()  argument
1002 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);  in tegra186_usb2_pad_probe()
1009 		return ERR_PTR(-ENOMEM);  in tegra186_usb2_pad_probe()
1011 	pad = &usb2->base;  in tegra186_usb2_pad_probe()
1012 	pad->ops = &tegra186_usb2_lane_ops;  in tegra186_usb2_pad_probe()
1013 	pad->soc = soc;  in tegra186_usb2_pad_probe()
1015 	err = tegra_xusb_pad_init(pad, padctl, np);  in tegra186_usb2_pad_probe()
1021 	priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk");  in tegra186_usb2_pad_probe()
1022 	if (IS_ERR(priv->usb2_trk_clk)) {  in tegra186_usb2_pad_probe()
1023 		err = PTR_ERR(priv->usb2_trk_clk);  in tegra186_usb2_pad_probe()
1024 		dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err);  in tegra186_usb2_pad_probe()
1032 	dev_set_drvdata(&pad->dev, pad);  in tegra186_usb2_pad_probe()
1037 	device_unregister(&pad->dev);  in tegra186_usb2_pad_probe()
1055 	"xusb",
1070 	return tegra_xusb_find_lane(port->padctl, "usb2", port->index);  in tegra186_usb2_port_map()
1091 		return ERR_PTR(-ENOMEM);  in tegra186_usb3_lane_probe()
1093 	INIT_LIST_HEAD(&usb3->base.list);  in tegra186_usb3_lane_probe()
1094 	usb3->base.soc = &pad->soc->lanes[index];  in tegra186_usb3_lane_probe()
1095 	usb3->base.index = index;  in tegra186_usb3_lane_probe()
1096 	usb3->base.pad = pad;  in tegra186_usb3_lane_probe()
1097 	usb3->base.np = np;  in tegra186_usb3_lane_probe()
1099 	err = tegra_xusb_lane_parse_dt(&usb3->base, np);  in tegra186_usb3_lane_probe()
1105 	return &usb3->base;  in tegra186_usb3_lane_probe()
1118 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_enable_phy_sleepwalk()  local
1119 	unsigned int index = lane->index;  in tegra186_usb3_enable_phy_sleepwalk()
1122 	mutex_lock(&padctl->lock);  in tegra186_usb3_enable_phy_sleepwalk()
1124 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_enable_phy_sleepwalk()
1126 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_enable_phy_sleepwalk()
1130 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_enable_phy_sleepwalk()
1132 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_enable_phy_sleepwalk()
1136 	mutex_unlock(&padctl->lock);  in tegra186_usb3_enable_phy_sleepwalk()
1143 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_disable_phy_sleepwalk()  local
1144 	unsigned int index = lane->index;  in tegra186_usb3_disable_phy_sleepwalk()
1147 	mutex_lock(&padctl->lock);  in tegra186_usb3_disable_phy_sleepwalk()
1149 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_disable_phy_sleepwalk()
1151 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_disable_phy_sleepwalk()
1155 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_disable_phy_sleepwalk()
1157 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_disable_phy_sleepwalk()
1159 	mutex_unlock(&padctl->lock);  in tegra186_usb3_disable_phy_sleepwalk()
1166 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_enable_phy_wake()  local
1167 	unsigned int index = lane->index;  in tegra186_usb3_enable_phy_wake()
1170 	mutex_lock(&padctl->lock);  in tegra186_usb3_enable_phy_wake()
1172 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra186_usb3_enable_phy_wake()
1175 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra186_usb3_enable_phy_wake()
1179 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra186_usb3_enable_phy_wake()
1182 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra186_usb3_enable_phy_wake()
1184 	mutex_unlock(&padctl->lock);  in tegra186_usb3_enable_phy_wake()
1191 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_disable_phy_wake()  local
1192 	unsigned int index = lane->index;  in tegra186_usb3_disable_phy_wake()
1195 	mutex_lock(&padctl->lock);  in tegra186_usb3_disable_phy_wake()
1197 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra186_usb3_disable_phy_wake()
1200 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra186_usb3_disable_phy_wake()
1204 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra186_usb3_disable_phy_wake()
1207 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra186_usb3_disable_phy_wake()
1209 	mutex_unlock(&padctl->lock);  in tegra186_usb3_disable_phy_wake()
1216 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_phy_remote_wake_detected()  local
1217 	unsigned int index = lane->index;  in tegra186_usb3_phy_remote_wake_detected()
1220 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra186_usb3_phy_remote_wake_detected()
1249 	return tegra_xusb_find_lane(port->padctl, "usb3", port->index);  in tegra186_usb3_port_map()
1262 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_phy_power_on()  local
1265 	unsigned int index = lane->index;  in tegra186_usb3_phy_power_on()
1266 	struct device *dev = padctl->dev;  in tegra186_usb3_phy_power_on()
1269 	port = tegra_xusb_find_usb3_port(padctl, index);  in tegra186_usb3_phy_power_on()
1272 		return -ENODEV;  in tegra186_usb3_phy_power_on()
1275 	usb2 = tegra_xusb_find_usb2_port(padctl, port->port);  in tegra186_usb3_phy_power_on()
1279 		return -ENODEV;  in tegra186_usb3_phy_power_on()
1282 	mutex_lock(&padctl->lock);  in tegra186_usb3_phy_power_on()
1284 	value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);  in tegra186_usb3_phy_power_on()
1287 	if (usb2->mode == USB_DR_MODE_UNKNOWN)  in tegra186_usb3_phy_power_on()
1289 	else if (usb2->mode == USB_DR_MODE_PERIPHERAL)  in tegra186_usb3_phy_power_on()
1291 	else if (usb2->mode == USB_DR_MODE_HOST)  in tegra186_usb3_phy_power_on()
1293 	else if (usb2->mode == USB_DR_MODE_OTG)  in tegra186_usb3_phy_power_on()
1296 	padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP);  in tegra186_usb3_phy_power_on()
1298 	if (padctl->soc->supports_gen2 && port->disable_gen2) {  in tegra186_usb3_phy_power_on()
1299 		value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG);  in tegra186_usb3_phy_power_on()
1304 		padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG);  in tegra186_usb3_phy_power_on()
1307 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_phy_power_on()
1309 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_phy_power_on()
1313 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_phy_power_on()
1315 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_phy_power_on()
1319 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_phy_power_on()
1321 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_phy_power_on()
1323 	mutex_unlock(&padctl->lock);  in tegra186_usb3_phy_power_on()
1331 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_phy_power_off()  local
1333 	unsigned int index = lane->index;  in tegra186_usb3_phy_power_off()
1334 	struct device *dev = padctl->dev;  in tegra186_usb3_phy_power_off()
1337 	port = tegra_xusb_find_usb3_port(padctl, index);  in tegra186_usb3_phy_power_off()
1340 		return -ENODEV;  in tegra186_usb3_phy_power_off()
1343 	mutex_lock(&padctl->lock);  in tegra186_usb3_phy_power_off()
1345 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_phy_power_off()
1347 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_phy_power_off()
1351 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_phy_power_off()
1353 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_phy_power_off()
1357 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_phy_power_off()
1359 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);  in tegra186_usb3_phy_power_off()
1361 	mutex_unlock(&padctl->lock);  in tegra186_usb3_phy_power_off()
1385 tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl,  in tegra186_usb3_pad_probe()  argument
1395 		return ERR_PTR(-ENOMEM);  in tegra186_usb3_pad_probe()
1397 	pad = &usb3->base;  in tegra186_usb3_pad_probe()
1398 	pad->ops = &tegra186_usb3_lane_ops;  in tegra186_usb3_pad_probe()
1399 	pad->soc = soc;  in tegra186_usb3_pad_probe()
1401 	err = tegra_xusb_pad_init(pad, padctl, np);  in tegra186_usb3_pad_probe()
1411 	dev_set_drvdata(&pad->dev, pad);  in tegra186_usb3_pad_probe()
1416 	device_unregister(&pad->dev);  in tegra186_usb3_pad_probe()
1434 	"xusb",
1438 tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)  in tegra186_xusb_read_fuse_calibration()  argument
1440 	struct device *dev = padctl->base.dev;  in tegra186_xusb_read_fuse_calibration()
1445 	count = padctl->base.soc->ports.usb2.count;  in tegra186_xusb_read_fuse_calibration()
1449 		return -ENOMEM;  in tegra186_xusb_read_fuse_calibration()
1462 	padctl->calib.hs_curr_level = level;  in tegra186_xusb_read_fuse_calibration()
1464 	padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &  in tegra186_xusb_read_fuse_calibration()
1466 	padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &  in tegra186_xusb_read_fuse_calibration()
1477 	padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;  in tegra186_xusb_read_fuse_calibration()
1493 		return ERR_PTR(-ENOMEM);  in tegra186_xusb_padctl_probe()
1495 	priv->base.dev = dev;  in tegra186_xusb_padctl_probe()
1496 	priv->base.soc = soc;  in tegra186_xusb_padctl_probe()
1499 	priv->ao_regs = devm_ioremap_resource(dev, res);  in tegra186_xusb_padctl_probe()
1500 	if (IS_ERR(priv->ao_regs))  in tegra186_xusb_padctl_probe()
1501 		return ERR_CAST(priv->ao_regs);  in tegra186_xusb_padctl_probe()
1507 	return &priv->base;  in tegra186_xusb_padctl_probe()
1510 static void tegra186_xusb_padctl_save(struct tegra_xusb_padctl *padctl)  in tegra186_xusb_padctl_save()  argument
1512 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);  in tegra186_xusb_padctl_save()
1514 	priv->context.vbus_id = padctl_readl(padctl, USB2_VBUS_ID);  in tegra186_xusb_padctl_save()
1515 	priv->context.usb2_pad_mux = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);  in tegra186_xusb_padctl_save()
1516 	priv->context.usb2_port_cap = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);  in tegra186_xusb_padctl_save()
1517 	priv->context.ss_port_cap = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);  in tegra186_xusb_padctl_save()
1520 static void tegra186_xusb_padctl_restore(struct tegra_xusb_padctl *padctl)  in tegra186_xusb_padctl_restore()  argument
1522 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);  in tegra186_xusb_padctl_restore()
1524 	padctl_writel(padctl, priv->context.usb2_pad_mux, XUSB_PADCTL_USB2_PAD_MUX);  in tegra186_xusb_padctl_restore()
1525 	padctl_writel(padctl, priv->context.usb2_port_cap, XUSB_PADCTL_USB2_PORT_CAP);  in tegra186_xusb_padctl_restore()
1526 	padctl_writel(padctl, priv->context.ss_port_cap, XUSB_PADCTL_SS_PORT_CAP);  in tegra186_xusb_padctl_restore()
1527 	padctl_writel(padctl, priv->context.vbus_id, USB2_VBUS_ID);  in tegra186_xusb_padctl_restore()
1530 static int tegra186_xusb_padctl_suspend_noirq(struct tegra_xusb_padctl *padctl)  in tegra186_xusb_padctl_suspend_noirq()  argument
1532 	tegra186_xusb_padctl_save(padctl);  in tegra186_xusb_padctl_suspend_noirq()
1537 static int tegra186_xusb_padctl_resume_noirq(struct tegra_xusb_padctl *padctl)  in tegra186_xusb_padctl_resume_noirq()  argument
1539 	tegra186_xusb_padctl_restore(padctl);  in tegra186_xusb_padctl_resume_noirq()
1544 static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)  in tegra186_xusb_padctl_remove()  argument
1560 	"avdd-pll-erefeut",
1561 	"avdd-usb",
1562 	"vclamp-usb",
1563 	"vddio-hsic",
1567 	TEGRA186_LANE("usb2-0", 0,  0, 0, usb2),
1568 	TEGRA186_LANE("usb2-1", 0,  0, 0, usb2),
1569 	TEGRA186_LANE("usb2-2", 0,  0, 0, usb2),
1580 	TEGRA186_LANE("usb3-0", 0,  0, 0, usb3),
1581 	TEGRA186_LANE("usb3-1", 0,  0, 0, usb3),
1582 	TEGRA186_LANE("usb3-2", 0,  0, 0, usb3),
1629 	"avdd-usb",
1630 	"vclamp-usb",
1634 	TEGRA186_LANE("usb2-0", 0,  0, 0, usb2),
1635 	TEGRA186_LANE("usb2-1", 0,  0, 0, usb2),
1636 	TEGRA186_LANE("usb2-2", 0,  0, 0, usb2),
1637 	TEGRA186_LANE("usb2-3", 0,  0, 0, usb2),
1648 	TEGRA186_LANE("usb3-0", 0,  0, 0, usb3),
1649 	TEGRA186_LANE("usb3-1", 0,  0, 0, usb3),
1650 	TEGRA186_LANE("usb3-2", 0,  0, 0, usb3),
1651 	TEGRA186_LANE("usb3-3", 0,  0, 0, usb3),
1712 MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver");