1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (c) 2016-2022, NVIDIA CORPORATION.  All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x)	((x) ? (11 + (x - 1) * 6) : 0)
22 #define HS_CURR_LEVEL_PAD_MASK		0x3f
24 #define HS_TERM_RANGE_ADJ_MASK		0xf
26 #define HS_SQUELCH_MASK			0x7
28 #define RPD_CTRL_SHIFT			0
29 #define RPD_CTRL_MASK			0x1f
32 #define XUSB_PADCTL_USB2_PAD_MUX	0x4
34 #define  USB2_PORT_MASK			0x3
37 #define  HSIC_PORT_MASK			0x1
38 #define   PORT_HSIC			0
40 #define XUSB_PADCTL_USB2_PORT_CAP	0x8
41 #define XUSB_PADCTL_SS_PORT_CAP		0xc
43 #define  PORT_CAP_MASK			0x3
44 #define   PORT_CAP_DISABLED		0x0
45 #define   PORT_CAP_HOST			0x1
46 #define   PORT_CAP_DEVICE		0x2
47 #define   PORT_CAP_OTG			0x3
49 #define XUSB_PADCTL_ELPG_PROGRAM		0x20
57 	(USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) |	\
58 	USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) |		\
60 	USB2_HSIC_PORT_WAKEUP_EVENT(0))
62 #define XUSB_PADCTL_ELPG_PROGRAM_1		0x24
63 #define  SSPX_ELPG_CLAMP_EN(x)			BIT(0 + (x) * 3)
66 #define XUSB_PADCTL_SS_PORT_CFG			0x2c
68 #define   PORTX_SPEED_SUPPORT_MASK		(0x3)
69 #define     PORT_SPEED_SUPPORT_GEN1		(0x0)
71 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x)	(0x88 + (x) * 0x40)
72 #define  HS_CURR_LEVEL(x)			((x) & 0x3f)
79 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x)	(0x8c + (x) * 0x40)
81 #define  TERM_RANGE_ADJ(x)			(((x) & 0xf) << 3)
82 #define  RPD_CTRL(x)				(((x) & 0x1f) << 26)
84 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0		0x284
86 #define  HS_SQUELCH_LEVEL(x)			(((x) & 0x7) << 0)
88 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1		0x288
89 #define  USB2_TRK_START_TIMER(x)		(((x) & 0x7f) << 12)
90 #define  USB2_TRK_DONE_RESET_TIMER(x)		(((x) & 0x7f) << 19)
94 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL2		0x28c
95 #define  USB2_TRK_HW_MODE			BIT(0)
98 #define XUSB_PADCTL_HSIC_PADX_CTL0(x)		(0x300 + (x) * 0x20)
110 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL0		0x340
111 #define  HSIC_TRK_START_TIMER(x)		(((x) & 0x7f) << 5)
112 #define  HSIC_TRK_DONE_RESET_TIMER(x)		(((x) & 0x7f) << 12)
115 #define USB2_VBUS_ID				0x360
117 #define  ID_OVERRIDE(x)				(((x) & 0xf) << 18)
119 #define  ID_OVERRIDE_GROUNDED			ID_OVERRIDE(0)
122 #define XUSB_AO_USB_DEBOUNCE_DEL		(0x4)
123 #define   UHSIC_LINE_DEB_CNT(x)			(((x) & 0xf) << 4)
124 #define   UTMIP_LINE_DEB_CNT(x)			((x) & 0xf)
126 #define XUSB_AO_UTMIP_TRIGGERS(x)		(0x40 + (x) * 4)
127 #define   CLR_WALK_PTR				BIT(0)
131 #define XUSB_AO_UHSIC_TRIGGERS(x)		(0x60 + (x) * 4)
132 #define   HSIC_CLR_WALK_PTR			BIT(0)
136 #define XUSB_AO_UTMIP_SAVED_STATE(x)		(0x70 + (x) * 4)
137 #define   SPEED(x)				((x) & 0x3)
138 #define     UTMI_HS				SPEED(0)
143 #define XUSB_AO_UHSIC_SAVED_STATE(x)		(0x90 + (x) * 4)
144 #define   MODE(x)				((x) & 0x1)
145 #define   MODE_HS				MODE(0)
148 #define XUSB_AO_UTMIP_SLEEPWALK_STATUS(x)	(0xa0 + (x) * 4)
150 #define XUSB_AO_UTMIP_SLEEPWALK_CFG(x)		(0xd0 + (x) * 4)
151 #define XUSB_AO_UHSIC_SLEEPWALK_CFG(x)		(0xf0 + (x) * 4)
152 #define   FAKE_USBOP_VAL			BIT(0)
156 #define   FAKE_STROBE_VAL			BIT(0)
163 #define   WAKE_VAL(x)				(((x) & 0xf) << 17)
170 #define XUSB_AO_UTMIP_SLEEPWALK(x)		(0x100 + (x) * 4)
172 #define   USBOP_RPD_A				BIT(0)
202 #define XUSB_AO_UHSIC_SLEEPWALK(x)		(0x120 + (x) * 4)
204 #define   RPD_STROBE_A				BIT(0)
224 #define XUSB_AO_UTMIP_PAD_CFG(x)		(0x130 + (x) * 4)
235 #define XUSB_AO_UHSIC_PAD_CFG(x)		(0x150 + (x) * 4)
236 #define   STROBE_VAL_PD				BIT(0)
280 	writel(value, priv->ao_regs + offset);  in ao_writel()
285 	return readl(priv->ao_regs + offset);  in ao_readl()
304 		return ERR_PTR(-ENOMEM);  in tegra186_usb2_lane_probe()
306 	INIT_LIST_HEAD(&usb2->base.list);  in tegra186_usb2_lane_probe()
307 	usb2->base.soc = &pad->soc->lanes[index];  in tegra186_usb2_lane_probe()
308 	usb2->base.index = index;  in tegra186_usb2_lane_probe()
309 	usb2->base.pad = pad;  in tegra186_usb2_lane_probe()
310 	usb2->base.np = np;  in tegra186_usb2_lane_probe()
312 	err = tegra_xusb_lane_parse_dt(&usb2->base, np);  in tegra186_usb2_lane_probe()
313 	if (err < 0) {  in tegra186_usb2_lane_probe()
318 	return &usb2->base;  in tegra186_usb2_lane_probe()
331 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_enable_phy_sleepwalk()
333 	unsigned int index = lane->index;  in tegra186_utmi_enable_phy_sleepwalk()
336 	mutex_lock(&padctl->lock);  in tegra186_utmi_enable_phy_sleepwalk()
350 	value &= ~UTMIP_LINE_DEB_CNT(~0);  in tegra186_utmi_enable_phy_sleepwalk()
367 	value &= ~WAKE_VAL(~0);  in tegra186_utmi_enable_phy_sleepwalk()
378 	value &= ~SPEED(~0);  in tegra186_utmi_enable_phy_sleepwalk()
407 	 * as well as capture the configuration of the USB2.0 pad  in tegra186_utmi_enable_phy_sleepwalk()
413 	/* setup the pull-ups and pull-downs of the signals during the four  in tegra186_utmi_enable_phy_sleepwalk()
424 		/* J state: D+/D- = high/low, K state: D+/D- = low/high */  in tegra186_utmi_enable_phy_sleepwalk()
428 		if (padctl->soc->supports_lp_cfg_en)  in tegra186_utmi_enable_phy_sleepwalk()
433 		/* J state: D+/D- = low/high, K state: D+/D- = high/low */  in tegra186_utmi_enable_phy_sleepwalk()
437 		if (padctl->soc->supports_lp_cfg_en)  in tegra186_utmi_enable_phy_sleepwalk()
455 	/* switch the electric control of the USB2.0 pad to XUSB_AO */  in tegra186_utmi_enable_phy_sleepwalk()
463 	value &= ~WAKE_VAL(~0);  in tegra186_utmi_enable_phy_sleepwalk()
472 	mutex_unlock(&padctl->lock);  in tegra186_utmi_enable_phy_sleepwalk()
474 	return 0;  in tegra186_utmi_enable_phy_sleepwalk()
479 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_disable_phy_sleepwalk()
481 	unsigned int index = lane->index;  in tegra186_utmi_disable_phy_sleepwalk()
484 	mutex_lock(&padctl->lock);  in tegra186_utmi_disable_phy_sleepwalk()
491 	/* switch the electric control of the USB2.0 pad to XUSB vcore logic */  in tegra186_utmi_disable_phy_sleepwalk()
499 	value &= ~WAKE_VAL(~0);  in tegra186_utmi_disable_phy_sleepwalk()
503 	if (padctl->soc->supports_lp_cfg_en) {  in tegra186_utmi_disable_phy_sleepwalk()
520 	mutex_unlock(&padctl->lock);  in tegra186_utmi_disable_phy_sleepwalk()
522 	return 0;  in tegra186_utmi_disable_phy_sleepwalk()
527 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_enable_phy_wake()
528 	unsigned int index = lane->index;  in tegra186_utmi_enable_phy_wake()
531 	mutex_lock(&padctl->lock);  in tegra186_utmi_enable_phy_wake()
545 	mutex_unlock(&padctl->lock);  in tegra186_utmi_enable_phy_wake()
547 	return 0;  in tegra186_utmi_enable_phy_wake()
552 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_disable_phy_wake()
553 	unsigned int index = lane->index;  in tegra186_utmi_disable_phy_wake()
556 	mutex_lock(&padctl->lock);  in tegra186_utmi_disable_phy_wake()
570 	mutex_unlock(&padctl->lock);  in tegra186_utmi_disable_phy_wake()
572 	return 0;  in tegra186_utmi_disable_phy_wake()
577 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_phy_remote_wake_detected()
578 	unsigned int index = lane->index;  in tegra186_utmi_phy_remote_wake_detected()
602 	struct device *dev = padctl->dev;  in tegra186_utmi_bias_pad_power_on()
606 	mutex_lock(&padctl->lock);  in tegra186_utmi_bias_pad_power_on()
608 	if (priv->bias_pad_enable++ > 0) {  in tegra186_utmi_bias_pad_power_on()
609 		mutex_unlock(&padctl->lock);  in tegra186_utmi_bias_pad_power_on()
613 	err = clk_prepare_enable(priv->usb2_trk_clk);  in tegra186_utmi_bias_pad_power_on()
614 	if (err < 0)  in tegra186_utmi_bias_pad_power_on()
618 	value &= ~USB2_TRK_START_TIMER(~0);  in tegra186_utmi_bias_pad_power_on()
619 	value |= USB2_TRK_START_TIMER(0x1e);  in tegra186_utmi_bias_pad_power_on()
620 	value &= ~USB2_TRK_DONE_RESET_TIMER(~0);  in tegra186_utmi_bias_pad_power_on()
621 	value |= USB2_TRK_DONE_RESET_TIMER(0xa);  in tegra186_utmi_bias_pad_power_on()
626 	value &= ~HS_SQUELCH_LEVEL(~0);  in tegra186_utmi_bias_pad_power_on()
627 	value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch);  in tegra186_utmi_bias_pad_power_on()
636 	if (padctl->soc->poll_trk_completed) {  in tegra186_utmi_bias_pad_power_on()
653 	if (padctl->soc->trk_hw_mode) {  in tegra186_utmi_bias_pad_power_on()
659 		clk_disable_unprepare(priv->usb2_trk_clk);  in tegra186_utmi_bias_pad_power_on()
662 	mutex_unlock(&padctl->lock);  in tegra186_utmi_bias_pad_power_on()
670 	mutex_lock(&padctl->lock);  in tegra186_utmi_bias_pad_power_off()
672 	if (WARN_ON(priv->bias_pad_enable == 0)) {  in tegra186_utmi_bias_pad_power_off()
673 		mutex_unlock(&padctl->lock);  in tegra186_utmi_bias_pad_power_off()
677 	if (--priv->bias_pad_enable > 0) {  in tegra186_utmi_bias_pad_power_off()
678 		mutex_unlock(&padctl->lock);  in tegra186_utmi_bias_pad_power_off()
686 	if (padctl->soc->trk_hw_mode) {  in tegra186_utmi_bias_pad_power_off()
690 		clk_disable_unprepare(priv->usb2_trk_clk);  in tegra186_utmi_bias_pad_power_off()
693 	mutex_unlock(&padctl->lock);  in tegra186_utmi_bias_pad_power_off()
699 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_pad_power_on()
701 	struct device *dev = padctl->dev;  in tegra186_utmi_pad_power_on()
702 	unsigned int index = lane->index;  in tegra186_utmi_pad_power_on()
732 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_pad_power_down()
733 	unsigned int index = lane->index;  in tegra186_utmi_pad_power_down()
739 	dev_dbg(padctl->dev, "power down UTMI pad %u\n", index);  in tegra186_utmi_pad_power_down()
759 	dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");  in tegra186_xusb_padctl_vbus_override()
765 		value &= ~ID_OVERRIDE(~0);  in tegra186_xusb_padctl_vbus_override()
773 	return 0;  in tegra186_xusb_padctl_vbus_override()
781 	dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");  in tegra186_xusb_padctl_id_override()
794 		value &= ~ID_OVERRIDE(~0);  in tegra186_xusb_padctl_id_override()
797 		value &= ~ID_OVERRIDE(~0);  in tegra186_xusb_padctl_id_override()
803 	return 0;  in tegra186_xusb_padctl_id_override()
810 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_phy_set_mode()
812 								lane->index);  in tegra186_utmi_phy_set_mode()
813 	int err = 0;  in tegra186_utmi_phy_set_mode()
815 	mutex_lock(&padctl->lock);  in tegra186_utmi_phy_set_mode()
817 	dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);  in tegra186_utmi_phy_set_mode()
823 			err = regulator_enable(port->supply);  in tegra186_utmi_phy_set_mode()
832 			if (regulator_is_enabled(port->supply))  in tegra186_utmi_phy_set_mode()
833 				regulator_disable(port->supply);  in tegra186_utmi_phy_set_mode()
840 	mutex_unlock(&padctl->lock);  in tegra186_utmi_phy_set_mode()
849 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_phy_power_on()
852 	unsigned int index = lane->index;  in tegra186_utmi_phy_power_on()
853 	struct device *dev = padctl->dev;  in tegra186_utmi_phy_power_on()
859 		return -ENODEV;  in tegra186_utmi_phy_power_on()
870 	if (port->mode == USB_DR_MODE_UNKNOWN)  in tegra186_utmi_phy_power_on()
872 	else if (port->mode == USB_DR_MODE_PERIPHERAL)  in tegra186_utmi_phy_power_on()
874 	else if (port->mode == USB_DR_MODE_HOST)  in tegra186_utmi_phy_power_on()
876 	else if (port->mode == USB_DR_MODE_OTG)  in tegra186_utmi_phy_power_on()
884 	value &= ~HS_CURR_LEVEL(~0);  in tegra186_utmi_phy_power_on()
886 	if (usb2->hs_curr_level_offset) {  in tegra186_utmi_phy_power_on()
889 		hs_current_level = (int)priv->calib.hs_curr_level[index] +  in tegra186_utmi_phy_power_on()
890 						usb2->hs_curr_level_offset;  in tegra186_utmi_phy_power_on()
892 		if (hs_current_level < 0)  in tegra186_utmi_phy_power_on()
893 			hs_current_level = 0;  in tegra186_utmi_phy_power_on()
894 		if (hs_current_level > 0x3f)  in tegra186_utmi_phy_power_on()
895 			hs_current_level = 0x3f;  in tegra186_utmi_phy_power_on()
899 		value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]);  in tegra186_utmi_phy_power_on()
905 	value &= ~TERM_RANGE_ADJ(~0);  in tegra186_utmi_phy_power_on()
906 	value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj);  in tegra186_utmi_phy_power_on()
907 	value &= ~RPD_CTRL(~0);  in tegra186_utmi_phy_power_on()
908 	value |= RPD_CTRL(priv->calib.rpd_ctrl);  in tegra186_utmi_phy_power_on()
913 	return 0;  in tegra186_utmi_phy_power_on()
920 	return 0;  in tegra186_utmi_phy_power_off()
926 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_phy_init()
928 	unsigned int index = lane->index;  in tegra186_utmi_phy_init()
929 	struct device *dev = padctl->dev;  in tegra186_utmi_phy_init()
936 		return -ENODEV;  in tegra186_utmi_phy_init()
939 	if (port->mode == USB_DR_MODE_OTG ||  in tegra186_utmi_phy_init()
940 	    port->mode == USB_DR_MODE_PERIPHERAL) {  in tegra186_utmi_phy_init()
944 		reg &= ~ID_OVERRIDE(~0);  in tegra186_utmi_phy_init()
949 	if (port->supply && port->mode == USB_DR_MODE_HOST) {  in tegra186_utmi_phy_init()
950 		err = regulator_enable(port->supply);  in tegra186_utmi_phy_init()
958 	return 0;  in tegra186_utmi_phy_init()
964 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_phy_exit()
966 	unsigned int index = lane->index;  in tegra186_utmi_phy_exit()
967 	struct device *dev = padctl->dev;  in tegra186_utmi_phy_exit()
973 		return -ENODEV;  in tegra186_utmi_phy_exit()
976 	if (port->supply && port->mode == USB_DR_MODE_HOST) {  in tegra186_utmi_phy_exit()
977 		err = regulator_disable(port->supply);  in tegra186_utmi_phy_exit()
985 	return 0;  in tegra186_utmi_phy_exit()
1009 		return ERR_PTR(-ENOMEM);  in tegra186_usb2_pad_probe()
1011 	pad = &usb2->base;  in tegra186_usb2_pad_probe()
1012 	pad->ops = &tegra186_usb2_lane_ops;  in tegra186_usb2_pad_probe()
1013 	pad->soc = soc;  in tegra186_usb2_pad_probe()
1016 	if (err < 0) {  in tegra186_usb2_pad_probe()
1021 	priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk");  in tegra186_usb2_pad_probe()
1022 	if (IS_ERR(priv->usb2_trk_clk)) {  in tegra186_usb2_pad_probe()
1023 		err = PTR_ERR(priv->usb2_trk_clk);  in tegra186_usb2_pad_probe()
1024 		dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err);  in tegra186_usb2_pad_probe()
1029 	if (err < 0)  in tegra186_usb2_pad_probe()
1032 	dev_set_drvdata(&pad->dev, pad);  in tegra186_usb2_pad_probe()
1037 	device_unregister(&pad->dev);  in tegra186_usb2_pad_probe()
1060 	return 0;  in tegra186_usb2_port_enable()
1070 	return tegra_xusb_find_lane(port->padctl, "usb2", port->index);  in tegra186_usb2_port_map()
1086 	struct tegra_xusb_usb3_lane *usb3;  in tegra186_usb3_lane_probe()  local
1089 	usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);  in tegra186_usb3_lane_probe()
1090 	if (!usb3)  in tegra186_usb3_lane_probe()
1091 		return ERR_PTR(-ENOMEM);  in tegra186_usb3_lane_probe()
1093 	INIT_LIST_HEAD(&usb3->base.list);  in tegra186_usb3_lane_probe()
1094 	usb3->base.soc = &pad->soc->lanes[index];  in tegra186_usb3_lane_probe()
1095 	usb3->base.index = index;  in tegra186_usb3_lane_probe()
1096 	usb3->base.pad = pad;  in tegra186_usb3_lane_probe()
1097 	usb3->base.np = np;  in tegra186_usb3_lane_probe()
1099 	err = tegra_xusb_lane_parse_dt(&usb3->base, np);  in tegra186_usb3_lane_probe()
1100 	if (err < 0) {  in tegra186_usb3_lane_probe()
1101 		kfree(usb3);  in tegra186_usb3_lane_probe()
1105 	return &usb3->base;  in tegra186_usb3_lane_probe()
1110 	struct tegra_xusb_usb3_lane *usb3 = to_usb3_lane(lane);  in tegra186_usb3_lane_remove()  local
1112 	kfree(usb3);  in tegra186_usb3_lane_remove()
1118 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_enable_phy_sleepwalk()
1119 	unsigned int index = lane->index;  in tegra186_usb3_enable_phy_sleepwalk()
1122 	mutex_lock(&padctl->lock);  in tegra186_usb3_enable_phy_sleepwalk()
1136 	mutex_unlock(&padctl->lock);  in tegra186_usb3_enable_phy_sleepwalk()
1138 	return 0;  in tegra186_usb3_enable_phy_sleepwalk()
1143 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_disable_phy_sleepwalk()
1144 	unsigned int index = lane->index;  in tegra186_usb3_disable_phy_sleepwalk()
1147 	mutex_lock(&padctl->lock);  in tegra186_usb3_disable_phy_sleepwalk()
1159 	mutex_unlock(&padctl->lock);  in tegra186_usb3_disable_phy_sleepwalk()
1161 	return 0;  in tegra186_usb3_disable_phy_sleepwalk()
1166 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_enable_phy_wake()
1167 	unsigned int index = lane->index;  in tegra186_usb3_enable_phy_wake()
1170 	mutex_lock(&padctl->lock);  in tegra186_usb3_enable_phy_wake()
1184 	mutex_unlock(&padctl->lock);  in tegra186_usb3_enable_phy_wake()
1186 	return 0;  in tegra186_usb3_enable_phy_wake()
1191 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_disable_phy_wake()
1192 	unsigned int index = lane->index;  in tegra186_usb3_disable_phy_wake()
1195 	mutex_lock(&padctl->lock);  in tegra186_usb3_disable_phy_wake()
1209 	mutex_unlock(&padctl->lock);  in tegra186_usb3_disable_phy_wake()
1211 	return 0;  in tegra186_usb3_disable_phy_wake()
1216 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_phy_remote_wake_detected()
1217 	unsigned int index = lane->index;  in tegra186_usb3_phy_remote_wake_detected()
1239 	return 0;  in tegra186_usb3_port_enable()
1249 	return tegra_xusb_find_lane(port->padctl, "usb3", port->index);  in tegra186_usb3_port_map()
1262 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_phy_power_on()
1265 	unsigned int index = lane->index;  in tegra186_usb3_phy_power_on()
1266 	struct device *dev = padctl->dev;  in tegra186_usb3_phy_power_on()
1271 		dev_err(dev, "no port found for USB3 lane %u\n", index);  in tegra186_usb3_phy_power_on()
1272 		return -ENODEV;  in tegra186_usb3_phy_power_on()
1275 	usb2 = tegra_xusb_find_usb2_port(padctl, port->port);  in tegra186_usb3_phy_power_on()
1277 		dev_err(dev, "no companion port found for USB3 lane %u\n",  in tegra186_usb3_phy_power_on()
1279 		return -ENODEV;  in tegra186_usb3_phy_power_on()
1282 	mutex_lock(&padctl->lock);  in tegra186_usb3_phy_power_on()
1287 	if (usb2->mode == USB_DR_MODE_UNKNOWN)  in tegra186_usb3_phy_power_on()
1289 	else if (usb2->mode == USB_DR_MODE_PERIPHERAL)  in tegra186_usb3_phy_power_on()
1291 	else if (usb2->mode == USB_DR_MODE_HOST)  in tegra186_usb3_phy_power_on()
1293 	else if (usb2->mode == USB_DR_MODE_OTG)  in tegra186_usb3_phy_power_on()
1298 	if (padctl->soc->supports_gen2 && port->disable_gen2) {  in tegra186_usb3_phy_power_on()
1323 	mutex_unlock(&padctl->lock);  in tegra186_usb3_phy_power_on()
1325 	return 0;  in tegra186_usb3_phy_power_on()
1331 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_phy_power_off()
1333 	unsigned int index = lane->index;  in tegra186_usb3_phy_power_off()
1334 	struct device *dev = padctl->dev;  in tegra186_usb3_phy_power_off()
1339 		dev_err(dev, "no port found for USB3 lane %u\n", index);  in tegra186_usb3_phy_power_off()
1340 		return -ENODEV;  in tegra186_usb3_phy_power_off()
1343 	mutex_lock(&padctl->lock);  in tegra186_usb3_phy_power_off()
1361 	mutex_unlock(&padctl->lock);  in tegra186_usb3_phy_power_off()
1363 	return 0;  in tegra186_usb3_phy_power_off()
1368 	return 0;  in tegra186_usb3_phy_init()
1373 	return 0;  in tegra186_usb3_phy_exit()
1389 	struct tegra_xusb_usb3_pad *usb3;  in tegra186_usb3_pad_probe()  local
1393 	usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);  in tegra186_usb3_pad_probe()
1394 	if (!usb3)  in tegra186_usb3_pad_probe()
1395 		return ERR_PTR(-ENOMEM);  in tegra186_usb3_pad_probe()
1397 	pad = &usb3->base;  in tegra186_usb3_pad_probe()
1398 	pad->ops = &tegra186_usb3_lane_ops;  in tegra186_usb3_pad_probe()
1399 	pad->soc = soc;  in tegra186_usb3_pad_probe()
1402 	if (err < 0) {  in tegra186_usb3_pad_probe()
1403 		kfree(usb3);  in tegra186_usb3_pad_probe()
1408 	if (err < 0)  in tegra186_usb3_pad_probe()
1411 	dev_set_drvdata(&pad->dev, pad);  in tegra186_usb3_pad_probe()
1416 	device_unregister(&pad->dev);  in tegra186_usb3_pad_probe()
1440 	struct device *dev = padctl->base.dev;  in tegra186_xusb_read_fuse_calibration()
1445 	count = padctl->base.soc->ports.usb2.count;  in tegra186_xusb_read_fuse_calibration()
1449 		return -ENOMEM;  in tegra186_xusb_read_fuse_calibration()
1458 	for (i = 0; i < count; i++)  in tegra186_xusb_read_fuse_calibration()
1462 	padctl->calib.hs_curr_level = level;  in tegra186_xusb_read_fuse_calibration()
1464 	padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &  in tegra186_xusb_read_fuse_calibration()
1466 	padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &  in tegra186_xusb_read_fuse_calibration()
1477 	padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;  in tegra186_xusb_read_fuse_calibration()
1479 	return 0;  in tegra186_xusb_read_fuse_calibration()
1493 		return ERR_PTR(-ENOMEM);  in tegra186_xusb_padctl_probe()
1495 	priv->base.dev = dev;  in tegra186_xusb_padctl_probe()
1496 	priv->base.soc = soc;  in tegra186_xusb_padctl_probe()
1499 	priv->ao_regs = devm_ioremap_resource(dev, res);  in tegra186_xusb_padctl_probe()
1500 	if (IS_ERR(priv->ao_regs))  in tegra186_xusb_padctl_probe()
1501 		return ERR_CAST(priv->ao_regs);  in tegra186_xusb_padctl_probe()
1504 	if (err < 0)  in tegra186_xusb_padctl_probe()
1507 	return &priv->base;  in tegra186_xusb_padctl_probe()
1514 	priv->context.vbus_id = padctl_readl(padctl, USB2_VBUS_ID);  in tegra186_xusb_padctl_save()
1515 	priv->context.usb2_pad_mux = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);  in tegra186_xusb_padctl_save()
1516 	priv->context.usb2_port_cap = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);  in tegra186_xusb_padctl_save()
1517 	priv->context.ss_port_cap = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);  in tegra186_xusb_padctl_save()
1524 	padctl_writel(padctl, priv->context.usb2_pad_mux, XUSB_PADCTL_USB2_PAD_MUX);  in tegra186_xusb_padctl_restore()
1525 	padctl_writel(padctl, priv->context.usb2_port_cap, XUSB_PADCTL_USB2_PORT_CAP);  in tegra186_xusb_padctl_restore()
1526 	padctl_writel(padctl, priv->context.ss_port_cap, XUSB_PADCTL_SS_PORT_CAP);  in tegra186_xusb_padctl_restore()
1527 	padctl_writel(padctl, priv->context.vbus_id, USB2_VBUS_ID);  in tegra186_xusb_padctl_restore()
1534 	return 0;  in tegra186_xusb_padctl_suspend_noirq()
1541 	return 0;  in tegra186_xusb_padctl_resume_noirq()
1560 	"avdd-pll-erefeut",
1561 	"avdd-usb",
1562 	"vclamp-usb",
1563 	"vddio-hsic",
1567 	TEGRA186_LANE("usb2-0", 0,  0, 0, usb2),
1568 	TEGRA186_LANE("usb2-1", 0,  0, 0, usb2),
1569 	TEGRA186_LANE("usb2-2", 0,  0, 0, usb2),
1580 	TEGRA186_LANE("usb3-0", 0,  0, 0, usb3),
1581 	TEGRA186_LANE("usb3-1", 0,  0, 0, usb3),
1582 	TEGRA186_LANE("usb3-2", 0,  0, 0, usb3),
1586 	.name = "usb3",
1595 #if 0 /* TODO implement */
1608 #if 0 /* TODO implement */
1614 		.usb3 = {
1629 	"avdd-usb",
1630 	"vclamp-usb",
1634 	TEGRA186_LANE("usb2-0", 0,  0, 0, usb2),
1635 	TEGRA186_LANE("usb2-1", 0,  0, 0, usb2),
1636 	TEGRA186_LANE("usb2-2", 0,  0, 0, usb2),
1637 	TEGRA186_LANE("usb2-3", 0,  0, 0, usb2),
1648 	TEGRA186_LANE("usb3-0", 0,  0, 0, usb3),
1649 	TEGRA186_LANE("usb3-1", 0,  0, 0, usb3),
1650 	TEGRA186_LANE("usb3-2", 0,  0, 0, usb3),
1651 	TEGRA186_LANE("usb3-3", 0,  0, 0, usb3),
1655 	.name = "usb3",
1674 		.usb3 = {
1695 		.usb3 = {