Lines Matching full:val

76 	u32 val;  in uniphier_ahciphy_pro4_init()  local
79 val = readl(priv->base + CKCTRL0); in uniphier_ahciphy_pro4_init()
80 val &= ~CKCTRL0_NCY_MASK; in uniphier_ahciphy_pro4_init()
81 val |= FIELD_PREP(CKCTRL0_NCY_MASK, 0x6); in uniphier_ahciphy_pro4_init()
82 val &= ~CKCTRL0_NCY5_MASK; in uniphier_ahciphy_pro4_init()
83 val |= FIELD_PREP(CKCTRL0_NCY5_MASK, 0x2); in uniphier_ahciphy_pro4_init()
84 val &= ~CKCTRL0_PRESCALE_MASK; in uniphier_ahciphy_pro4_init()
85 val |= FIELD_PREP(CKCTRL0_PRESCALE_MASK, 0x1); in uniphier_ahciphy_pro4_init()
86 writel(val, priv->base + CKCTRL0); in uniphier_ahciphy_pro4_init()
89 val = readl(priv->base + CKCTRL1); in uniphier_ahciphy_pro4_init()
90 val &= ~CKCTRL1_LOS_LVL_MASK; in uniphier_ahciphy_pro4_init()
91 val |= FIELD_PREP(CKCTRL1_LOS_LVL_MASK, 0x10); in uniphier_ahciphy_pro4_init()
92 val &= ~CKCTRL1_TX_LVL_MASK; in uniphier_ahciphy_pro4_init()
93 val |= FIELD_PREP(CKCTRL1_TX_LVL_MASK, 0x06); in uniphier_ahciphy_pro4_init()
94 writel(val, priv->base + CKCTRL1); in uniphier_ahciphy_pro4_init()
96 val = readl(priv->base + RXTXCTRL); in uniphier_ahciphy_pro4_init()
97 val &= ~RXTXCTRL_RX_EQ_VALL_MASK; in uniphier_ahciphy_pro4_init()
98 val |= FIELD_PREP(RXTXCTRL_RX_EQ_VALL_MASK, 0x6); in uniphier_ahciphy_pro4_init()
99 val &= ~RXTXCTRL_RX_DPLL_MODE_MASK; in uniphier_ahciphy_pro4_init()
100 val |= FIELD_PREP(RXTXCTRL_RX_DPLL_MODE_MASK, 0x3); in uniphier_ahciphy_pro4_init()
101 val &= ~RXTXCTRL_TX_ATTEN_MASK; in uniphier_ahciphy_pro4_init()
102 val |= FIELD_PREP(RXTXCTRL_TX_ATTEN_MASK, 0x3); in uniphier_ahciphy_pro4_init()
103 val &= ~RXTXCTRL_TX_BOOST_MASK; in uniphier_ahciphy_pro4_init()
104 val |= FIELD_PREP(RXTXCTRL_TX_BOOST_MASK, 0x5); in uniphier_ahciphy_pro4_init()
105 val &= ~RXTXCTRL_TX_EDGERATE_MASK; in uniphier_ahciphy_pro4_init()
106 val |= FIELD_PREP(RXTXCTRL_TX_EDGERATE_MASK, 0x0); in uniphier_ahciphy_pro4_init()
107 writel(val, priv->base + RXTXCTRL); in uniphier_ahciphy_pro4_init()
114 u32 val; in uniphier_ahciphy_pro4_power_on() local
118 val = readl(priv->base + CKCTRL0); in uniphier_ahciphy_pro4_power_on()
119 val &= ~CKCTRL0_CK_OFF; in uniphier_ahciphy_pro4_power_on()
120 writel(val, priv->base + CKCTRL0); in uniphier_ahciphy_pro4_power_on()
123 val = readl(priv->base + RXTXCTRL); in uniphier_ahciphy_pro4_power_on()
124 val |= RXTXCTRL_TX_CKO_EN; in uniphier_ahciphy_pro4_power_on()
125 writel(val, priv->base + RXTXCTRL); in uniphier_ahciphy_pro4_power_on()
128 ret = readl_poll_timeout(priv->base + RSTPWR, val, in uniphier_ahciphy_pro4_power_on()
129 !(val & RSTPWR_RX_EN_VAL), 200, 2000); in uniphier_ahciphy_pro4_power_on()
163 val = readl(priv->base + RXTXCTRL); in uniphier_ahciphy_pro4_power_on()
164 val &= ~RXTXCTRL_TX_CKO_EN; in uniphier_ahciphy_pro4_power_on()
165 writel(val, priv->base + RXTXCTRL); in uniphier_ahciphy_pro4_power_on()
168 val = readl(priv->base + CKCTRL0); in uniphier_ahciphy_pro4_power_on()
169 val |= CKCTRL0_CK_OFF; in uniphier_ahciphy_pro4_power_on()
170 writel(val, priv->base + CKCTRL0); in uniphier_ahciphy_pro4_power_on()
177 u32 val; in uniphier_ahciphy_pro4_power_off() local
184 val = readl(priv->base + RXTXCTRL); in uniphier_ahciphy_pro4_power_off()
185 val &= ~RXTXCTRL_TX_CKO_EN; in uniphier_ahciphy_pro4_power_off()
186 writel(val, priv->base + RXTXCTRL); in uniphier_ahciphy_pro4_power_off()
189 val = readl(priv->base + CKCTRL0); in uniphier_ahciphy_pro4_power_off()
190 val |= CKCTRL0_CK_OFF; in uniphier_ahciphy_pro4_power_off()
191 writel(val, priv->base + CKCTRL0); in uniphier_ahciphy_pro4_power_off()
199 u32 val; in uniphier_ahciphy_pxs2_enable() local
201 val = readl(priv->base + CKCTRL); in uniphier_ahciphy_pxs2_enable()
204 val |= CKCTRL_REF_SSP_EN; in uniphier_ahciphy_pxs2_enable()
205 writel(val, priv->base + CKCTRL); in uniphier_ahciphy_pxs2_enable()
206 val &= ~CKCTRL_P0_RESET; in uniphier_ahciphy_pxs2_enable()
207 writel(val, priv->base + CKCTRL); in uniphier_ahciphy_pxs2_enable()
209 val |= CKCTRL_P0_RESET; in uniphier_ahciphy_pxs2_enable()
210 writel(val, priv->base + CKCTRL); in uniphier_ahciphy_pxs2_enable()
211 val &= ~CKCTRL_REF_SSP_EN; in uniphier_ahciphy_pxs2_enable()
212 writel(val, priv->base + CKCTRL); in uniphier_ahciphy_pxs2_enable()
219 u32 val; in uniphier_ahciphy_pxs2_power_on() local
225 ret = readl_poll_timeout(priv->base + CKCTRL, val, in uniphier_ahciphy_pxs2_power_on()
226 (val & CKCTRL_P0_READY), 200, 400); in uniphier_ahciphy_pxs2_power_on()
228 ret = readl_poll_timeout(priv->base + CKCTRL, val, in uniphier_ahciphy_pxs2_power_on()
229 !(val & CKCTRL_P0_READY), 200, 400); in uniphier_ahciphy_pxs2_power_on()
248 u32 val; in uniphier_ahciphy_pxs3_init() local
251 val = readl(priv->base + TXCTRL0); in uniphier_ahciphy_pxs3_init()
252 val &= ~TXCTRL0_AMP_G3_MASK; in uniphier_ahciphy_pxs3_init()
253 val |= FIELD_PREP(TXCTRL0_AMP_G3_MASK, 0x73); in uniphier_ahciphy_pxs3_init()
254 val &= ~TXCTRL0_AMP_G2_MASK; in uniphier_ahciphy_pxs3_init()
255 val |= FIELD_PREP(TXCTRL0_AMP_G2_MASK, 0x46); in uniphier_ahciphy_pxs3_init()
256 val &= ~TXCTRL0_AMP_G1_MASK; in uniphier_ahciphy_pxs3_init()
257 val |= FIELD_PREP(TXCTRL0_AMP_G1_MASK, 0x42); in uniphier_ahciphy_pxs3_init()
258 writel(val, priv->base + TXCTRL0); in uniphier_ahciphy_pxs3_init()
260 val = readl(priv->base + TXCTRL1); in uniphier_ahciphy_pxs3_init()
261 val &= ~TXCTRL1_DEEMPH_G3_MASK; in uniphier_ahciphy_pxs3_init()
262 val |= FIELD_PREP(TXCTRL1_DEEMPH_G3_MASK, 0x23); in uniphier_ahciphy_pxs3_init()
263 val &= ~TXCTRL1_DEEMPH_G2_MASK; in uniphier_ahciphy_pxs3_init()
264 val |= FIELD_PREP(TXCTRL1_DEEMPH_G2_MASK, 0x05); in uniphier_ahciphy_pxs3_init()
265 val &= ~TXCTRL1_DEEMPH_G1_MASK; in uniphier_ahciphy_pxs3_init()
266 val |= FIELD_PREP(TXCTRL1_DEEMPH_G1_MASK, 0x05); in uniphier_ahciphy_pxs3_init()
268 val = readl(priv->base + RXCTRL); in uniphier_ahciphy_pxs3_init()
269 val &= ~RXCTRL_LOS_LVL_MASK; in uniphier_ahciphy_pxs3_init()
270 val |= FIELD_PREP(RXCTRL_LOS_LVL_MASK, 0x9); in uniphier_ahciphy_pxs3_init()
271 val &= ~RXCTRL_LOS_BIAS_MASK; in uniphier_ahciphy_pxs3_init()
272 val |= FIELD_PREP(RXCTRL_LOS_BIAS_MASK, 0x2); in uniphier_ahciphy_pxs3_init()
273 val &= ~RXCTRL_RX_EQ_MASK; in uniphier_ahciphy_pxs3_init()
274 val |= FIELD_PREP(RXCTRL_RX_EQ_MASK, 0x1); in uniphier_ahciphy_pxs3_init()