Lines Matching +full:0 +full:x08f0
28 #define EXYNOS5_FSEL_9MHZ6 0x0
29 #define EXYNOS5_FSEL_10MHZ 0x1
30 #define EXYNOS5_FSEL_12MHZ 0x2
31 #define EXYNOS5_FSEL_19MHZ2 0x3
32 #define EXYNOS5_FSEL_20MHZ 0x4
33 #define EXYNOS5_FSEL_24MHZ 0x5
34 #define EXYNOS5_FSEL_26MHZ 0x6
35 #define EXYNOS5_FSEL_50MHZ 0x7
38 #define EXYNOS5_DRD_LINKSYSTEM 0x04
40 #define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
43 #define EXYNOS5_DRD_PHYUTMI 0x08
46 #define PHYUTMI_FORCESLEEP BIT(0)
48 #define EXYNOS5_DRD_PHYPIPE 0x0c
50 #define EXYNOS5_DRD_PHYCLKRST 0x10
52 #define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
54 #define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
59 #define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
60 #define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
61 #define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x32 << 11)
62 #define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
63 #define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
64 #define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
65 #define PHYCLKRST_FSEL_PIPE_MASK (0x7 << 8)
66 #define PHYCLKRST_FSEL_UTMI_MASK (0x7 << 5)
68 #define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
69 #define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
70 #define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
71 #define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
73 #define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
74 #define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
75 #define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
77 #define PHYCLKRST_COMMONONN BIT(0)
79 #define EXYNOS5_DRD_PHYREG0 0x14
86 #define PHYREG0_CR_CAP_ADDR BIT(0)
88 #define EXYNOS5_DRD_PHYREG1 0x18
90 #define PHYREG1_CR_ACK BIT(0)
92 #define EXYNOS5_DRD_PHYPARAM0 0x1c
94 #define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
95 #define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
97 #define EXYNOS5_DRD_PHYPARAM1 0x20
98 #define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
99 #define PHYPARAM1_PCS_TXDEEMPH (0x1c)
101 #define EXYNOS5_DRD_PHYTERM 0x24
103 #define EXYNOS5_DRD_PHYTEST 0x28
107 #define EXYNOS5_DRD_PHYADP 0x2c
109 #define EXYNOS5_DRD_PHYUTMICLKSEL 0x30
112 #define EXYNOS5_DRD_PHYRESUME 0x34
114 #define EXYNOS5_DRD_LINKPORT 0x44
117 #define EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN (0x15)
118 #define LOSLEVEL_OVRD_IN_LOS_BIAS_5420 (0x5 << 13)
119 #define LOSLEVEL_OVRD_IN_LOS_BIAS_DEFAULT (0x0 << 13)
120 #define LOSLEVEL_OVRD_IN_EN (0x1 << 10)
121 #define LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT (0x9 << 0)
123 #define EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN (0x12)
124 #define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420 (0x5 << 13)
125 #define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_DEFAULT (0x4 << 13)
127 #define EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG (0x1010)
128 #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M (0x4 << 4)
129 #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M (0x8 << 4)
130 #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_25M_26M (0x8 << 4)
131 #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M (0x20 << 4)
132 #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_62M5 (0x20 << 4)
133 #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_96M_100M (0x40 << 4)
136 #define EXYNOS850_DRD_LINKCTRL 0x04
143 #define EXYNOS850_DRD_LINKPORT 0x08
147 #define EXYNOS850_DRD_CLKRST 0x20
159 #define CLKRST_LINK_SW_RST BIT(0)
161 #define EXYNOS850_DRD_SSPPLLCTL 0x30
162 #define SSPPLLCTL_FSEL GENMASK(2, 0)
164 #define EXYNOS850_DRD_UTMI 0x50
170 #define UTMI_FORCE_SLEEP BIT(0)
172 #define EXYNOS850_DRD_HSP 0x54
179 #define EXYNOS850_DRD_HSPPARACON 0x58
189 #define HSPPARACON_COMPDIS GENMASK(2, 0)
191 #define EXYNOS850_DRD_HSP_TEST 0x5c
195 #define EXYNOS850_DRD_SECPMACTL 0x48
203 #define SECPMACTL_PMA_APB_SW_RST BIT(0)
206 #define EXYNOS9_PMA_USBDP_CMN_REG0008 0x0020
210 #define EXYNOS9_PMA_USBDP_CMN_REG00B8 0x02e0
211 #define CMN_REG00B8_LANE_MUX_SEL_DP GENMASK(3, 0)
213 #define EXYNOS9_PMA_USBDP_CMN_REG01C0 0x0700
217 /* these have similar register layout, for lanes 0 and 2 */
218 #define EXYNOS9_PMA_USBDP_TRSV_REG03C3 0x0f0c
219 #define EXYNOS9_PMA_USBDP_TRSV_REG07C3 0x1f0c
223 #define TRSV_REG03C3_LN0_MON_RX_CDR_LOCK_DONE BIT(0)
226 #define EXYNOS9_PMA_USBDP_TRSV_REG0413 0x104c
230 #define EXYNOS9_PMA_USBDP_TRSV_REG0813 0x204c
235 #define EXYNOS9_PCS_NS_VEC_PS1_N1 0x010c
236 #define EXYNOS9_PCS_NS_VEC_PS2_N0 0x0110
237 #define EXYNOS9_PCS_NS_VEC_PS3_N0 0x0118
243 #define NS_VEC_EXP_COND GENMASK(3, 0)
245 #define EXYNOS9_PCS_OUT_VEC_2 0x014c
246 #define EXYNOS9_PCS_OUT_VEC_3 0x0150
266 #define PCS_OUT_VEC_B0_SEL_OUT BIT(0)
268 #define EXYNOS9_PCS_TIMEOUT_0 0x0170
270 #define EXYNOS9_PCS_TIMEOUT_3 0x017c
272 #define EXYNOS9_PCS_EBUF_PARAM 0x0304
275 #define EXYNOS9_PCS_BACK_END_MODE_VEC 0x030c
277 #define BACK_END_MODE_VEC_DISABLE_DATA_MASK BIT(0)
279 #define EXYNOS9_PCS_RX_CONTROL 0x03f0
282 #define EXYNOS9_PCS_RX_CONTROL_DEBUG 0x03f4
284 #define RX_CONTROL_DEBUG_NUM_COM_FOUND GENMASK(3, 0)
286 #define EXYNOS9_PCS_LOCAL_COEF 0x040c
289 #define LOCAL_COEF_FS GENMASK(5, 0)
291 #define EXYNOS9_PCS_HS_TX_COEF_MAP_0 0x0410
294 #define HS_TX_COEF_MAP_0_SSTX_PRE_SHOOT GENMASK(5, 0)
331 #define PTR_INVALID 0
455 return 0; in exynos5_rate_to_clk()
466 val = isolate ? 0 : EXYNOS4_PHY_ENABLE; in exynos5_usbdrd_phy_isol()
497 PHYCLKRST_SSC_REFCLKSEL(0x00)); in exynos5_usbdrd_pipe3_set_refclk()
501 PHYCLKRST_SSC_REFCLKSEL(0x88)); in exynos5_usbdrd_pipe3_set_refclk()
505 PHYCLKRST_SSC_REFCLKSEL(0x00)); in exynos5_usbdrd_pipe3_set_refclk()
509 PHYCLKRST_SSC_REFCLKSEL(0x88)); in exynos5_usbdrd_pipe3_set_refclk()
555 u32 reg = 0; in exynos5_usbdrd_apply_phy_tunes()
756 writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); in exynos5_usbdrd_phy_init()
757 writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYRESUME); in exynos5_usbdrd_phy_init()
760 * Setting the Frame length Adj value[6:1] to default 0x20 in exynos5_usbdrd_phy_init()
764 LINKSYSTEM_FLADJ(0x20); in exynos5_usbdrd_phy_init()
803 return 0; in exynos5_usbdrd_phy_init()
837 return 0; in exynos5_usbdrd_phy_exit()
864 return 0; in exynos5_usbdrd_phy_power_on()
890 return 0; in exynos5_usbdrd_phy_power_off()
904 dev_err(phy_drd->dev, "CRPORT handshake timeout1 (0x%08x)\n", val); in crport_handshake()
913 dev_err(phy_drd->dev, "CRPORT handshake timeout2 (0x%08x)\n", val); in crport_handshake()
917 return 0; in crport_handshake()
955 int ret = 0; in exynos5420_usbdrd_phy_calibrate()
958 * Change los_bias to (0x5) for 28nm PHY from a in exynos5420_usbdrd_phy_calibrate()
959 * default value (0x0); los_level is set as default in exynos5420_usbdrd_phy_calibrate()
960 * (0x9) as also reflected in los_level[30:26] bits in exynos5420_usbdrd_phy_calibrate()
976 * Set tx_vboost_lvl to (0x5) for 28nm PHY Tuning, in exynos5420_usbdrd_phy_calibrate()
977 * to raise Tx signal level from its default value of (0x4) in exynos5420_usbdrd_phy_calibrate()
1027 if (WARN_ON(args->args[0] >= EXYNOS5_DRDPHYS_NUM)) in exynos5_usbdrd_phy_xlate()
1030 return phy_drd->phys[args->args[0]].phy; in exynos5_usbdrd_phy_xlate()
1040 return 0; in exynos5_usbdrd_phy_calibrate()
1111 reg |= LINKCTRL_BUS_FILTER_BYPASS(0xf); in exynos850_usbdrd_utmi_init()
1138 reg |= FIELD_PREP(SSPPLLCTL_FSEL, 0); in exynos850_usbdrd_utmi_init()
1191 return 0; in exynos850_usbdrd_phy_init()
1227 return 0; in exynos850_usbdrd_phy_exit()
1308 return 0; in exynos5_usbdrd_gs101_phy_exit()
1331 for (int i = 0; i < phy_drd->drv_data->n_clks; ++i) in exynos5_usbdrd_phy_clk_handle()
1347 for (int i = 0; i < phy_drd->drv_data->n_core_clks; ++i) in exynos5_usbdrd_phy_clk_handle()
1357 for (int i = 0; i < phy_drd->drv_data->n_core_clks; ++i) { in exynos5_usbdrd_phy_clk_handle()
1374 return 0; in exynos5_usbdrd_phy_clk_handle()
1507 PHY_TUNING_ENTRY_PMA(0x0c8c, -1, 0xff),
1508 PHY_TUNING_ENTRY_PMA(0x1c8c, -1, 0xff),
1509 PHY_TUNING_ENTRY_PMA(0x0c9c, -1, 0x7d),
1510 PHY_TUNING_ENTRY_PMA(0x1c9c, -1, 0x7d),
1512 PHY_TUNING_ENTRY_PMA(0x0e7c, -1, 0x06),
1513 PHY_TUNING_ENTRY_PMA(0x09e0, -1, 0x00),
1514 PHY_TUNING_ENTRY_PMA(0x09e4, -1, 0x36),
1515 PHY_TUNING_ENTRY_PMA(0x1e7c, -1, 0x06),
1516 PHY_TUNING_ENTRY_PMA(0x1e90, -1, 0x00),
1517 PHY_TUNING_ENTRY_PMA(0x1e94, -1, 0x36),
1519 PHY_TUNING_ENTRY_PMA(0x08f0, -1, 0x30),
1520 PHY_TUNING_ENTRY_PMA(0x18f0, -1, 0x30),
1522 PHY_TUNING_ENTRY_PMA(0x0a08, -1, 0x0c),
1523 PHY_TUNING_ENTRY_PMA(0x1a08, -1, 0x0c),
1525 PHY_TUNING_ENTRY_PMA(0x0a0c, -1, 0x05),
1526 PHY_TUNING_ENTRY_PMA(0x1a0c, -1, 0x05),
1528 PHY_TUNING_ENTRY_PMA(0x00f8, -1, 0x1c),
1529 PHY_TUNING_ENTRY_PMA(0x00fc, -1, 0x54),
1531 PHY_TUNING_ENTRY_PMA(0x104c, -1, 0x07),
1532 PHY_TUNING_ENTRY_PMA(0x204c, -1, 0x07),
1535 PHY_TUNING_ENTRY_PMA(0x0ca8, -1, 0x00),
1536 PHY_TUNING_ENTRY_PMA(0x0cac, -1, 0x04),
1537 PHY_TUNING_ENTRY_PMA(0x1ca8, -1, 0x00),
1538 PHY_TUNING_ENTRY_PMA(0x1cac, -1, 0x04),
1540 PHY_TUNING_ENTRY_PMA(0x0cb8, -1, 0x00),
1541 PHY_TUNING_ENTRY_PMA(0x0cbc, -1, 0x04),
1542 PHY_TUNING_ENTRY_PMA(0x1cb8, -1, 0x00),
1543 PHY_TUNING_ENTRY_PMA(0x1cbc, -1, 0x04),
1545 PHY_TUNING_ENTRY_PMA(0x0bb0, 0x03, 0x01),
1546 PHY_TUNING_ENTRY_PMA(0x0bb4, 0xf0, 0xa0),
1547 PHY_TUNING_ENTRY_PMA(0x1bb0, 0x03, 0x01),
1548 PHY_TUNING_ENTRY_PMA(0x1bb4, 0xf0, 0xa0),
1557 BACK_END_MODE_VEC_DISABLE_DATA_MASK, 0),
1582 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_RX_CONTROL, 0,
1591 * 19.6us(0x200) -> 15.3us(0x4)
1599 FIELD_PREP_CONST(HS_TX_COEF_MAP_0_SSTX_LEVEL, 0xb) |
1600 FIELD_PREP_CONST(HS_TX_COEF_MAP_0_SSTX_PRE_SHOOT, 0))),
1604 FIELD_PREP_CONST(LOCAL_COEF_PMA_CENTER_COEF, 0xb)),
1607 /* set skp_remove_th 0x2 -> 0x7 for avoiding retry problem. */
1610 FIELD_PREP_CONST(EBUF_PARAM_SKP_REMOVE_TH_EMPTY_MODE, 0x7)),
1617 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_OUT_VEC_3, PCS_OUT_VEC_B2_SEL_OUT, 0),
1720 phy_drd->reg_phy = devm_platform_ioremap_resource(pdev, 0); in exynos5_usbdrd_phy_probe()
1742 if (channel < 0) in exynos5_usbdrd_phy_probe()
1762 for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) { in exynos5_usbdrd_phy_probe()
1777 case 0: in exynos5_usbdrd_phy_probe()
1797 return 0; in exynos5_usbdrd_phy_probe()