Lines Matching +full:drv +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4x12 support
13 #include "phy-samsung-usb2.h"
18 #define EXYNOS_4x12_UPHYPWR 0x0
20 #define EXYNOS_4x12_UPHYPWR_PHY0_SUSPEND BIT(0)
55 #define EXYNOS_4x12_UPHYCLK 0x4
57 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK (0x7 << 0)
58 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET 0
59 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_9MHZ6 (0x0 << 0)
60 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_10MHZ (0x1 << 0)
61 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0)
62 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_19MHZ2 (0x3 << 0)
63 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_20MHZ (0x4 << 0)
64 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_24MHZ (0x5 << 0)
65 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_50MHZ (0x7 << 0)
67 #define EXYNOS_3250_UPHYCLK_REFCLKSEL (0x2 << 8)
73 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_MASK (0x7f << 10)
75 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_12MHZ (0x24 << 10)
76 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_15MHZ (0x1c << 10)
77 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_16MHZ (0x1a << 10)
78 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_19MHZ2 (0x15 << 10)
79 #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_20MHZ (0x14 << 10)
82 #define EXYNOS_4x12_UPHYRST 0x8
84 #define EXYNOS_4x12_URSTCON_PHY0 BIT(0)
107 #define EXYNOS_4x12_USB_ISOL_OFFSET 0x704
108 #define EXYNOS_4x12_USB_ISOL_OTG BIT(0)
109 #define EXYNOS_4x12_USB_ISOL_HSIC0_OFFSET 0x708
110 #define EXYNOS_4x12_USB_ISOL_HSIC0 BIT(0)
111 #define EXYNOS_4x12_USB_ISOL_HSIC1_OFFSET 0x70c
112 #define EXYNOS_4x12_USB_ISOL_HSIC1 BIT(0)
114 /* Mode switching SUB Device <-> Host */
115 #define EXYNOS_4x12_MODE_SWITCH_OFFSET 0x21c
117 #define EXYNOS_4x12_MODE_SWITCH_DEVICE 0
159 return -EINVAL; in exynos4x12_rate_to_clk()
162 return 0; in exynos4x12_rate_to_clk()
167 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos4x12_isol() local
171 switch (inst->cfg->id) { in exynos4x12_isol()
189 regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask); in exynos4x12_isol()
194 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos4x12_setup_clk() local
197 clk = readl(drv->reg_phy + EXYNOS_4x12_UPHYCLK); in exynos4x12_setup_clk()
200 if (drv->cfg->has_refclk_sel) in exynos4x12_setup_clk()
203 clk |= drv->ref_reg_val << EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET; in exynos4x12_setup_clk()
205 writel(clk, drv->reg_phy + EXYNOS_4x12_UPHYCLK); in exynos4x12_setup_clk()
210 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos4x12_phy_pwr() local
211 u32 rstbits = 0; in exynos4x12_phy_pwr()
212 u32 phypwr = 0; in exynos4x12_phy_pwr()
216 switch (inst->cfg->id) { in exynos4x12_phy_pwr()
240 pwr = readl(drv->reg_phy + EXYNOS_4x12_UPHYPWR); in exynos4x12_phy_pwr()
242 writel(pwr, drv->reg_phy + EXYNOS_4x12_UPHYPWR); in exynos4x12_phy_pwr()
244 rst = readl(drv->reg_phy + EXYNOS_4x12_UPHYRST); in exynos4x12_phy_pwr()
246 writel(rst, drv->reg_phy + EXYNOS_4x12_UPHYRST); in exynos4x12_phy_pwr()
249 writel(rst, drv->reg_phy + EXYNOS_4x12_UPHYRST); in exynos4x12_phy_pwr()
254 pwr = readl(drv->reg_phy + EXYNOS_4x12_UPHYPWR); in exynos4x12_phy_pwr()
256 writel(pwr, drv->reg_phy + EXYNOS_4x12_UPHYPWR); in exynos4x12_phy_pwr()
262 if (inst->int_cnt++ > 0) in exynos4x12_power_on_int()
266 exynos4x12_isol(inst, 0); in exynos4x12_power_on_int()
272 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos4x12_power_on() local
274 if (inst->ext_cnt++ > 0) in exynos4x12_power_on()
275 return 0; in exynos4x12_power_on()
277 if (inst->cfg->id == EXYNOS4x12_HOST) { in exynos4x12_power_on()
278 regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET, in exynos4x12_power_on()
281 exynos4x12_power_on_int(&drv->instances[EXYNOS4x12_DEVICE]); in exynos4x12_power_on()
284 if (inst->cfg->id == EXYNOS4x12_DEVICE && drv->cfg->has_mode_switch) in exynos4x12_power_on()
285 regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET, in exynos4x12_power_on()
289 if (inst->cfg->id == EXYNOS4x12_HSIC0 || in exynos4x12_power_on()
290 inst->cfg->id == EXYNOS4x12_HSIC1) { in exynos4x12_power_on()
291 exynos4x12_power_on_int(&drv->instances[EXYNOS4x12_DEVICE]); in exynos4x12_power_on()
292 exynos4x12_power_on_int(&drv->instances[EXYNOS4x12_HOST]); in exynos4x12_power_on()
297 return 0; in exynos4x12_power_on()
302 if (inst->int_cnt-- > 1) in exynos4x12_power_off_int()
306 exynos4x12_phy_pwr(inst, 0); in exynos4x12_power_off_int()
311 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos4x12_power_off() local
313 if (inst->ext_cnt-- > 1) in exynos4x12_power_off()
314 return 0; in exynos4x12_power_off()
316 if (inst->cfg->id == EXYNOS4x12_DEVICE && drv->cfg->has_mode_switch) in exynos4x12_power_off()
317 regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET, in exynos4x12_power_off()
321 if (inst->cfg->id == EXYNOS4x12_HOST) in exynos4x12_power_off()
322 exynos4x12_power_off_int(&drv->instances[EXYNOS4x12_DEVICE]); in exynos4x12_power_off()
324 if (inst->cfg->id == EXYNOS4x12_HSIC0 || in exynos4x12_power_off()
325 inst->cfg->id == EXYNOS4x12_HSIC1) { in exynos4x12_power_off()
326 exynos4x12_power_off_int(&drv->instances[EXYNOS4x12_DEVICE]); in exynos4x12_power_off()
327 exynos4x12_power_off_int(&drv->instances[EXYNOS4x12_HOST]); in exynos4x12_power_off()
332 return 0; in exynos4x12_power_off()