Lines Matching +full:pwr +full:- +full:reg
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4210 support
13 #include "phy-samsung-usb2.h"
87 /* Mode switching SUB Device <-> Host */
105 static int exynos4210_rate_to_clk(unsigned long rate, u32 *reg) in exynos4210_rate_to_clk() argument
109 *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ; in exynos4210_rate_to_clk()
112 *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ; in exynos4210_rate_to_clk()
115 *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ; in exynos4210_rate_to_clk()
118 return -EINVAL; in exynos4210_rate_to_clk()
126 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos4210_isol()
130 switch (inst->cfg->id) { in exynos4210_isol()
143 regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask); in exynos4210_isol()
148 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos4210_phy_pwr()
152 u32 pwr; in exynos4210_phy_pwr() local
155 switch (inst->cfg->id) { in exynos4210_phy_pwr()
167 writel(on, drv->reg_phy + EXYNOS_4210_UPHY1CON); in exynos4210_phy_pwr()
182 clk = readl(drv->reg_phy + EXYNOS_4210_UPHYCLK); in exynos4210_phy_pwr()
184 clk |= drv->ref_reg_val << EXYNOS_4210_UPHYCLK_PHYFSEL_OFFSET; in exynos4210_phy_pwr()
185 writel(clk, drv->reg_phy + EXYNOS_4210_UPHYCLK); in exynos4210_phy_pwr()
187 pwr = readl(drv->reg_phy + EXYNOS_4210_UPHYPWR); in exynos4210_phy_pwr()
188 pwr &= ~phypwr; in exynos4210_phy_pwr()
189 writel(pwr, drv->reg_phy + EXYNOS_4210_UPHYPWR); in exynos4210_phy_pwr()
191 rst = readl(drv->reg_phy + EXYNOS_4210_UPHYRST); in exynos4210_phy_pwr()
193 writel(rst, drv->reg_phy + EXYNOS_4210_UPHYRST); in exynos4210_phy_pwr()
196 writel(rst, drv->reg_phy + EXYNOS_4210_UPHYRST); in exynos4210_phy_pwr()
201 pwr = readl(drv->reg_phy + EXYNOS_4210_UPHYPWR); in exynos4210_phy_pwr()
202 pwr |= phypwr; in exynos4210_phy_pwr()
203 writel(pwr, drv->reg_phy + EXYNOS_4210_UPHYPWR); in exynos4210_phy_pwr()
209 /* Order of initialisation is important - first power then isolation */ in exynos4210_power_on()