Lines Matching +full:enable +full:- +full:ssc
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
104 u16 enable; member
171 temp = readl(priv->mmio + reg); in rockchip_combphy_updatel()
173 writel(temp, priv->mmio + reg); in rockchip_combphy_updatel()
181 tmp = en ? reg->enable : reg->disable; in rockchip_combphy_param_write()
182 mask = GENMASK(reg->bitend, reg->bitstart); in rockchip_combphy_param_write()
183 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in rockchip_combphy_param_write()
185 return regmap_write(base, reg->offset, val); in rockchip_combphy_param_write()
190 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_is_ready()
193 mask = GENMASK(cfg->pipe_phy_status.bitend, in rockchip_combphy_is_ready()
194 cfg->pipe_phy_status.bitstart); in rockchip_combphy_is_ready()
196 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); in rockchip_combphy_is_ready()
197 val = (val & mask) >> cfg->pipe_phy_status.bitstart; in rockchip_combphy_is_ready()
205 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_init()
209 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); in rockchip_combphy_init()
211 dev_err(priv->dev, "failed to enable clks\n"); in rockchip_combphy_init()
215 switch (priv->type) { in rockchip_combphy_init()
221 if (priv->cfg->combphy_cfg) in rockchip_combphy_init()
222 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_init()
225 dev_err(priv->dev, "incompatible PHY type\n"); in rockchip_combphy_init()
226 ret = -EINVAL; in rockchip_combphy_init()
231 dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type); in rockchip_combphy_init()
235 ret = reset_control_deassert(priv->phy_rst); in rockchip_combphy_init()
239 if (priv->type == PHY_TYPE_USB3) { in rockchip_combphy_init()
242 val == cfg->pipe_phy_status.enable, in rockchip_combphy_init()
245 dev_warn(priv->dev, "wait phy status ready timeout\n"); in rockchip_combphy_init()
251 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rockchip_combphy_init()
260 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rockchip_combphy_exit()
261 reset_control_assert(priv->phy_rst); in rockchip_combphy_exit()
276 if (args->args_count != 1) { in rockchip_combphy_xlate()
278 return ERR_PTR(-EINVAL); in rockchip_combphy_xlate()
281 if (priv->type != PHY_NONE && priv->type != args->args[0]) in rockchip_combphy_xlate()
283 args->args[0], priv->type); in rockchip_combphy_xlate()
285 priv->type = args->args[0]; in rockchip_combphy_xlate()
287 return priv->phy; in rockchip_combphy_xlate()
294 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); in rockchip_combphy_parse_dt()
295 if (priv->num_clks < 1) in rockchip_combphy_parse_dt()
296 return -EINVAL; in rockchip_combphy_parse_dt()
298 priv->refclk = NULL; in rockchip_combphy_parse_dt()
299 for (i = 0; i < priv->num_clks; i++) { in rockchip_combphy_parse_dt()
300 if (!strncmp(priv->clks[i].id, "ref", 3)) { in rockchip_combphy_parse_dt()
301 priv->refclk = priv->clks[i].clk; in rockchip_combphy_parse_dt()
306 if (!priv->refclk) { in rockchip_combphy_parse_dt()
308 return -EINVAL; in rockchip_combphy_parse_dt()
311 priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf"); in rockchip_combphy_parse_dt()
312 if (IS_ERR(priv->pipe_grf)) { in rockchip_combphy_parse_dt()
313 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); in rockchip_combphy_parse_dt()
314 return PTR_ERR(priv->pipe_grf); in rockchip_combphy_parse_dt()
317 priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf"); in rockchip_combphy_parse_dt()
318 if (IS_ERR(priv->phy_grf)) { in rockchip_combphy_parse_dt()
319 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); in rockchip_combphy_parse_dt()
320 return PTR_ERR(priv->phy_grf); in rockchip_combphy_parse_dt()
323 priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc"); in rockchip_combphy_parse_dt()
325 priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); in rockchip_combphy_parse_dt()
327 priv->phy_rst = devm_reset_control_get_exclusive(dev, "phy"); in rockchip_combphy_parse_dt()
329 if (PTR_ERR(priv->phy_rst) == -ENOENT) in rockchip_combphy_parse_dt()
330 priv->phy_rst = devm_reset_control_array_get_exclusive(dev); in rockchip_combphy_parse_dt()
331 if (IS_ERR(priv->phy_rst)) in rockchip_combphy_parse_dt()
332 return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); in rockchip_combphy_parse_dt()
340 struct device *dev = &pdev->dev; in rockchip_combphy_probe()
349 return -EINVAL; in rockchip_combphy_probe()
354 return -ENOMEM; in rockchip_combphy_probe()
356 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in rockchip_combphy_probe()
357 if (IS_ERR(priv->mmio)) { in rockchip_combphy_probe()
358 ret = PTR_ERR(priv->mmio); in rockchip_combphy_probe()
362 /* find the phy-id from the io address */ in rockchip_combphy_probe()
363 priv->id = -ENODEV; in rockchip_combphy_probe()
364 for (id = 0; id < phy_cfg->num_phys; id++) { in rockchip_combphy_probe()
365 if (res->start == phy_cfg->phy_ids[id]) { in rockchip_combphy_probe()
366 priv->id = id; in rockchip_combphy_probe()
371 priv->dev = dev; in rockchip_combphy_probe()
372 priv->type = PHY_NONE; in rockchip_combphy_probe()
373 priv->cfg = phy_cfg; in rockchip_combphy_probe()
379 ret = reset_control_assert(priv->phy_rst); in rockchip_combphy_probe()
385 priv->phy = devm_phy_create(dev, NULL, &rockchip_combphy_ops); in rockchip_combphy_probe()
386 if (IS_ERR(priv->phy)) { in rockchip_combphy_probe()
388 return PTR_ERR(priv->phy); in rockchip_combphy_probe()
392 phy_set_drvdata(priv->phy, priv); in rockchip_combphy_probe()
401 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3568_combphy_cfg()
405 switch (priv->type) { in rk3568_combphy_cfg()
407 /* Set SSC downward spread spectrum. */ in rk3568_combphy_cfg()
412 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3568_combphy_cfg()
413 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3568_combphy_cfg()
414 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3568_combphy_cfg()
415 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3568_combphy_cfg()
419 /* Set SSC downward spread spectrum. */ in rk3568_combphy_cfg()
424 /* Enable adaptive CTLE for USB3.0 Rx. */ in rk3568_combphy_cfg()
425 val = readl(priv->mmio + PHYREG15); in rk3568_combphy_cfg()
427 writel(val, priv->mmio + PHYREG15); in rk3568_combphy_cfg()
434 /* Enable controlling random jitter. */ in rk3568_combphy_cfg()
435 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3568_combphy_cfg()
442 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3568_combphy_cfg()
443 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3568_combphy_cfg()
445 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3568_combphy_cfg()
446 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3568_combphy_cfg()
447 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3568_combphy_cfg()
448 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3568_combphy_cfg()
452 /* Enable adaptive CTLE for SATA Rx. */ in rk3568_combphy_cfg()
453 val = readl(priv->mmio + PHYREG15); in rk3568_combphy_cfg()
455 writel(val, priv->mmio + PHYREG15); in rk3568_combphy_cfg()
462 writel(val, priv->mmio + PHYREG7); in rk3568_combphy_cfg()
464 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3568_combphy_cfg()
465 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3568_combphy_cfg()
466 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3568_combphy_cfg()
467 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3568_combphy_cfg()
468 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3568_combphy_cfg()
472 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
473 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
474 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
475 rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); in rk3568_combphy_cfg()
479 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
480 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
481 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); in rk3568_combphy_cfg()
482 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
483 rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); in rk3568_combphy_cfg()
487 dev_err(priv->dev, "incompatible PHY type\n"); in rk3568_combphy_cfg()
488 return -EINVAL; in rk3568_combphy_cfg()
491 rate = clk_get_rate(priv->refclk); in rk3568_combphy_cfg()
495 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { in rk3568_combphy_cfg()
501 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); in rk3568_combphy_cfg()
506 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3568_combphy_cfg()
510 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3568_combphy_cfg()
511 if (priv->type == PHY_TYPE_PCIE) { in rk3568_combphy_cfg()
517 /* Enable controlling random jitter. */ in rk3568_combphy_cfg()
518 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3568_combphy_cfg()
524 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3568_combphy_cfg()
525 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3568_combphy_cfg()
526 } else if (priv->type == PHY_TYPE_SATA) { in rk3568_combphy_cfg()
535 dev_err(priv->dev, "unsupported rate: %lu\n", rate); in rk3568_combphy_cfg()
536 return -EINVAL; in rk3568_combphy_cfg()
539 if (priv->ext_refclk) { in rk3568_combphy_cfg()
540 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3568_combphy_cfg()
541 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3568_combphy_cfg()
546 val = readl(priv->mmio + PHYREG14); in rk3568_combphy_cfg()
548 writel(val, priv->mmio + PHYREG14); in rk3568_combphy_cfg()
552 if (priv->enable_ssc) { in rk3568_combphy_cfg()
553 val = readl(priv->mmio + PHYREG8); in rk3568_combphy_cfg()
555 writel(val, priv->mmio + PHYREG8); in rk3568_combphy_cfg()
562 /* pipe-phy-grf */
589 /* pipe-grf */
607 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3576_combphy_cfg()
611 switch (priv->type) { in rk3576_combphy_cfg()
613 /* Set SSC downward spread spectrum */ in rk3576_combphy_cfg()
617 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3576_combphy_cfg()
618 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3576_combphy_cfg()
619 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3576_combphy_cfg()
620 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3576_combphy_cfg()
624 /* Set SSC downward spread spectrum */ in rk3576_combphy_cfg()
628 /* Enable adaptive CTLE for USB3.0 Rx */ in rk3576_combphy_cfg()
629 val = readl(priv->mmio + PHYREG15); in rk3576_combphy_cfg()
631 writel(val, priv->mmio + PHYREG15); in rk3576_combphy_cfg()
637 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3576_combphy_cfg()
644 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3576_combphy_cfg()
647 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3576_combphy_cfg()
650 writel(PHYREG21_RX_SQUELCH_VAL, priv->mmio + PHYREG21); in rk3576_combphy_cfg()
652 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3576_combphy_cfg()
653 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3576_combphy_cfg()
654 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3576_combphy_cfg()
658 /* Enable adaptive CTLE for SATA Rx */ in rk3576_combphy_cfg()
659 val = readl(priv->mmio + PHYREG15); in rk3576_combphy_cfg()
661 writel(val, priv->mmio + PHYREG15); in rk3576_combphy_cfg()
666 writel(val, priv->mmio + PHYREG7); in rk3576_combphy_cfg()
668 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3576_combphy_cfg()
669 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3576_combphy_cfg()
670 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3576_combphy_cfg()
671 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3576_combphy_cfg()
672 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3576_combphy_cfg()
673 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); in rk3576_combphy_cfg()
677 dev_err(priv->dev, "incompatible PHY type\n"); in rk3576_combphy_cfg()
678 return -EINVAL; in rk3576_combphy_cfg()
681 rate = clk_get_rate(priv->refclk); in rk3576_combphy_cfg()
685 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); in rk3576_combphy_cfg()
686 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { in rk3576_combphy_cfg()
692 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); in rk3576_combphy_cfg()
693 } else if (priv->type == PHY_TYPE_PCIE) { in rk3576_combphy_cfg()
700 writel(0x00, priv->mmio + PHYREG27); in rk3576_combphy_cfg()
708 writel(0x90, priv->mmio + PHYREG11); in rk3576_combphy_cfg()
709 writel(0x02, priv->mmio + PHYREG12); in rk3576_combphy_cfg()
710 writel(0x57, priv->mmio + PHYREG14); in rk3576_combphy_cfg()
712 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); in rk3576_combphy_cfg()
717 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3576_combphy_cfg()
721 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3576_combphy_cfg()
722 if (priv->type == PHY_TYPE_PCIE) { in rk3576_combphy_cfg()
724 writel(0xc0, priv->mmio + PHYREG30); in rk3576_combphy_cfg()
732 writel(0x4c, priv->mmio + PHYREG27); in rk3576_combphy_cfg()
742 writel(0x90, priv->mmio + PHYREG11); in rk3576_combphy_cfg()
743 writel(0x43, priv->mmio + PHYREG12); in rk3576_combphy_cfg()
744 writel(0x88, priv->mmio + PHYREG13); in rk3576_combphy_cfg()
745 writel(0x56, priv->mmio + PHYREG14); in rk3576_combphy_cfg()
746 } else if (priv->type == PHY_TYPE_SATA) { in rk3576_combphy_cfg()
752 /* ssc ppm adjust to 3500ppm */ in rk3576_combphy_cfg()
760 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3576_combphy_cfg()
761 return -EINVAL; in rk3576_combphy_cfg()
764 if (priv->ext_refclk) { in rk3576_combphy_cfg()
765 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3576_combphy_cfg()
766 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3576_combphy_cfg()
772 writel(0x0c, priv->mmio + PHYREG27); in rk3576_combphy_cfg()
782 writel(0x90, priv->mmio + PHYREG11); in rk3576_combphy_cfg()
783 writel(0x43, priv->mmio + PHYREG12); in rk3576_combphy_cfg()
784 writel(0x88, priv->mmio + PHYREG13); in rk3576_combphy_cfg()
785 writel(0x56, priv->mmio + PHYREG14); in rk3576_combphy_cfg()
789 if (priv->enable_ssc) { in rk3576_combphy_cfg()
790 val = readl(priv->mmio + PHYREG8); in rk3576_combphy_cfg()
792 writel(val, priv->mmio + PHYREG8); in rk3576_combphy_cfg()
794 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) { in rk3576_combphy_cfg()
796 writel(0x00, priv->mmio + PHYREG17); in rk3576_combphy_cfg()
797 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3576_combphy_cfg()
800 writel(0x00, priv->mmio + PHYREG27); in rk3576_combphy_cfg()
809 writel(0x90, priv->mmio + PHYREG11); in rk3576_combphy_cfg()
810 writel(0x02, priv->mmio + PHYREG12); in rk3576_combphy_cfg()
811 writel(0x08, priv->mmio + PHYREG13); in rk3576_combphy_cfg()
812 writel(0x57, priv->mmio + PHYREG14); in rk3576_combphy_cfg()
813 writel(0x40, priv->mmio + PHYREG15); in rk3576_combphy_cfg()
815 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); in rk3576_combphy_cfg()
818 writel(val, priv->mmio + PHYREG33); in rk3576_combphy_cfg()
826 /* pipe-phy-grf */
850 /* php-grf */
867 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3588_combphy_cfg()
871 switch (priv->type) { in rk3588_combphy_cfg()
873 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3588_combphy_cfg()
874 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3588_combphy_cfg()
875 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3588_combphy_cfg()
876 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3588_combphy_cfg()
877 switch (priv->id) { in rk3588_combphy_cfg()
879 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true); in rk3588_combphy_cfg()
882 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true); in rk3588_combphy_cfg()
887 /* Set SSC downward spread spectrum */ in rk3588_combphy_cfg()
892 /* Enable adaptive CTLE for USB3.0 Rx. */ in rk3588_combphy_cfg()
893 val = readl(priv->mmio + PHYREG15); in rk3588_combphy_cfg()
895 writel(val, priv->mmio + PHYREG15); in rk3588_combphy_cfg()
902 /* Enable controlling random jitter. */ in rk3588_combphy_cfg()
903 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3588_combphy_cfg()
910 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3588_combphy_cfg()
911 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3588_combphy_cfg()
913 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3588_combphy_cfg()
914 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3588_combphy_cfg()
915 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3588_combphy_cfg()
918 /* Enable adaptive CTLE for SATA Rx. */ in rk3588_combphy_cfg()
919 val = readl(priv->mmio + PHYREG15); in rk3588_combphy_cfg()
921 writel(val, priv->mmio + PHYREG15); in rk3588_combphy_cfg()
928 writel(val, priv->mmio + PHYREG7); in rk3588_combphy_cfg()
930 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3588_combphy_cfg()
931 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3588_combphy_cfg()
932 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3588_combphy_cfg()
933 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3588_combphy_cfg()
934 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3588_combphy_cfg()
935 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); in rk3588_combphy_cfg()
940 dev_err(priv->dev, "incompatible PHY type\n"); in rk3588_combphy_cfg()
941 return -EINVAL; in rk3588_combphy_cfg()
944 rate = clk_get_rate(priv->refclk); in rk3588_combphy_cfg()
948 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { in rk3588_combphy_cfg()
954 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); in rk3588_combphy_cfg()
959 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3588_combphy_cfg()
962 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3588_combphy_cfg()
963 if (priv->type == PHY_TYPE_PCIE) { in rk3588_combphy_cfg()
969 /* Enable controlling random jitter. */ in rk3588_combphy_cfg()
970 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3588_combphy_cfg()
973 writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27); in rk3588_combphy_cfg()
976 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3588_combphy_cfg()
977 } else if (priv->type == PHY_TYPE_SATA) { in rk3588_combphy_cfg()
985 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3588_combphy_cfg()
986 return -EINVAL; in rk3588_combphy_cfg()
989 if (priv->ext_refclk) { in rk3588_combphy_cfg()
990 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3588_combphy_cfg()
991 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3588_combphy_cfg()
996 val = readl(priv->mmio + PHYREG14); in rk3588_combphy_cfg()
998 writel(val, priv->mmio + PHYREG14); in rk3588_combphy_cfg()
1002 if (priv->enable_ssc) { in rk3588_combphy_cfg()
1003 val = readl(priv->mmio + PHYREG8); in rk3588_combphy_cfg()
1005 writel(val, priv->mmio + PHYREG8); in rk3588_combphy_cfg()
1012 /* pipe-phy-grf */
1033 /* pipe-grf */
1053 .compatible = "rockchip,rk3568-naneng-combphy",
1057 .compatible = "rockchip,rk3576-naneng-combphy",
1061 .compatible = "rockchip,rk3588-naneng-combphy",
1071 .name = "rockchip-naneng-combphy",