Lines Matching +full:4 +full:ohm
30 #define PHYREG7_TX_RTERM_MASK GENMASK(7, 4)
31 #define PHYREG7_TX_RTERM_SHIFT 4
38 #define PHYREG8_SSC_EN BIT(4)
48 #define PHYREG12_PLL_LPF_ADJ_VALUE 4
51 #define PHYREG13_RESISTER_MASK GENMASK(5, 4)
82 #define PHYREG32_SSC_MASK GENMASK(7, 4)
83 #define PHYREG32_SSC_DIR_MASK GENMASK(5, 4)
84 #define PHYREG32_SSC_DIR_SHIFT 4
92 #define PHYREG33_PLL_KVCO_MASK GENMASK(4, 2)
95 #define PHYREG33_PLL_KVCO_VALUE_RK3576 4
457 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. in rk3568_combphy_cfg()
458 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) in rk3568_combphy_cfg()
569 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
663 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ in rk3576_combphy_cfg()
831 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
923 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. in rk3588_combphy_cfg()
924 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) in rk3588_combphy_cfg()
965 val = 4 << PHYREG33_PLL_KVCO_SHIFT; in rk3588_combphy_cfg()
1017 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },