Lines Matching +full:imp +full:- +full:res +full:- +full:offset +full:- +full:value
1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/nvmem-consumer.h>
22 #include <dt-bindings/phy/phy-qcom-qusb2.h>
101 unsigned int offset; member
105 * if yes, then offset gives index in the reg-layout
112 .offset = o, \
118 .offset = o, \
123 /* set of registers with offsets different per-PHY */
304 /* offset to PHY_CLK_SCHEME register in TCSR map */
316 /* true if TUNE1 register must be updated by fused value, else TUNE2 */
322 /* true if PHY default clk scheme is single-ended */
422 "vdd", "vdda-pll", "vdda-phy-dpdm",
427 /* struct override_param - structure holding qusb2 v2 phy overriding param
429 * to value
433 u8 value; member
436 /*struct override_params - structure holding qusb2 v2 phy overriding params
437 * @imp_res_offset: rescode offset to be updated in IMP_CTRL1 register
439 * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register
440 * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
456 * struct qusb2_phy - structure holding qusb2 phy attributes
468 * @cell: nvmem cell containing phy tuning value
473 * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
498 static inline void qusb2_write_mask(void __iomem *base, u32 offset, in qusb2_write_mask() argument
503 reg = readl(base + offset); in qusb2_write_mask()
506 writel(reg, base + offset); in qusb2_write_mask()
509 readl(base + offset); in qusb2_write_mask()
512 static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val) in qusb2_setbits() argument
516 reg = readl(base + offset); in qusb2_setbits()
518 writel(reg, base + offset); in qusb2_setbits()
521 readl(base + offset); in qusb2_setbits()
524 static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val) in qusb2_clrbits() argument
528 reg = readl(base + offset); in qusb2_clrbits()
530 writel(reg, base + offset); in qusb2_clrbits()
533 readl(base + offset); in qusb2_clrbits()
545 writel(tbl[i].val, base + regs[tbl[i].offset]); in qcom_qusb2_phy_configure()
547 writel(tbl[i].val, base + tbl[i].offset); in qcom_qusb2_phy_configure()
557 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_override_phy_params()
558 struct override_params *or = &qphy->overrides; in qusb2_phy_override_phy_params()
560 if (or->imp_res_offset.override) in qusb2_phy_override_phy_params()
561 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1, in qusb2_phy_override_phy_params()
562 or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
565 if (or->bias_ctrl.override) in qusb2_phy_override_phy_params()
566 qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2, in qusb2_phy_override_phy_params()
567 or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
570 if (or->charge_ctrl.override) in qusb2_phy_override_phy_params()
571 qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2, in qusb2_phy_override_phy_params()
572 or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
575 if (or->hstx_trim.override) in qusb2_phy_override_phy_params()
576 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
577 or->hstx_trim.value << HSTX_TRIM_SHIFT, in qusb2_phy_override_phy_params()
580 if (or->preemphasis.override) in qusb2_phy_override_phy_params()
581 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
582 or->preemphasis.value << PREEMPHASIS_EN_SHIFT, in qusb2_phy_override_phy_params()
585 if (or->preemphasis_width.override) { in qusb2_phy_override_phy_params()
586 if (or->preemphasis_width.value == in qusb2_phy_override_phy_params()
588 qusb2_setbits(qphy->base, in qusb2_phy_override_phy_params()
589 cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
592 qusb2_clrbits(qphy->base, in qusb2_phy_override_phy_params()
593 cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
597 if (or->hsdisc_trim.override) in qusb2_phy_override_phy_params()
598 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], in qusb2_phy_override_phy_params()
599 or->hsdisc_trim.value << HSDISC_TRIM_SHIFT, in qusb2_phy_override_phy_params()
604 * Fetches HS Tx tuning value from nvmem and sets the
606 * For error case, skip setting the value and use the default value.
610 struct device *dev = &qphy->phy->dev; in qusb2_phy_set_tune2_param()
611 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_set_tune2_param()
615 if (!qphy->cell) in qusb2_phy_set_tune2_param()
620 * If efuse register shows value as 0x0 (indicating value is not in qusb2_phy_set_tune2_param()
622 * then use default value for high nibble that we have already in qusb2_phy_set_tune2_param()
625 val = nvmem_cell_read(qphy->cell, NULL); in qusb2_phy_set_tune2_param()
627 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); in qusb2_phy_set_tune2_param()
633 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); in qusb2_phy_set_tune2_param()
637 /* Fused TUNE1/2 value is the higher nibble only */ in qusb2_phy_set_tune2_param()
638 if (cfg->update_tune1_with_efuse) in qusb2_phy_set_tune2_param()
639 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_set_tune2_param()
642 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], in qusb2_phy_set_tune2_param()
651 qphy->mode = mode; in qusb2_phy_set_mode()
659 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_runtime_suspend()
662 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode); in qusb2_phy_runtime_suspend()
664 if (!qphy->phy_initialized) { in qusb2_phy_runtime_suspend()
672 * current D+/D- levels are e.g. if currently D+ high, D- low in qusb2_phy_runtime_suspend()
673 * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high in qusb2_phy_runtime_suspend()
676 switch (qphy->mode) { in qusb2_phy_runtime_suspend()
694 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); in qusb2_phy_runtime_suspend()
697 if (cfg->has_pll_override) { in qusb2_phy_runtime_suspend()
698 qusb2_setbits(qphy->base, in qusb2_phy_runtime_suspend()
699 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], in qusb2_phy_runtime_suspend()
704 /* enable phy auto-resume only if device is connected on bus */ in qusb2_phy_runtime_suspend()
705 if (qphy->mode != PHY_MODE_INVALID) { in qusb2_phy_runtime_suspend()
706 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], in qusb2_phy_runtime_suspend()
707 cfg->autoresume_en); in qusb2_phy_runtime_suspend()
709 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], in qusb2_phy_runtime_suspend()
710 cfg->autoresume_en); in qusb2_phy_runtime_suspend()
713 if (!qphy->has_se_clk_scheme) in qusb2_phy_runtime_suspend()
714 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_runtime_suspend()
716 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_runtime_suspend()
717 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_runtime_suspend()
725 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_runtime_resume()
728 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode); in qusb2_phy_runtime_resume()
730 if (!qphy->phy_initialized) { in qusb2_phy_runtime_resume()
735 ret = clk_prepare_enable(qphy->iface_clk); in qusb2_phy_runtime_resume()
741 ret = clk_prepare_enable(qphy->cfg_ahb_clk); in qusb2_phy_runtime_resume()
747 if (!qphy->has_se_clk_scheme) { in qusb2_phy_runtime_resume()
748 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_runtime_resume()
755 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); in qusb2_phy_runtime_resume()
758 if (cfg->has_pll_override) { in qusb2_phy_runtime_resume()
759 qusb2_clrbits(qphy->base, in qusb2_phy_runtime_resume()
760 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], in qusb2_phy_runtime_resume()
767 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_runtime_resume()
769 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_runtime_resume()
777 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_init()
782 dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__); in qusb2_phy_init()
785 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_init()
789 ret = clk_prepare_enable(qphy->iface_clk); in qusb2_phy_init()
791 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret); in qusb2_phy_init()
796 ret = clk_prepare_enable(qphy->cfg_ahb_clk); in qusb2_phy_init()
798 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); in qusb2_phy_init()
803 ret = reset_control_assert(qphy->phy_reset); in qusb2_phy_init()
805 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); in qusb2_phy_init()
812 ret = reset_control_deassert(qphy->phy_reset); in qusb2_phy_init()
814 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); in qusb2_phy_init()
819 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_init()
820 qphy->cfg->disable_ctrl); in qusb2_phy_init()
822 if (cfg->has_pll_test) { in qusb2_phy_init()
823 /* save reset value to override reference clock scheme later */ in qusb2_phy_init()
824 val = readl(qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
827 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, in qusb2_phy_init()
828 cfg->tbl_num); in qusb2_phy_init()
833 /* Set efuse value for tuning the PHY */ in qusb2_phy_init()
837 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_init()
846 * value hardcoded in the configuration. in qusb2_phy_init()
848 qphy->has_se_clk_scheme = cfg->se_clk_scheme_default; in qusb2_phy_init()
851 * read TCSR_PHY_CLK_SCHEME register to check if single-ended in qusb2_phy_init()
853 * ref_clk and use single-ended clock, otherwise use differential in qusb2_phy_init()
856 if (qphy->tcsr) { in qusb2_phy_init()
857 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, in qusb2_phy_init()
860 dev_err(&phy->dev, "failed to read clk scheme reg\n"); in qusb2_phy_init()
866 dev_vdbg(&phy->dev, "%s(): select differential clk\n", in qusb2_phy_init()
868 qphy->has_se_clk_scheme = false; in qusb2_phy_init()
870 dev_vdbg(&phy->dev, "%s(): select single-ended clk\n", in qusb2_phy_init()
875 if (!qphy->has_se_clk_scheme) { in qusb2_phy_init()
876 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_init()
878 dev_err(&phy->dev, "failed to enable ref clk, %d\n", in qusb2_phy_init()
884 if (cfg->has_pll_test) { in qusb2_phy_init()
885 if (!qphy->has_se_clk_scheme) in qusb2_phy_init()
890 writel(val, qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
893 readl(qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
899 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); in qusb2_phy_init()
900 if (!(val & cfg->mask_core_ready)) { in qusb2_phy_init()
901 dev_err(&phy->dev, in qusb2_phy_init()
903 ret = -EBUSY; in qusb2_phy_init()
906 qphy->phy_initialized = true; in qusb2_phy_init()
911 if (!qphy->has_se_clk_scheme) in qusb2_phy_init()
912 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_init()
914 reset_control_assert(qphy->phy_reset); in qusb2_phy_init()
916 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_init()
918 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_init()
920 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_init()
930 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_exit()
931 qphy->cfg->disable_ctrl); in qusb2_phy_exit()
933 if (!qphy->has_se_clk_scheme) in qusb2_phy_exit()
934 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_exit()
936 reset_control_assert(qphy->phy_reset); in qusb2_phy_exit()
938 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_exit()
939 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_exit()
941 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_exit()
943 qphy->phy_initialized = false; in qusb2_phy_exit()
957 .compatible = "qcom,ipq5424-qusb2-phy",
960 .compatible = "qcom,ipq6018-qusb2-phy",
963 .compatible = "qcom,ipq8074-qusb2-phy",
966 .compatible = "qcom,ipq9574-qusb2-phy",
969 .compatible = "qcom,msm8953-qusb2-phy",
972 .compatible = "qcom,msm8996-qusb2-phy",
975 .compatible = "qcom,msm8998-qusb2-phy",
978 .compatible = "qcom,qcs615-qusb2-phy",
981 .compatible = "qcom,qcm2290-qusb2-phy",
984 .compatible = "qcom,sdm660-qusb2-phy",
987 .compatible = "qcom,sm4250-qusb2-phy",
990 .compatible = "qcom,sm6115-qusb2-phy",
995 * trees that didn't include "qcom,qusb2-v2-phy"
997 .compatible = "qcom,sdm845-qusb2-phy",
1000 .compatible = "qcom,qusb2-v2-phy",
1014 struct device *dev = &pdev->dev; in qusb2_phy_probe()
1020 u32 value; in qusb2_phy_probe() local
1025 return -ENOMEM; in qusb2_phy_probe()
1026 or = &qphy->overrides; in qusb2_phy_probe()
1028 qphy->base = devm_platform_ioremap_resource(pdev, 0); in qusb2_phy_probe()
1029 if (IS_ERR(qphy->base)) in qusb2_phy_probe()
1030 return PTR_ERR(qphy->base); in qusb2_phy_probe()
1032 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb"); in qusb2_phy_probe()
1033 if (IS_ERR(qphy->cfg_ahb_clk)) in qusb2_phy_probe()
1034 return dev_err_probe(dev, PTR_ERR(qphy->cfg_ahb_clk), in qusb2_phy_probe()
1037 qphy->ref_clk = devm_clk_get(dev, "ref"); in qusb2_phy_probe()
1038 if (IS_ERR(qphy->ref_clk)) in qusb2_phy_probe()
1039 return dev_err_probe(dev, PTR_ERR(qphy->ref_clk), in qusb2_phy_probe()
1042 qphy->iface_clk = devm_clk_get_optional(dev, "iface"); in qusb2_phy_probe()
1043 if (IS_ERR(qphy->iface_clk)) in qusb2_phy_probe()
1044 return PTR_ERR(qphy->iface_clk); in qusb2_phy_probe()
1046 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0); in qusb2_phy_probe()
1047 if (IS_ERR(qphy->phy_reset)) { in qusb2_phy_probe()
1049 return PTR_ERR(qphy->phy_reset); in qusb2_phy_probe()
1052 num = ARRAY_SIZE(qphy->vregs); in qusb2_phy_probe()
1054 qphy->vregs[i].supply = qusb2_phy_vreg_names[i]; in qusb2_phy_probe()
1056 ret = devm_regulator_bulk_get(dev, num, qphy->vregs); in qusb2_phy_probe()
1062 qphy->cfg = of_device_get_match_data(dev); in qusb2_phy_probe()
1064 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, in qusb2_phy_probe()
1065 "qcom,tcsr-syscon"); in qusb2_phy_probe()
1066 if (IS_ERR(qphy->tcsr)) { in qusb2_phy_probe()
1068 qphy->tcsr = NULL; in qusb2_phy_probe()
1071 qphy->cell = devm_nvmem_cell_get(dev, NULL); in qusb2_phy_probe()
1072 if (IS_ERR(qphy->cell)) { in qusb2_phy_probe()
1073 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER) in qusb2_phy_probe()
1074 return -EPROBE_DEFER; in qusb2_phy_probe()
1075 qphy->cell = NULL; in qusb2_phy_probe()
1076 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n"); in qusb2_phy_probe()
1079 if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value", in qusb2_phy_probe()
1080 &value)) { in qusb2_phy_probe()
1081 or->imp_res_offset.value = (u8)value; in qusb2_phy_probe()
1082 or->imp_res_offset.override = true; in qusb2_phy_probe()
1085 if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value", in qusb2_phy_probe()
1086 &value)) { in qusb2_phy_probe()
1087 or->bias_ctrl.value = (u8)value; in qusb2_phy_probe()
1088 or->bias_ctrl.override = true; in qusb2_phy_probe()
1091 if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value", in qusb2_phy_probe()
1092 &value)) { in qusb2_phy_probe()
1093 or->charge_ctrl.value = (u8)value; in qusb2_phy_probe()
1094 or->charge_ctrl.override = true; in qusb2_phy_probe()
1097 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value", in qusb2_phy_probe()
1098 &value)) { in qusb2_phy_probe()
1099 or->hstx_trim.value = (u8)value; in qusb2_phy_probe()
1100 or->hstx_trim.override = true; in qusb2_phy_probe()
1103 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level", in qusb2_phy_probe()
1104 &value)) { in qusb2_phy_probe()
1105 or->preemphasis.value = (u8)value; in qusb2_phy_probe()
1106 or->preemphasis.override = true; in qusb2_phy_probe()
1109 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width", in qusb2_phy_probe()
1110 &value)) { in qusb2_phy_probe()
1111 or->preemphasis_width.value = (u8)value; in qusb2_phy_probe()
1112 or->preemphasis_width.override = true; in qusb2_phy_probe()
1115 if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value", in qusb2_phy_probe()
1116 &value)) { in qusb2_phy_probe()
1117 or->hsdisc_trim.value = (u8)value; in qusb2_phy_probe()
1118 or->hsdisc_trim.override = true; in qusb2_phy_probe()
1136 qphy->phy = generic_phy; in qusb2_phy_probe()
1143 dev_info(dev, "Registered Qcom-QUSB2 phy\n"); in qusb2_phy_probe()
1153 .name = "qcom-qusb2-phy",