Lines Matching +full:sc7180 +full:- +full:dp
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
24 #include <drm/bridge/aux-bridge.h>
26 #include <dt-bindings/phy/phy-qcom-qmp.h>
28 #include "phy-qcom-qmp-common.h"
30 #include "phy-qcom-qmp.h"
31 #include "phy-qcom-qmp-pcs-misc-v3.h"
32 #include "phy-qcom-qmp-pcs-usb-v4.h"
33 #include "phy-qcom-qmp-pcs-usb-v5.h"
34 #include "phy-qcom-qmp-pcs-usb-v6.h"
36 #include "phy-qcom-qmp-dp-com-v3.h"
38 #include "phy-qcom-qmp-dp-phy.h"
39 #include "phy-qcom-qmp-dp-phy-v3.h"
40 #include "phy-qcom-qmp-dp-phy-v4.h"
41 #include "phy-qcom-qmp-dp-phy-v5.h"
42 #include "phy-qcom-qmp-dp-phy-v6.h"
45 /* DP PHY soft reset */
47 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
56 #define DP_MODE BIT(1) /* enables DP mode */
64 /* set of registers with offsets different per-PHY */
1486 { .name = "vdda-phy", .enable_load = 21800 },
1487 { .name = "vdda-pll", .enable_load = 36000 },
1602 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1619 /* Init sequence for DP PHY block link rates */
1629 /* DP PHY swing and pre_emphasis tables */
1635 /* DP PHY callbacks */
2285 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_dp_serdes_init()
2286 void __iomem *serdes = qmp->dp_serdes; in qmp_combo_dp_serdes_init()
2287 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; in qmp_combo_dp_serdes_init()
2289 qmp_configure(qmp->dev, serdes, cfg->dp_serdes_tbl, in qmp_combo_dp_serdes_init()
2290 cfg->dp_serdes_tbl_num); in qmp_combo_dp_serdes_init()
2292 switch (dp_opts->link_rate) { in qmp_combo_dp_serdes_init()
2294 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_rbr, in qmp_combo_dp_serdes_init()
2295 cfg->serdes_tbl_rbr_num); in qmp_combo_dp_serdes_init()
2298 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr, in qmp_combo_dp_serdes_init()
2299 cfg->serdes_tbl_hbr_num); in qmp_combo_dp_serdes_init()
2302 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr2, in qmp_combo_dp_serdes_init()
2303 cfg->serdes_tbl_hbr2_num); in qmp_combo_dp_serdes_init()
2306 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr3, in qmp_combo_dp_serdes_init()
2307 cfg->serdes_tbl_hbr3_num); in qmp_combo_dp_serdes_init()
2311 return -EINVAL; in qmp_combo_dp_serdes_init()
2319 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_v3_dp_aux_init()
2323 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); in qmp_v3_dp_aux_init()
2328 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); in qmp_v3_dp_aux_init()
2330 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); in qmp_v3_dp_aux_init()
2336 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); in qmp_v3_dp_aux_init()
2342 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); in qmp_v3_dp_aux_init()
2344 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); in qmp_v3_dp_aux_init()
2345 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); in qmp_v3_dp_aux_init()
2346 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); in qmp_v3_dp_aux_init()
2347 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); in qmp_v3_dp_aux_init()
2348 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); in qmp_v3_dp_aux_init()
2349 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); in qmp_v3_dp_aux_init()
2350 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); in qmp_v3_dp_aux_init()
2351 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); in qmp_v3_dp_aux_init()
2352 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); in qmp_v3_dp_aux_init()
2353 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); in qmp_v3_dp_aux_init()
2354 qmp->dp_aux_cfg = 0; in qmp_v3_dp_aux_init()
2359 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); in qmp_v3_dp_aux_init()
2364 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; in qmp_combo_configure_dp_swing()
2365 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_configure_dp_swing()
2370 for (i = 0; i < dp_opts->lanes; i++) { in qmp_combo_configure_dp_swing()
2371 v_level = max(v_level, dp_opts->voltage[i]); in qmp_combo_configure_dp_swing()
2372 p_level = max(p_level, dp_opts->pre[i]); in qmp_combo_configure_dp_swing()
2375 if (dp_opts->link_rate <= 2700) { in qmp_combo_configure_dp_swing()
2376 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; in qmp_combo_configure_dp_swing()
2377 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; in qmp_combo_configure_dp_swing()
2379 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; in qmp_combo_configure_dp_swing()
2380 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; in qmp_combo_configure_dp_swing()
2385 return -EINVAL; in qmp_combo_configure_dp_swing()
2391 writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); in qmp_combo_configure_dp_swing()
2392 writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); in qmp_combo_configure_dp_swing()
2393 writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); in qmp_combo_configure_dp_swing()
2394 writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); in qmp_combo_configure_dp_swing()
2401 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; in qmp_v3_configure_dp_tx()
2407 if (dp_opts->lanes == 1) { in qmp_v3_configure_dp_tx()
2415 writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); in qmp_v3_configure_dp_tx()
2416 writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); in qmp_v3_configure_dp_tx()
2417 writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); in qmp_v3_configure_dp_tx()
2418 writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); in qmp_v3_configure_dp_tx()
2423 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); in qmp_combo_configure_dp_mode()
2424 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; in qmp_combo_configure_dp_mode()
2430 if (dp_opts->lanes == 4 || reverse) in qmp_combo_configure_dp_mode()
2432 if (dp_opts->lanes == 4 || !reverse) in qmp_combo_configure_dp_mode()
2435 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); in qmp_combo_configure_dp_mode()
2438 writel(0x4c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); in qmp_combo_configure_dp_mode()
2440 writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); in qmp_combo_configure_dp_mode()
2447 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; in qmp_combo_configure_dp_clocks()
2450 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_configure_dp_clocks()
2452 switch (dp_opts->link_rate) { in qmp_combo_configure_dp_clocks()
2471 return -EINVAL; in qmp_combo_configure_dp_clocks()
2473 writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]); in qmp_combo_configure_dp_clocks()
2475 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); in qmp_combo_configure_dp_clocks()
2476 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); in qmp_combo_configure_dp_clocks()
2483 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_v3_configure_dp_phy()
2489 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); in qmp_v3_configure_dp_phy()
2490 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); in qmp_v3_configure_dp_phy()
2496 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); in qmp_v3_configure_dp_phy()
2497 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v3_configure_dp_phy()
2498 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v3_configure_dp_phy()
2499 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v3_configure_dp_phy()
2500 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v3_configure_dp_phy()
2502 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); in qmp_v3_configure_dp_phy()
2504 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], in qmp_v3_configure_dp_phy()
2509 return -ETIMEDOUT; in qmp_v3_configure_dp_phy()
2511 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v3_configure_dp_phy()
2513 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], in qmp_v3_configure_dp_phy()
2518 return -ETIMEDOUT; in qmp_v3_configure_dp_phy()
2520 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v3_configure_dp_phy()
2522 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v3_configure_dp_phy()
2524 return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], in qmp_v3_configure_dp_phy()
2540 qmp->dp_aux_cfg++; in qmp_v3_calibrate_dp_phy()
2541 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); in qmp_v3_calibrate_dp_phy()
2542 val = cfg1_settings[qmp->dp_aux_cfg]; in qmp_v3_calibrate_dp_phy()
2544 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); in qmp_v3_calibrate_dp_phy()
2551 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_v4_dp_aux_init()
2555 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); in qmp_v4_dp_aux_init()
2558 writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); in qmp_v4_dp_aux_init()
2560 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); in qmp_v4_dp_aux_init()
2561 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); in qmp_v4_dp_aux_init()
2562 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); in qmp_v4_dp_aux_init()
2563 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); in qmp_v4_dp_aux_init()
2564 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); in qmp_v4_dp_aux_init()
2565 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); in qmp_v4_dp_aux_init()
2566 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); in qmp_v4_dp_aux_init()
2567 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); in qmp_v4_dp_aux_init()
2568 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); in qmp_v4_dp_aux_init()
2569 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); in qmp_v4_dp_aux_init()
2570 qmp->dp_aux_cfg = 0; in qmp_v4_dp_aux_init()
2575 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); in qmp_v4_dp_aux_init()
2580 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_v4_configure_dp_tx()
2583 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); in qmp_v4_configure_dp_tx()
2584 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); in qmp_v4_configure_dp_tx()
2586 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); in qmp_v4_configure_dp_tx()
2587 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); in qmp_v4_configure_dp_tx()
2594 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_v456_configure_dp_phy()
2598 writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1); in qmp_v456_configure_dp_phy()
2602 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); in qmp_v456_configure_dp_phy()
2603 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); in qmp_v456_configure_dp_phy()
2605 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); in qmp_v456_configure_dp_phy()
2606 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); in qmp_v456_configure_dp_phy()
2612 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v456_configure_dp_phy()
2613 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v456_configure_dp_phy()
2614 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v456_configure_dp_phy()
2615 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v456_configure_dp_phy()
2617 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); in qmp_v456_configure_dp_phy()
2619 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], in qmp_v456_configure_dp_phy()
2624 return -ETIMEDOUT; in qmp_v456_configure_dp_phy()
2626 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], in qmp_v456_configure_dp_phy()
2631 return -ETIMEDOUT; in qmp_v456_configure_dp_phy()
2633 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], in qmp_v456_configure_dp_phy()
2638 return -ETIMEDOUT; in qmp_v456_configure_dp_phy()
2640 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v456_configure_dp_phy()
2642 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], in qmp_v456_configure_dp_phy()
2647 return -ETIMEDOUT; in qmp_v456_configure_dp_phy()
2649 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], in qmp_v456_configure_dp_phy()
2654 return -ETIMEDOUT; in qmp_v456_configure_dp_phy()
2661 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_v4_configure_dp_phy()
2662 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); in qmp_v4_configure_dp_phy()
2663 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; in qmp_v4_configure_dp_phy()
2673 * At least for 7nm DP PHY this has to be done after enabling link in qmp_v4_configure_dp_phy()
2677 if (dp_opts->lanes == 1) { in qmp_v4_configure_dp_phy()
2682 } else if (dp_opts->lanes == 2) { in qmp_v4_configure_dp_phy()
2694 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); in qmp_v4_configure_dp_phy()
2695 writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); in qmp_v4_configure_dp_phy()
2696 writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); in qmp_v4_configure_dp_phy()
2697 writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); in qmp_v4_configure_dp_phy()
2699 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v4_configure_dp_phy()
2701 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v4_configure_dp_phy()
2703 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], in qmp_v4_configure_dp_phy()
2708 return -ETIMEDOUT; in qmp_v4_configure_dp_phy()
2710 writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]); in qmp_v4_configure_dp_phy()
2711 writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]); in qmp_v4_configure_dp_phy()
2713 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); in qmp_v4_configure_dp_phy()
2714 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); in qmp_v4_configure_dp_phy()
2716 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); in qmp_v4_configure_dp_phy()
2717 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); in qmp_v4_configure_dp_phy()
2731 qmp->dp_aux_cfg++; in qmp_v4_calibrate_dp_phy()
2732 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); in qmp_v4_calibrate_dp_phy()
2733 val = cfg1_settings[qmp->dp_aux_cfg]; in qmp_v4_calibrate_dp_phy()
2735 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); in qmp_v4_calibrate_dp_phy()
2742 const struct phy_configure_opts_dp *dp_opts = &opts->dp; in qmp_combo_dp_configure()
2744 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_dp_configure()
2746 mutex_lock(&qmp->phy_mutex); in qmp_combo_dp_configure()
2748 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); in qmp_combo_dp_configure()
2749 if (qmp->dp_opts.set_voltages) { in qmp_combo_dp_configure()
2750 cfg->configure_dp_tx(qmp); in qmp_combo_dp_configure()
2751 qmp->dp_opts.set_voltages = 0; in qmp_combo_dp_configure()
2754 mutex_unlock(&qmp->phy_mutex); in qmp_combo_dp_configure()
2762 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_dp_calibrate()
2765 mutex_lock(&qmp->phy_mutex); in qmp_combo_dp_calibrate()
2767 if (cfg->calibrate_dp_phy) in qmp_combo_dp_calibrate()
2768 ret = cfg->calibrate_dp_phy(qmp); in qmp_combo_dp_calibrate()
2770 mutex_unlock(&qmp->phy_mutex); in qmp_combo_dp_calibrate()
2777 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_com_init()
2778 void __iomem *com = qmp->com; in qmp_combo_com_init()
2782 if (!force && qmp->init_count++) in qmp_combo_com_init()
2785 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); in qmp_combo_com_init()
2787 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); in qmp_combo_com_init()
2791 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_combo_com_init()
2793 dev_err(qmp->dev, "reset assert failed\n"); in qmp_combo_com_init()
2797 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); in qmp_combo_com_init()
2799 dev_err(qmp->dev, "reset deassert failed\n"); in qmp_combo_com_init()
2803 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); in qmp_combo_com_init()
2816 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) in qmp_combo_com_init()
2821 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ in qmp_combo_com_init()
2829 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_combo_com_init()
2835 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_combo_com_init()
2837 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_combo_com_init()
2839 qmp->init_count--; in qmp_combo_com_init()
2846 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_com_exit()
2848 if (!force && --qmp->init_count) in qmp_combo_com_exit()
2851 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_combo_com_exit()
2853 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); in qmp_combo_com_exit()
2855 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_combo_com_exit()
2863 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_dp_init()
2866 mutex_lock(&qmp->phy_mutex); in qmp_combo_dp_init()
2872 cfg->dp_aux_init(qmp); in qmp_combo_dp_init()
2874 qmp->dp_init_count++; in qmp_combo_dp_init()
2877 mutex_unlock(&qmp->phy_mutex); in qmp_combo_dp_init()
2885 mutex_lock(&qmp->phy_mutex); in qmp_combo_dp_exit()
2889 qmp->dp_init_count--; in qmp_combo_dp_exit()
2891 mutex_unlock(&qmp->phy_mutex); in qmp_combo_dp_exit()
2899 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_dp_power_on()
2900 void __iomem *tx = qmp->dp_tx; in qmp_combo_dp_power_on()
2901 void __iomem *tx2 = qmp->dp_tx2; in qmp_combo_dp_power_on()
2903 mutex_lock(&qmp->phy_mutex); in qmp_combo_dp_power_on()
2907 qmp_configure_lane(qmp->dev, tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); in qmp_combo_dp_power_on()
2908 qmp_configure_lane(qmp->dev, tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); in qmp_combo_dp_power_on()
2910 /* Configure special DP tx tunings */ in qmp_combo_dp_power_on()
2911 cfg->configure_dp_tx(qmp); in qmp_combo_dp_power_on()
2914 cfg->configure_dp_phy(qmp); in qmp_combo_dp_power_on()
2916 mutex_unlock(&qmp->phy_mutex); in qmp_combo_dp_power_on()
2925 mutex_lock(&qmp->phy_mutex); in qmp_combo_dp_power_off()
2927 /* Assert DP PHY power down */ in qmp_combo_dp_power_off()
2928 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); in qmp_combo_dp_power_off()
2930 mutex_unlock(&qmp->phy_mutex); in qmp_combo_dp_power_off()
2938 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_usb_power_on()
2939 void __iomem *serdes = qmp->serdes; in qmp_combo_usb_power_on()
2940 void __iomem *tx = qmp->tx; in qmp_combo_usb_power_on()
2941 void __iomem *rx = qmp->rx; in qmp_combo_usb_power_on()
2942 void __iomem *tx2 = qmp->tx2; in qmp_combo_usb_power_on()
2943 void __iomem *rx2 = qmp->rx2; in qmp_combo_usb_power_on()
2944 void __iomem *pcs = qmp->pcs; in qmp_combo_usb_power_on()
2945 void __iomem *pcs_usb = qmp->pcs_usb; in qmp_combo_usb_power_on()
2950 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); in qmp_combo_usb_power_on()
2952 ret = clk_prepare_enable(qmp->pipe_clk); in qmp_combo_usb_power_on()
2954 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); in qmp_combo_usb_power_on()
2959 qmp_configure_lane(qmp->dev, tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); in qmp_combo_usb_power_on()
2960 qmp_configure_lane(qmp->dev, tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); in qmp_combo_usb_power_on()
2962 qmp_configure_lane(qmp->dev, rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); in qmp_combo_usb_power_on()
2963 qmp_configure_lane(qmp->dev, rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); in qmp_combo_usb_power_on()
2965 qmp_configure(qmp->dev, pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); in qmp_combo_usb_power_on()
2968 qmp_configure(qmp->dev, pcs_usb, cfg->pcs_usb_tbl, in qmp_combo_usb_power_on()
2969 cfg->pcs_usb_tbl_num); in qmp_combo_usb_power_on()
2971 if (cfg->has_pwrdn_delay) in qmp_combo_usb_power_on()
2975 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_combo_usb_power_on()
2977 /* start SerDes and Phy-Coding-Sublayer */ in qmp_combo_usb_power_on()
2978 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); in qmp_combo_usb_power_on()
2980 status = pcs + cfg->regs[QPHY_PCS_STATUS]; in qmp_combo_usb_power_on()
2984 dev_err(qmp->dev, "phy initialization timed-out\n"); in qmp_combo_usb_power_on()
2991 clk_disable_unprepare(qmp->pipe_clk); in qmp_combo_usb_power_on()
2999 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_usb_power_off()
3001 clk_disable_unprepare(qmp->pipe_clk); in qmp_combo_usb_power_off()
3004 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_combo_usb_power_off()
3006 /* stop SerDes and Phy-Coding-Sublayer */ in qmp_combo_usb_power_off()
3007 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], in qmp_combo_usb_power_off()
3011 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_combo_usb_power_off()
3022 mutex_lock(&qmp->phy_mutex); in qmp_combo_usb_init()
3033 qmp->usb_init_count++; in qmp_combo_usb_init()
3036 mutex_unlock(&qmp->phy_mutex); in qmp_combo_usb_init()
3045 mutex_lock(&qmp->phy_mutex); in qmp_combo_usb_exit()
3054 qmp->usb_init_count--; in qmp_combo_usb_exit()
3057 mutex_unlock(&qmp->phy_mutex); in qmp_combo_usb_exit()
3065 qmp->mode = mode; in qmp_combo_usb_set_mode()
3089 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_enable_autonomous_mode()
3090 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; in qmp_combo_enable_autonomous_mode()
3091 void __iomem *pcs_misc = qmp->pcs_misc; in qmp_combo_enable_autonomous_mode()
3094 if (qmp->mode == PHY_MODE_USB_HOST_SS || in qmp_combo_enable_autonomous_mode()
3095 qmp->mode == PHY_MODE_USB_DEVICE_SS) in qmp_combo_enable_autonomous_mode()
3101 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); in qmp_combo_enable_autonomous_mode()
3103 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); in qmp_combo_enable_autonomous_mode()
3105 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], in qmp_combo_enable_autonomous_mode()
3109 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); in qmp_combo_enable_autonomous_mode()
3118 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_disable_autonomous_mode()
3119 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; in qmp_combo_disable_autonomous_mode()
3120 void __iomem *pcs_misc = qmp->pcs_misc; in qmp_combo_disable_autonomous_mode()
3126 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], in qmp_combo_disable_autonomous_mode()
3129 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); in qmp_combo_disable_autonomous_mode()
3131 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); in qmp_combo_disable_autonomous_mode()
3138 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); in qmp_combo_runtime_suspend()
3140 if (!qmp->init_count) { in qmp_combo_runtime_suspend()
3147 clk_disable_unprepare(qmp->pipe_clk); in qmp_combo_runtime_suspend()
3148 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); in qmp_combo_runtime_suspend()
3158 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); in qmp_combo_runtime_resume()
3160 if (!qmp->init_count) { in qmp_combo_runtime_resume()
3165 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); in qmp_combo_runtime_resume()
3169 ret = clk_prepare_enable(qmp->pipe_clk); in qmp_combo_runtime_resume()
3172 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); in qmp_combo_runtime_resume()
3188 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_vreg_init()
3189 struct device *dev = qmp->dev; in qmp_combo_vreg_init()
3190 int num = cfg->num_vregs; in qmp_combo_vreg_init()
3193 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); in qmp_combo_vreg_init()
3194 if (!qmp->vregs) in qmp_combo_vreg_init()
3195 return -ENOMEM; in qmp_combo_vreg_init()
3198 qmp->vregs[i].supply = cfg->vreg_list[i].name; in qmp_combo_vreg_init()
3200 ret = devm_regulator_bulk_get(dev, num, qmp->vregs); in qmp_combo_vreg_init()
3207 ret = regulator_set_load(qmp->vregs[i].consumer, in qmp_combo_vreg_init()
3208 cfg->vreg_list[i].enable_load); in qmp_combo_vreg_init()
3211 qmp->vregs[i].supply); in qmp_combo_vreg_init()
3221 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_reset_init()
3222 struct device *dev = qmp->dev; in qmp_combo_reset_init()
3226 qmp->resets = devm_kcalloc(dev, cfg->num_resets, in qmp_combo_reset_init()
3227 sizeof(*qmp->resets), GFP_KERNEL); in qmp_combo_reset_init()
3228 if (!qmp->resets) in qmp_combo_reset_init()
3229 return -ENOMEM; in qmp_combo_reset_init()
3231 for (i = 0; i < cfg->num_resets; i++) in qmp_combo_reset_init()
3232 qmp->resets[i].id = cfg->reset_list[i]; in qmp_combo_reset_init()
3234 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); in qmp_combo_reset_init()
3243 struct device *dev = qmp->dev; in qmp_combo_clk_init()
3247 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); in qmp_combo_clk_init()
3248 if (!qmp->clks) in qmp_combo_clk_init()
3249 return -ENOMEM; in qmp_combo_clk_init()
3252 qmp->clks[i].id = qmp_combo_phy_clk_l[i]; in qmp_combo_clk_init()
3254 qmp->num_clks = num; in qmp_combo_clk_init()
3256 return devm_clk_bulk_get_optional(dev, num, qmp->clks); in qmp_combo_clk_init()
3274 * +---------------+
3275 * | PHY block |<<---------------------------------------+
3277 * | +-------+ | +-----+ |
3278 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
3279 * clk | +-------+ | +-----+
3280 * +---------------+
3284 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; in phy_pipe_clk_register()
3288 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); in phy_pipe_clk_register()
3293 fixed->fixed_rate = 125000000; in phy_pipe_clk_register()
3294 fixed->hw.init = &init; in phy_pipe_clk_register()
3296 return devm_clk_hw_register(qmp->dev, &fixed->hw); in phy_pipe_clk_register()
3302 * +------------------------------+
3305 * | +-------------------+ |
3306 * | | (DP PLL/VCO) | |
3307 * | +---------+---------+ |
3309 * | +----------+-----------+ |
3311 * | +----------+-----------+ |
3312 * +------------------------------+
3314 * +---------<---------v------------>----------+
3316 * +--------v----------------+ |
3319 * +--------+----------------+ |
3328 * +--------<------------+-----------------+---<---+
3330 * +----v---------+ +--------v-----+ +--------v------+
3335 * +-------+------+ +-----+--------+ +--------+------+
3337 * v---->----------v-------------<------v
3339 * +----------+-----------------+
3341 * +---------+------------------+
3345 * for DP pixel clock
3350 switch (req->rate) { in qmp_dp_pixel_clk_determine_rate()
3356 return -EINVAL; in qmp_dp_pixel_clk_determine_rate()
3366 dp_opts = &qmp->dp_opts; in qmp_dp_pixel_clk_recalc_rate()
3368 switch (dp_opts->link_rate) { in qmp_dp_pixel_clk_recalc_rate()
3389 switch (req->rate) { in qmp_dp_link_clk_determine_rate()
3396 return -EINVAL; in qmp_dp_link_clk_determine_rate()
3406 dp_opts = &qmp->dp_opts; in qmp_dp_link_clk_recalc_rate()
3408 switch (dp_opts->link_rate) { in qmp_dp_link_clk_recalc_rate()
3413 return dp_opts->link_rate * 100000; in qmp_dp_link_clk_recalc_rate()
3427 unsigned int idx = clkspec->args[0]; in qmp_dp_clks_hw_get()
3431 return ERR_PTR(-EINVAL); in qmp_dp_clks_hw_get()
3435 return &qmp->dp_link_hw; in qmp_dp_clks_hw_get()
3437 return &qmp->dp_pixel_hw; in qmp_dp_clks_hw_get()
3446 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); in phy_dp_clks_register()
3449 qmp->dp_link_hw.init = &init; in phy_dp_clks_register()
3450 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); in phy_dp_clks_register()
3454 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); in phy_dp_clks_register()
3457 qmp->dp_pixel_hw.init = &init; in phy_dp_clks_register()
3458 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); in phy_dp_clks_register()
3469 switch (clkspec->args[0]) { in qmp_combo_clk_hw_get()
3471 return &qmp->pipe_clk_fixed.hw; in qmp_combo_clk_hw_get()
3473 return &qmp->dp_link_hw; in qmp_combo_clk_hw_get()
3475 return &qmp->dp_pixel_hw; in qmp_combo_clk_hw_get()
3478 return ERR_PTR(-EINVAL); in qmp_combo_clk_hw_get()
3497 if (usb_np == qmp->dev->of_node) in qmp_combo_register_clocks()
3498 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp); in qmp_combo_register_clocks()
3504 &qmp->pipe_clk_fixed.hw); in qmp_combo_register_clocks()
3512 ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np); in qmp_combo_register_clocks()
3520 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np); in qmp_combo_register_clocks()
3528 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_typec_switch_set()
3530 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE) in qmp_combo_typec_switch_set()
3533 mutex_lock(&qmp->phy_mutex); in qmp_combo_typec_switch_set()
3534 qmp->orientation = orientation; in qmp_combo_typec_switch_set()
3536 if (qmp->init_count) { in qmp_combo_typec_switch_set()
3537 if (qmp->usb_init_count) in qmp_combo_typec_switch_set()
3538 qmp_combo_usb_power_off(qmp->usb_phy); in qmp_combo_typec_switch_set()
3542 if (qmp->usb_init_count) in qmp_combo_typec_switch_set()
3543 qmp_combo_usb_power_on(qmp->usb_phy); in qmp_combo_typec_switch_set()
3544 if (qmp->dp_init_count) in qmp_combo_typec_switch_set()
3545 cfg->dp_aux_init(qmp); in qmp_combo_typec_switch_set()
3547 mutex_unlock(&qmp->phy_mutex); in qmp_combo_typec_switch_set()
3556 typec_switch_unregister(qmp->sw); in qmp_combo_typec_unregister()
3562 struct device *dev = qmp->dev; in qmp_combo_typec_switch_register()
3565 sw_desc.fwnode = dev->fwnode; in qmp_combo_typec_switch_register()
3567 qmp->sw = typec_switch_register(dev, &sw_desc); in qmp_combo_typec_switch_register()
3568 if (IS_ERR(qmp->sw)) { in qmp_combo_typec_switch_register()
3569 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw); in qmp_combo_typec_switch_register()
3570 return PTR_ERR(qmp->sw); in qmp_combo_typec_switch_register()
3584 struct device *dev = qmp->dev; in qmp_combo_parse_dt_legacy_dp()
3587 * Get memory resources from the DP child node: in qmp_combo_parse_dt_legacy_dp()
3588 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; in qmp_combo_parse_dt_legacy_dp()
3589 * tx2 -> 3; rx2 -> 4 in qmp_combo_parse_dt_legacy_dp()
3591 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP in qmp_combo_parse_dt_legacy_dp()
3594 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL); in qmp_combo_parse_dt_legacy_dp()
3595 if (IS_ERR(qmp->dp_tx)) in qmp_combo_parse_dt_legacy_dp()
3596 return PTR_ERR(qmp->dp_tx); in qmp_combo_parse_dt_legacy_dp()
3598 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL); in qmp_combo_parse_dt_legacy_dp()
3599 if (IS_ERR(qmp->dp_dp_phy)) in qmp_combo_parse_dt_legacy_dp()
3600 return PTR_ERR(qmp->dp_dp_phy); in qmp_combo_parse_dt_legacy_dp()
3602 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL); in qmp_combo_parse_dt_legacy_dp()
3603 if (IS_ERR(qmp->dp_tx2)) in qmp_combo_parse_dt_legacy_dp()
3604 return PTR_ERR(qmp->dp_tx2); in qmp_combo_parse_dt_legacy_dp()
3611 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_parse_dt_legacy_usb()
3612 struct device *dev = qmp->dev; in qmp_combo_parse_dt_legacy_usb()
3616 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; in qmp_combo_parse_dt_legacy_usb()
3617 * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5 in qmp_combo_parse_dt_legacy_usb()
3619 qmp->tx = devm_of_iomap(dev, np, 0, NULL); in qmp_combo_parse_dt_legacy_usb()
3620 if (IS_ERR(qmp->tx)) in qmp_combo_parse_dt_legacy_usb()
3621 return PTR_ERR(qmp->tx); in qmp_combo_parse_dt_legacy_usb()
3623 qmp->rx = devm_of_iomap(dev, np, 1, NULL); in qmp_combo_parse_dt_legacy_usb()
3624 if (IS_ERR(qmp->rx)) in qmp_combo_parse_dt_legacy_usb()
3625 return PTR_ERR(qmp->rx); in qmp_combo_parse_dt_legacy_usb()
3627 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); in qmp_combo_parse_dt_legacy_usb()
3628 if (IS_ERR(qmp->pcs)) in qmp_combo_parse_dt_legacy_usb()
3629 return PTR_ERR(qmp->pcs); in qmp_combo_parse_dt_legacy_usb()
3631 if (cfg->pcs_usb_offset) in qmp_combo_parse_dt_legacy_usb()
3632 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; in qmp_combo_parse_dt_legacy_usb()
3634 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); in qmp_combo_parse_dt_legacy_usb()
3635 if (IS_ERR(qmp->tx2)) in qmp_combo_parse_dt_legacy_usb()
3636 return PTR_ERR(qmp->tx2); in qmp_combo_parse_dt_legacy_usb()
3638 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); in qmp_combo_parse_dt_legacy_usb()
3639 if (IS_ERR(qmp->rx2)) in qmp_combo_parse_dt_legacy_usb()
3640 return PTR_ERR(qmp->rx2); in qmp_combo_parse_dt_legacy_usb()
3642 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); in qmp_combo_parse_dt_legacy_usb()
3643 if (IS_ERR(qmp->pcs_misc)) { in qmp_combo_parse_dt_legacy_usb()
3644 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); in qmp_combo_parse_dt_legacy_usb()
3645 qmp->pcs_misc = NULL; in qmp_combo_parse_dt_legacy_usb()
3648 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); in qmp_combo_parse_dt_legacy_usb()
3649 if (IS_ERR(qmp->pipe_clk)) { in qmp_combo_parse_dt_legacy_usb()
3650 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), in qmp_combo_parse_dt_legacy_usb()
3660 struct platform_device *pdev = to_platform_device(qmp->dev); in qmp_combo_parse_dt_legacy()
3663 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); in qmp_combo_parse_dt_legacy()
3664 if (IS_ERR(qmp->serdes)) in qmp_combo_parse_dt_legacy()
3665 return PTR_ERR(qmp->serdes); in qmp_combo_parse_dt_legacy()
3667 qmp->com = devm_platform_ioremap_resource(pdev, 1); in qmp_combo_parse_dt_legacy()
3668 if (IS_ERR(qmp->com)) in qmp_combo_parse_dt_legacy()
3669 return PTR_ERR(qmp->com); in qmp_combo_parse_dt_legacy()
3671 qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2); in qmp_combo_parse_dt_legacy()
3672 if (IS_ERR(qmp->dp_serdes)) in qmp_combo_parse_dt_legacy()
3673 return PTR_ERR(qmp->dp_serdes); in qmp_combo_parse_dt_legacy()
3683 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks); in qmp_combo_parse_dt_legacy()
3687 qmp->num_clks = ret; in qmp_combo_parse_dt_legacy()
3694 struct platform_device *pdev = to_platform_device(qmp->dev); in qmp_combo_parse_dt()
3695 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_parse_dt()
3696 const struct qmp_combo_offsets *offs = cfg->offsets; in qmp_combo_parse_dt()
3697 struct device *dev = qmp->dev; in qmp_combo_parse_dt()
3702 return -EINVAL; in qmp_combo_parse_dt()
3708 qmp->com = base + offs->com; in qmp_combo_parse_dt()
3709 qmp->tx = base + offs->txa; in qmp_combo_parse_dt()
3710 qmp->rx = base + offs->rxa; in qmp_combo_parse_dt()
3711 qmp->tx2 = base + offs->txb; in qmp_combo_parse_dt()
3712 qmp->rx2 = base + offs->rxb; in qmp_combo_parse_dt()
3714 qmp->serdes = base + offs->usb3_serdes; in qmp_combo_parse_dt()
3715 qmp->pcs_misc = base + offs->usb3_pcs_misc; in qmp_combo_parse_dt()
3716 qmp->pcs = base + offs->usb3_pcs; in qmp_combo_parse_dt()
3717 qmp->pcs_usb = base + offs->usb3_pcs_usb; in qmp_combo_parse_dt()
3719 qmp->dp_serdes = base + offs->dp_serdes; in qmp_combo_parse_dt()
3720 if (offs->dp_txa) { in qmp_combo_parse_dt()
3721 qmp->dp_tx = base + offs->dp_txa; in qmp_combo_parse_dt()
3722 qmp->dp_tx2 = base + offs->dp_txb; in qmp_combo_parse_dt()
3724 qmp->dp_tx = base + offs->txa; in qmp_combo_parse_dt()
3725 qmp->dp_tx2 = base + offs->txb; in qmp_combo_parse_dt()
3727 qmp->dp_dp_phy = base + offs->dp_dp_phy; in qmp_combo_parse_dt()
3733 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe"); in qmp_combo_parse_dt()
3734 if (IS_ERR(qmp->pipe_clk)) { in qmp_combo_parse_dt()
3735 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), in qmp_combo_parse_dt()
3746 if (args->args_count == 0) in qmp_combo_phy_xlate()
3747 return ERR_PTR(-EINVAL); in qmp_combo_phy_xlate()
3749 switch (args->args[0]) { in qmp_combo_phy_xlate()
3751 return qmp->usb_phy; in qmp_combo_phy_xlate()
3753 return qmp->dp_phy; in qmp_combo_phy_xlate()
3756 return ERR_PTR(-EINVAL); in qmp_combo_phy_xlate()
3762 struct device *dev = &pdev->dev; in qmp_combo_probe()
3769 return -ENOMEM; in qmp_combo_probe()
3771 qmp->dev = dev; in qmp_combo_probe()
3774 qmp->orientation = TYPEC_ORIENTATION_NORMAL; in qmp_combo_probe()
3776 qmp->cfg = of_device_get_match_data(dev); in qmp_combo_probe()
3777 if (!qmp->cfg) in qmp_combo_probe()
3778 return -EINVAL; in qmp_combo_probe()
3780 mutex_init(&qmp->phy_mutex); in qmp_combo_probe()
3791 usb_np = of_get_child_by_name(dev->of_node, "usb3-phy"); in qmp_combo_probe()
3793 dp_np = of_get_child_by_name(dev->of_node, "dp-phy"); in qmp_combo_probe()
3796 return -EINVAL; in qmp_combo_probe()
3801 usb_np = of_node_get(dev->of_node); in qmp_combo_probe()
3802 dp_np = of_node_get(dev->of_node); in qmp_combo_probe()
3831 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops); in qmp_combo_probe()
3832 if (IS_ERR(qmp->usb_phy)) { in qmp_combo_probe()
3833 ret = PTR_ERR(qmp->usb_phy); in qmp_combo_probe()
3838 phy_set_drvdata(qmp->usb_phy, qmp); in qmp_combo_probe()
3840 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); in qmp_combo_probe()
3841 if (IS_ERR(qmp->dp_phy)) { in qmp_combo_probe()
3842 ret = PTR_ERR(qmp->dp_phy); in qmp_combo_probe()
3843 dev_err(dev, "failed to create DP PHY: %d\n", ret); in qmp_combo_probe()
3847 phy_set_drvdata(qmp->dp_phy, qmp); in qmp_combo_probe()
3849 if (usb_np == dev->of_node) in qmp_combo_probe()
3867 .compatible = "qcom,sar2130p-qmp-usb3-dp-phy",
3871 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
3875 .compatible = "qcom,sc7280-qmp-usb3-dp-phy",
3879 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
3883 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy",
3887 .compatible = "qcom,sdm845-qmp-usb3-dp-phy",
3891 .compatible = "qcom,sm6350-qmp-usb3-dp-phy",
3895 .compatible = "qcom,sm8150-qmp-usb3-dp-phy",
3899 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
3903 .compatible = "qcom,sm8350-qmp-usb3-dp-phy",
3907 .compatible = "qcom,sm8450-qmp-usb3-dp-phy",
3911 .compatible = "qcom,sm8550-qmp-usb3-dp-phy",
3915 .compatible = "qcom,sm8650-qmp-usb3-dp-phy",
3919 .compatible = "qcom,x1e80100-qmp-usb3-dp-phy",
3929 .name = "qcom-qmp-combo-phy",
3938 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver");