98 	void __iomem *tx1;  member
308 	writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG);  in qcom_edp_set_voltages()
309 	writel(swing, edp->tx1 + TXn_TX_DRV_LVL);  in qcom_edp_set_voltages()
310 	writel(emph, edp->tx1 + TXn_TX_EMP_POST1_LVL);  in qcom_edp_set_voltages()
757 	writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG);  in qcom_edp_phy_power_on()
759 	writel(0x00, edp->tx1 + TXn_LANE_MODE_1);  in qcom_edp_phy_power_on()
783 	writel(0x03, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN);  in qcom_edp_phy_power_on()
784 	writel(0x0f, edp->tx1 + TXn_CLKBUF_ENABLE);  in qcom_edp_phy_power_on()
785 	writel(0x03, edp->tx1 + TXn_RESET_TSYNC_EN);  in qcom_edp_phy_power_on()
786 	writel(0x01, edp->tx1 + TXn_TRAN_DRVR_EMP_EN);  in qcom_edp_phy_power_on()
787 	writel(0x04, edp->tx1 + TXn_TX_BAND);  in qcom_edp_phy_power_on()
806 	writel(0x1f, edp->tx1 + TXn_HIGHZ_DRVR_EN);  in qcom_edp_phy_power_on()
807 	writel(0x04, edp->tx1 + TXn_HIGHZ_DRVR_EN);  in qcom_edp_phy_power_on()
808 	writel(0x00, edp->tx1 + TXn_TX_POL_INV);  in qcom_edp_phy_power_on()
810 	writel(0x10, edp->tx1 + TXn_TX_DRV_LVL_OFFSET);  in qcom_edp_phy_power_on()
813 	writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX0);  in qcom_edp_phy_power_on()
814 	writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX1);  in qcom_edp_phy_power_on()
817 	writel(0x10, edp->tx1 + TXn_TX_EMP_POST1_LVL);  in qcom_edp_phy_power_on()
819 	writel(0x1f, edp->tx1 + TXn_TX_DRV_LVL);  in qcom_edp_phy_power_on()
843 	writel(drvr1_en, edp->tx1 + TXn_HIGHZ_DRVR_EN);  in qcom_edp_phy_power_on()
844 	writel(bias1_en, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN);  in qcom_edp_phy_power_on()
1087 	edp->tx1 = devm_platform_ioremap_resource(pdev, 2);  in qcom_edp_phy_probe()
1088 	if (IS_ERR(edp->tx1))  in qcom_edp_phy_probe()
1089 		return PTR_ERR(edp->tx1);  in qcom_edp_phy_probe()