Lines Matching +full:0 +full:x08ec
11 #define REG_CSR_2L_CMN 0x0000
12 #define CSR_2L_PXP_CMN_LANE_EN BIT(0)
15 #define REG_CSR_2L_JCPLL_IB_EXT 0x0004
20 #define REG_CSR_2L_JCPLL_LPF_BR 0x0008
21 #define CSR_2L_PXP_JCPLL_LPF_BR GENMASK(4, 0)
26 #define REG_CSR_2L_JCPLL_LPF_BWC 0x000c
27 #define CSR_2L_PXP_JCPLL_LPF_BWC GENMASK(4, 0)
31 #define REG_CSR_2L_JCPLL_KBAND_KFC 0x0010
32 #define CSR_2L_PXP_JCPLL_KBAND_KFC GENMASK(1, 0)
37 #define REG_CSR_2L_JCPLL_MMD_PREDIV_MODE 0x0014
38 #define CSR_2L_PXP_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0)
42 #define CSR_2L_PXP_JCPLL_MONCK 0x0018
45 #define REG_CSR_2L_JCPLL_RST_DLY 0x001c
46 #define CSR_2L_PXP_JCPLL_RST_DLY GENMASK(2, 0)
51 #define REG_CSR_2L_JCPLL_SDM_IFM 0x0020
52 #define CSR_2L_PXP_JCPLL_SDM_IFM BIT(0)
54 #define REG_CSR_2L_JCPLL_SDM_HREN 0x0024
55 #define CSR_2L_PXP_JCPLL_SDM_HREN BIT(0)
60 #define REG_CSR_2L_JCPLL_TCL_CMP 0x0028
64 #define REG_CSR_2L_JCPLL_VCODIV 0x002c
69 #define REG_CSR_2L_JCPLL_VCO_TCLVAR 0x0030
70 #define CSR_2L_PXP_JCPLL_VCO_TCLVAR GENMASK(2, 0)
72 #define REG_CSR_2L_JCPLL_SSC 0x0038
73 #define CSR_2L_PXP_JCPLL_SSC_EN BIT(0)
77 #define REG_CSR_2L_JCPLL_SSC_DELTA1 0x003c
78 #define CSR_2L_PXP_JCPLL_SSC_DELTA1 GENMASK(15, 0)
81 #define REG_CSR_2L_JCPLL_SSC_PERIOD 0x0040
82 #define CSR_2L_PXP_JCPLL_SSC_PERIOD GENMASK(15, 0)
84 #define REG_CSR_2L_JCPLL_TCL_VTP_EN 0x004c
87 #define REG_CSR_2L_JCPLL_TCL_KBAND_VREF 0x0050
88 #define CSR_2L_PXP_JCPLL_TCL_KBAND_VREF GENMASK(4, 0)
91 #define REG_CSR_2L_750M_SYS_CK 0x0054
95 #define REG_CSR_2L_TXPLL_CHP_IOFST 0x0058
96 #define CSR_2L_PXP_TXPLL_CHP_IOFST GENMASK(5, 0)
101 #define REG_CSR_2L_TXPLL_LPF_BWR 0x005c
102 #define CSR_2L_PXP_TXPLL_LPF_BWR GENMASK(4, 0)
106 #define REG_CSR_2L_TXPLL_KBAND_DIV 0x0060
107 #define CSR_2L_PXP_TXPLL_KBAND_DIV GENMASK(2, 0)
112 #define REG_CSR_2L_TXPLL_POSTDIV 0x0064
113 #define CSR_2L_PXP_TXPLL_POSTDIV_EN BIT(0)
117 #define REG_CSR_2L_TXPLL_PHY_CK2 0x0068
120 #define REG_CSR_2L_TXPLL_REFIN_DIV 0x006c
121 #define CSR_2L_PXP_TXPLL_REFIN_DIV GENMASK(1, 0)
125 #define REG_CSR_2L_TXPLL_SDM_DI_LS 0x0070
126 #define CSR_2L_PXP_TXPLL_SDM_DI_LS GENMASK(1, 0)
130 #define REG_CSR_2L_TXPLL_SDM_OUT 0x0074
134 #define REG_CSR_2L_TXPLL_TCL_AMP_VREF 0x0078
135 #define CSR_2L_PXP_TXPLL_TCL_AMP_VREF GENMASK(4, 0)
138 #define REG_CSR_2L_TXPLL_TCL_LPF_BW 0x007c
139 #define CSR_2L_PXP_TXPLL_TCL_LPF_BW GENMASK(2, 0)
143 #define REG_CSR_2L_TXPLL_VCO_SCAPWR 0x0080
144 #define CSR_2L_PXP_TXPLL_VCO_SCAPWR GENMASK(2, 0)
146 #define REG_CSR_2L_TXPLL_SSC 0x0084
147 #define CSR_2L_PXP_TXPLL_SSC_EN BIT(0)
150 #define REG_CSR_2L_TXPLL_SSC_DELTA1 0x0088
151 #define CSR_2L_PXP_TXPLL_SSC_DELTA1 GENMASK(15, 0)
154 #define REG_CSR_2L_TXPLL_SSC_PERIOD 0x008c
155 #define CSR_2L_PXP_txpll_SSC_PERIOD GENMASK(15, 0)
157 #define REG_CSR_2L_TXPLL_VTP 0x0090
158 #define CSR_2L_PXP_TXPLL_VTP_EN BIT(0)
160 #define REG_CSR_2L_TXPLL_TCL_VTP 0x0098
163 #define REG_CSR_2L_TXPLL_TCL_KBAND_VREF 0x009c
164 #define CSR_2L_PXP_TXPLL_TCL_KBAND_VREF GENMASK(4, 0)
167 #define REG_CSR_2L_TXPLL_POSTDIV_D256 0x00a0
172 #define REG_CSR_2L_CLKTX0_FORCE_OUT1 0x00a4
177 #define REG_CSR_2L_CLKTX1_OFFSET 0x00a8
178 #define CSR_2L_PXP_CLKTX1_OFFSET GENMASK(1, 0)
182 #define REG_CSR_2L_CLKTX1_IMP_SEL 0x00ac
183 #define CSR_2L_PXP_CLKTX1_IMP_SEL GENMASK(4, 0)
185 #define REG_CSR_2L_PLL_CMN_RESERVE0 0x00b0
186 #define CSR_2L_PXP_PLL_RESERVE_MASK GENMASK(15, 0)
188 #define REG_CSR_2L_TX0_CKLDO 0x00cc
189 #define CSR_2L_PXP_TX0_CKLDO_EN BIT(0)
192 #define REG_CSR_2L_TX1_CKLDO 0x00e8
193 #define CSR_2L_PXP_TX1_CKLDO_EN BIT(0)
196 #define REG_CSR_2L_TX1_MULTLANE 0x00ec
197 #define CSR_2L_PXP_TX1_MULTLANE_EN BIT(0)
199 #define REG_CSR_2L_RX0_REV0 0x00fc
204 #define REG_CSR_2L_RX0_PHYCK_DIV 0x0100
209 #define REG_CSR_2L_CDR0_PD_PICAL_CKD8_INV 0x0104
212 #define REG_CSR_2L_CDR0_LPF_RATIO 0x0110
215 #define REG_CSR_2L_CDR0_PR_INJ_MODE 0x011c
218 #define REG_CSR_2L_CDR0_PR_BETA_DAC 0x0120
222 #define REG_CSR_2L_CDR0_PR_VREG_IBAND 0x0124
223 #define CSR_2L_PXP_CDR0_PR_VREG_IBAND GENMASK(2, 0)
226 #define REG_CSR_2L_CDR0_PR_CKREF_DIV 0x0128
227 #define CSR_2L_PXP_CDR0_PR_CKREF_DIV GENMASK(1, 0)
229 #define REG_CSR_2L_CDR0_PR_MONCK 0x012c
230 #define CSR_2L_PXP_CDR0_PR_MONCK_ENABLE BIT(0)
233 #define REG_CSR_2L_CDR0_PR_COR_HBW 0x0130
237 #define REG_CSR_2L_CDR0_PR_MONPI 0x0134
240 #define REG_CSR_2L_RX0_SIGDET_DCTEST 0x0140
244 #define REG_CSR_2L_RX0_SIGDET_VTH_SEL 0x0144
245 #define CSR_2L_PXP_RX0_SIGDET_VTH_SEL GENMASK(4, 0)
248 #define REG_CSR_2L_PXP_RX0_FE_VB_EQ2 0x0148
249 #define CSR_2L_PXP_RX0_FE_VB_EQ2_EN BIT(0)
253 #define REG_CSR_2L_PXP_RX0_OSCAL_CTLE1IOS 0x0158
256 #define REG_CSR_2L_PXP_RX0_OSCA_VGA1VOS 0x015c
257 #define CSR_2L_PXP_RX0_PR_OSCAL_VGA1VOS GENMASK(5, 0)
260 #define REG_CSR_2L_RX1_REV0 0x01b4
262 #define REG_CSR_2L_RX1_PHYCK_DIV 0x01b8
267 #define REG_CSR_2L_CDR1_PD_PICAL_CKD8_INV 0x01bc
270 #define REG_CSR_2L_CDR1_PR_BETA_DAC 0x01d8
274 #define REG_CSR_2L_CDR1_PR_MONCK 0x01e4
275 #define CSR_2L_PXP_CDR1_PR_MONCK_ENABLE BIT(0)
278 #define REG_CSR_2L_CDR1_LPF_RATIO 0x01c8
281 #define REG_CSR_2L_CDR1_PR_INJ_MODE 0x01d4
284 #define REG_CSR_2L_CDR1_PR_VREG_IBAND_VAL 0x01dc
285 #define CSR_2L_PXP_CDR1_PR_VREG_IBAND GENMASK(2, 0)
288 #define REG_CSR_2L_CDR1_PR_CKREF_DIV 0x01e0
289 #define CSR_2L_PXP_CDR1_PR_CKREF_DIV GENMASK(1, 0)
291 #define REG_CSR_2L_CDR1_PR_COR_HBW 0x01e8
295 #define REG_CSR_2L_CDR1_PR_MONPI 0x01ec
298 #define REG_CSR_2L_RX1_DAC_RANGE_EYE 0x01f4
301 #define REG_CSR_2L_RX1_SIGDET_NOVTH 0x01f8
305 #define REG_CSR_2L_RX1_FE_VB_EQ1 0x0200
306 #define CSR_2L_PXP_RX1_FE_VB_EQ1_EN BIT(0)
311 #define REG_CSR_2L_RX1_OSCAL_VGA1IOS 0x0214
312 #define CSR_2L_PXP_RX1_PR_OSCAL_VGA1IOS GENMASK(5, 0)
317 #define REG_PCIE_PMA_SS_LCPLL_PWCTL_SETTING_1 0x0004
318 #define PCIE_LCPLL_MAN_PWDB BIT(0)
320 #define REG_PCIE_PMA_SEQUENCE_DISB_CTRL1 0x010c
321 #define PCIE_DISB_RX_SDCAL_EN BIT(0)
323 #define REG_PCIE_PMA_CTRL_SEQUENCE_FORCE_CTRL1 0x0114
324 #define PCIE_FORCE_RX_SDCAL_EN BIT(0)
326 #define REG_PCIE_PMA_SS_RX_FREQ_DET1 0x014c
327 #define PCIE_PLL_FT_LOCK_CYCLECNT GENMASK(15, 0)
330 #define REG_PCIE_PMA_SS_RX_FREQ_DET2 0x0150
331 #define PCIE_LOCK_TARGET_BEG GENMASK(15, 0)
334 #define REG_PCIE_PMA_SS_RX_FREQ_DET3 0x0154
335 #define PCIE_UNLOCK_TARGET_BEG GENMASK(15, 0)
338 #define REG_PCIE_PMA_SS_RX_FREQ_DET4 0x0158
339 #define PCIE_FREQLOCK_DET_EN GENMASK(2, 0)
343 #define REG_PCIE_PMA_SS_RX_CAL1 0x0160
344 #define REG_PCIE_PMA_SS_RX_CAL2 0x0164
347 #define REG_PCIE_PMA_SS_RX_SIGDET0 0x0168
350 #define REG_PCIE_PMA_TX_RESET 0x0260
351 #define PCIE_TX_TOP_RST BIT(0)
354 #define REG_PCIE_PMA_RX_FORCE_MODE0 0x0294
355 #define PCIE_FORCE_DA_XPON_RX_FE_GAIN_CTRL GENMASK(1, 0)
357 #define REG_PCIE_PMA_SS_DA_XPON_PWDB0 0x034c
360 #define REG_PCIE_PMA_SW_RESET 0x0460
361 #define PCIE_SW_RX_FIFO_RST BIT(0)
386 #define REG_PCIE_PMA_RO_RX_FREQDET 0x0530
387 #define PCIE_RO_FBCK_LOCK BIT(0)
390 #define REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_IDAC 0x0794
391 #define PCIE_FORCE_DA_PXP_CDR_PR_IDAC GENMASK(10, 0)
395 #define REG_PCIE_PMA_FORCE_DA_PXP_TXPLL_SDM_PCW 0x0798
396 #define PCIE_FORCE_DA_PXP_TXPLL_SDM_PCW GENMASK(30, 0)
398 #define REG_PCIE_PMA_FORCE_DA_PXP_RX_FE_VOS 0x079c
401 #define REG_PCIE_PMA_FORCE_DA_PXP_JCPLL_SDM_PCW 0x0800
402 #define PCIE_FORCE_DA_PXP_JCPLL_SDM_PCW GENMASK(30, 0)
404 #define REG_PCIE_PMA_FORCE_DA_PXP_CDR_PD_PWDB 0x081c
405 #define PCIE_FORCE_DA_PXP_CDR_PD_PWDB BIT(0)
408 #define REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_LPF_C 0x0820
409 #define PCIE_FORCE_DA_PXP_CDR_PR_LPF_C_EN BIT(0)
414 #define REG_PCIE_PMA_FORCE_DA_PXP_CDR_PR_PIEYE_PWDB 0x0824
418 #define REG_PCIE_PMA_FORCE_PXP_JCPLL_CKOUT 0x0828
419 #define PCIE_FORCE_DA_PXP_JCPLL_CKOUT_EN BIT(0)
424 #define REG_PCIE_PMA_FORCE_DA_PXP_RX_SCAN_RST 0x0084c
428 #define REG_PCIE_PMA_FORCE_DA_PXP_TXPLL_CKOUT 0x0854
429 #define PCIE_FORCE_DA_PXP_TXPLL_CKOUT_EN BIT(0)
434 #define REG_PCIE_PMA_SCAN_MODE 0x0884
435 #define PCIE_FORCE_DA_PXP_JCPLL_KBAND_LOAD_EN BIT(0)
438 #define REG_PCIE_PMA_DIG_RESERVE_13 0x08bc
439 #define PCIE_FLL_IDAC_PCIEG1 GENMASK(10, 0)
442 #define REG_PCIE_PMA_DIG_RESERVE_14 0x08c0
443 #define PCIE_FLL_IDAC_PCIEG3 GENMASK(10, 0)
446 #define REG_PCIE_PMA_FORCE_DA_PXP_RX_FE_GAIN_CTRL 0x088c
447 #define PCIE_FORCE_DA_PXP_RX_FE_GAIN_CTRL GENMASK(1, 0)
450 #define REG_PCIE_PMA_FORCE_DA_PXP_RX_FE_PWDB 0x0894
451 #define PCIE_FORCE_DA_PXP_RX_FE_PWDB BIT(0)
454 #define REG_PCIE_PMA_DIG_RESERVE_12 0x08b8
458 #define REG_PCIE_PMA_DIG_RESERVE_17 0x08e0
460 #define REG_PCIE_PMA_DIG_RESERVE_18 0x08e4
461 #define PCIE_PXP_RX_VTH_SEL_PCIE_G1 GENMASK(4, 0)
465 #define REG_PCIE_PMA_DIG_RESERVE_19 0x08e8
468 #define REG_PCIE_PMA_DIG_RESERVE_20 0x08ec
469 #define PCIE_PCP_RX_REV0_PCIE_GEN2 GENMASK(15, 0)
472 #define REG_PCIE_PMA_DIG_RESERVE_21 0x08f0
473 #define REG_PCIE_PMA_DIG_RESERVE_22 0x08f4
474 #define REG_PCIE_PMA_DIG_RESERVE_27 0x0908
475 #define REG_PCIE_PMA_DIG_RESERVE_30 0x0914
478 #define REG_PCIE_PEXTP_DIG_GLB44 0x00
479 #define PCIE_XTP_RXDET_VCM_OFF_STB_T_SEL GENMASK(7, 0)
487 #define REG_PCIE_PEXTP_DIG_LN_RX30_P0 0x0000
488 #define PCIE_XTP_LN_RX_PDOWN_L1P2_EXIT_WAIT GENMASK(7, 0)
492 #define REG_PCIE_PEXTP_DIG_LN_RX30_P1 0x0100