Lines Matching +full:4 +full:x
46 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 4, 0, \
47 1, 4)
50 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ argument
51 FIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
52 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\ argument
53 FIELD_GET(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
55 #define SD10G_LANE_LANE_01_CFG_RXDET_EN BIT(4)
56 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\ argument
57 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
58 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\ argument
59 FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
62 #define SD10G_LANE_LANE_01_CFG_RXDET_STR_SET(x)\ argument
63 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
64 #define SD10G_LANE_LANE_01_CFG_RXDET_STR_GET(x)\ argument
65 FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
70 1, 4)
73 #define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\ argument
74 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_ADV, x)
75 #define SD10G_LANE_LANE_02_CFG_EN_ADV_GET(x)\ argument
76 FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_ADV, x)
79 #define SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(x)\ argument
80 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)
81 #define SD10G_LANE_LANE_02_CFG_EN_MAIN_GET(x)\ argument
82 FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)
85 #define SD10G_LANE_LANE_02_CFG_EN_DLY_SET(x)\ argument
86 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY, x)
87 #define SD10G_LANE_LANE_02_CFG_EN_DLY_GET(x)\ argument
88 FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY, x)
91 #define SD10G_LANE_LANE_02_CFG_EN_DLY2_SET(x)\ argument
92 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)
93 #define SD10G_LANE_LANE_02_CFG_EN_DLY2_GET(x)\ argument
94 FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)
96 #define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0 GENMASK(7, 4)
97 #define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET(x)\ argument
98 FIELD_PREP(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)
99 #define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_GET(x)\ argument
100 FIELD_GET(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)
105 1, 4)
108 #define SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(x)\ argument
109 FIELD_PREP(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)
110 #define SD10G_LANE_LANE_03_CFG_TAP_MAIN_GET(x)\ argument
111 FIELD_GET(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)
116 1, 4)
118 #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0 GENMASK(4, 0)
119 #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET(x)\ argument
120 FIELD_PREP(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)
121 #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_GET(x)\ argument
122 FIELD_GET(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)
127 1, 4)
130 #define SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(x)\ argument
131 FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x)
132 #define SD10G_LANE_LANE_06_CFG_PD_DRIVER_GET(x)\ argument
133 FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x)
136 #define SD10G_LANE_LANE_06_CFG_PD_CLK_SET(x)\ argument
137 FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CLK, x)
138 #define SD10G_LANE_LANE_06_CFG_PD_CLK_GET(x)\ argument
139 FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CLK, x)
142 #define SD10G_LANE_LANE_06_CFG_PD_CML_SET(x)\ argument
143 FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CML, x)
144 #define SD10G_LANE_LANE_06_CFG_PD_CML_GET(x)\ argument
145 FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CML, x)
148 #define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET(x)\ argument
149 FIELD_PREP(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x)
150 #define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_GET(x)\ argument
151 FIELD_GET(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x)
153 #define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN BIT(4)
154 #define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET(x)\ argument
155 FIELD_PREP(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x)
156 #define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_GET(x)\ argument
157 FIELD_GET(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x)
160 #define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET(x)\ argument
161 FIELD_PREP(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x)
162 #define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_GET(x)\ argument
163 FIELD_GET(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x)
168 1, 4)
171 #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET(x)\ argument
172 FIELD_PREP(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x)
173 #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_GET(x)\ argument
174 FIELD_GET(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x)
176 #define SD10G_LANE_LANE_0B_CFG_PD_CTLE BIT(4)
177 #define SD10G_LANE_LANE_0B_CFG_PD_CTLE_SET(x)\ argument
178 FIELD_PREP(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x)
179 #define SD10G_LANE_LANE_0B_CFG_PD_CTLE_GET(x)\ argument
180 FIELD_GET(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x)
183 #define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_SET(x)\ argument
184 FIELD_PREP(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x)
185 #define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_GET(x)\ argument
186 FIELD_GET(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x)
189 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET(x)\ argument
190 FIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x)
191 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_GET(x)\ argument
192 FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x)
195 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_SET(x)\ argument
196 FIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x)
197 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_GET(x)\ argument
198 FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x)
203 1, 4)
206 #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET(x)\ argument
207 FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x)
208 #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_GET(x)\ argument
209 FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x)
212 #define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_SET(x)\ argument
213 FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x)
214 #define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_GET(x)\ argument
215 FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x)
218 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_SET(x)\ argument
219 FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x)
220 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_GET(x)\ argument
221 FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x)
224 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_SET(x)\ argument
225 FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x)
226 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_GET(x)\ argument
227 FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x)
229 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE BIT(4)
230 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET(x)\ argument
231 FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x)
232 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_GET(x)\ argument
233 FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x)
236 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_SET(x)\ argument
237 FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x)
238 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_GET(x)\ argument
239 FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x)
242 #define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_SET(x)\ argument
243 FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x)
244 #define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_GET(x)\ argument
245 FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x)
248 #define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_SET(x)\ argument
249 FIELD_PREP(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x)
250 #define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_GET(x)\ argument
251 FIELD_GET(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x)
256 1, 4)
259 #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_SET(x)\ argument
260 FIELD_PREP(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x)
261 #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_GET(x)\ argument
262 FIELD_GET(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x)
264 #define SD10G_LANE_LANE_0D_CFG_EQR_BYP BIT(4)
265 #define SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(x)\ argument
266 FIELD_PREP(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x)
267 #define SD10G_LANE_LANE_0D_CFG_EQR_BYP_GET(x)\ argument
268 FIELD_GET(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x)
273 1, 4)
276 #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET(x)\ argument
277 FIELD_PREP(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x)
278 #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_GET(x)\ argument
279 FIELD_GET(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x)
281 #define SD10G_LANE_LANE_0E_CFG_RXLB_EN BIT(4)
282 #define SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(x)\ argument
283 FIELD_PREP(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x)
284 #define SD10G_LANE_LANE_0E_CFG_RXLB_EN_GET(x)\ argument
285 FIELD_GET(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x)
288 #define SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(x)\ argument
289 FIELD_PREP(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x)
290 #define SD10G_LANE_LANE_0E_CFG_TXLB_EN_GET(x)\ argument
291 FIELD_GET(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x)
294 #define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET(x)\ argument
295 FIELD_PREP(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x)
296 #define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_GET(x)\ argument
297 FIELD_GET(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x)
302 1, 4)
305 #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET(x)\ argument
306 FIELD_PREP(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x)
307 #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_GET(x)\ argument
308 FIELD_GET(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x)
313 1, 4)
316 #define SD10G_LANE_LANE_13_CFG_DCDR_PD_SET(x)\ argument
317 FIELD_PREP(SD10G_LANE_LANE_13_CFG_DCDR_PD, x)
318 #define SD10G_LANE_LANE_13_CFG_DCDR_PD_GET(x)\ argument
319 FIELD_GET(SD10G_LANE_LANE_13_CFG_DCDR_PD, x)
322 #define SD10G_LANE_LANE_13_CFG_PHID_1T_SET(x)\ argument
323 FIELD_PREP(SD10G_LANE_LANE_13_CFG_PHID_1T, x)
324 #define SD10G_LANE_LANE_13_CFG_PHID_1T_GET(x)\ argument
325 FIELD_GET(SD10G_LANE_LANE_13_CFG_PHID_1T, x)
328 #define SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(x)\ argument
329 FIELD_PREP(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x)
330 #define SD10G_LANE_LANE_13_CFG_CDRCK_EN_GET(x)\ argument
331 FIELD_GET(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x)
336 1, 4)
339 #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET(x)\ argument
340 FIELD_PREP(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x)
341 #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_GET(x)\ argument
342 FIELD_GET(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x)
347 1, 4)
350 #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET(x)\ argument
351 FIELD_PREP(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x)
352 #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_GET(x)\ argument
353 FIELD_GET(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x)
358 1, 4)
361 #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET(x)\ argument
362 FIELD_PREP(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x)
363 #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_GET(x)\ argument
364 FIELD_GET(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x)
369 1, 4)
372 #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_SET(x)\ argument
373 FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x)
374 #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_GET(x)\ argument
375 FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x)
378 #define SD10G_LANE_LANE_1A_CFG_PI_EN_SET(x)\ argument
379 FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_EN, x)
380 #define SD10G_LANE_LANE_1A_CFG_PI_EN_GET(x)\ argument
381 FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_EN, x)
384 #define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET(x)\ argument
385 FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x)
386 #define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_GET(x)\ argument
387 FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x)
390 #define SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(x)\ argument
391 FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x)
392 #define SD10G_LANE_LANE_1A_CFG_PI_STEPS_GET(x)\ argument
393 FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x)
395 #define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0 GENMASK(5, 4)
396 #define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET(x)\ argument
397 FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x)
398 #define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_GET(x)\ argument
399 FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x)
404 1, 4)
406 #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1 GENMASK(4, 0)
407 #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET(x)\ argument
408 FIELD_PREP(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x)
409 #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_GET(x)\ argument
410 FIELD_GET(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x)
415 1, 4)
418 #define SD10G_LANE_LANE_23_CFG_DFE_PD_SET(x)\ argument
419 FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFE_PD, x)
420 #define SD10G_LANE_LANE_23_CFG_DFE_PD_GET(x)\ argument
421 FIELD_GET(SD10G_LANE_LANE_23_CFG_DFE_PD, x)
424 #define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET(x)\ argument
425 FIELD_PREP(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x)
426 #define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_GET(x)\ argument
427 FIELD_GET(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x)
430 #define SD10G_LANE_LANE_23_CFG_DFECK_EN_SET(x)\ argument
431 FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFECK_EN, x)
432 #define SD10G_LANE_LANE_23_CFG_DFECK_EN_GET(x)\ argument
433 FIELD_GET(SD10G_LANE_LANE_23_CFG_DFECK_EN, x)
436 #define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET(x)\ argument
437 FIELD_PREP(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x)
438 #define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_GET(x)\ argument
439 FIELD_GET(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x)
441 #define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0 GENMASK(6, 4)
442 #define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_SET(x)\ argument
443 FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x)
444 #define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_GET(x)\ argument
445 FIELD_GET(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x)
450 1, 4)
453 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET(x)\ argument
454 FIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x)
455 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_GET(x)\ argument
456 FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x)
458 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0 GENMASK(7, 4)
459 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_SET(x)\ argument
460 FIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x)
461 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_GET(x)\ argument
462 FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x)
467 1, 4)
470 #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET(x)\ argument
471 FIELD_PREP(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x)
472 #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_GET(x)\ argument
473 FIELD_GET(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x)
478 1, 4)
481 #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET(x)\ argument
482 FIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x)
483 #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_GET(x)\ argument
484 FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x)
486 #define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0 GENMASK(7, 4)
487 #define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET(x)\ argument
488 FIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x)
489 #define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_GET(x)\ argument
490 FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x)
495 1, 4)
498 #define SD10G_LANE_LANE_30_CFG_SUMMER_EN_SET(x)\ argument
499 FIELD_PREP(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x)
500 #define SD10G_LANE_LANE_30_CFG_SUMMER_EN_GET(x)\ argument
501 FIELD_GET(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x)
503 #define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0 GENMASK(6, 4)
504 #define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET(x)\ argument
505 FIELD_PREP(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x)
506 #define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_GET(x)\ argument
507 FIELD_GET(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x)
512 1, 4)
515 #define SD10G_LANE_LANE_31_CFG_PI_RSTN_SET(x)\ argument
516 FIELD_PREP(SD10G_LANE_LANE_31_CFG_PI_RSTN, x)
517 #define SD10G_LANE_LANE_31_CFG_PI_RSTN_GET(x)\ argument
518 FIELD_GET(SD10G_LANE_LANE_31_CFG_PI_RSTN, x)
521 #define SD10G_LANE_LANE_31_CFG_CDR_RSTN_SET(x)\ argument
522 FIELD_PREP(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x)
523 #define SD10G_LANE_LANE_31_CFG_CDR_RSTN_GET(x)\ argument
524 FIELD_GET(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x)
527 #define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET(x)\ argument
528 FIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x)
529 #define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_GET(x)\ argument
530 FIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x)
533 #define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_SET(x)\ argument
534 FIELD_PREP(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x)
535 #define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_GET(x)\ argument
536 FIELD_GET(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x)
538 #define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8 BIT(4)
539 #define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_SET(x)\ argument
540 FIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x)
541 #define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_GET(x)\ argument
542 FIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x)
545 #define SD10G_LANE_LANE_31_CFG_R50_EN_SET(x)\ argument
546 FIELD_PREP(SD10G_LANE_LANE_31_CFG_R50_EN, x)
547 #define SD10G_LANE_LANE_31_CFG_R50_EN_GET(x)\ argument
548 FIELD_GET(SD10G_LANE_LANE_31_CFG_R50_EN, x)
553 1, 4)
556 #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_SET(x)\ argument
557 FIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x)
558 #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_GET(x)\ argument
559 FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x)
561 #define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)
562 #define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET(x)\ argument
563 FIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x)
564 #define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_GET(x)\ argument
565 FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x)
570 1, 4)
573 #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\ argument
574 FIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x)
575 #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\ argument
576 FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x)
578 #define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0 GENMASK(5, 4)
579 #define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET(x)\ argument
580 FIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x)
581 #define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_GET(x)\ argument
582 FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x)
587 1, 4)
590 #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET(x)\ argument
591 FIELD_PREP(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x)
592 #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_GET(x)\ argument
593 FIELD_GET(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x)
595 #define SD10G_LANE_LANE_35_CFG_RXRATE_1_0 GENMASK(5, 4)
596 #define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET(x)\ argument
597 FIELD_PREP(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x)
598 #define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_GET(x)\ argument
599 FIELD_GET(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x)
604 1, 4)
607 #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET(x)\ argument
608 FIELD_PREP(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x)
609 #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_GET(x)\ argument
610 FIELD_GET(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x)
612 #define SD10G_LANE_LANE_36_CFG_EID_LP BIT(4)
613 #define SD10G_LANE_LANE_36_CFG_EID_LP_SET(x)\ argument
614 FIELD_PREP(SD10G_LANE_LANE_36_CFG_EID_LP, x)
615 #define SD10G_LANE_LANE_36_CFG_EID_LP_GET(x)\ argument
616 FIELD_GET(SD10G_LANE_LANE_36_CFG_EID_LP, x)
619 #define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_SET(x)\ argument
620 FIELD_PREP(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x)
621 #define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_GET(x)\ argument
622 FIELD_GET(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x)
625 #define SD10G_LANE_LANE_36_CFG_PRBS_SEL_SET(x)\ argument
626 FIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x)
627 #define SD10G_LANE_LANE_36_CFG_PRBS_SEL_GET(x)\ argument
628 FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x)
631 #define SD10G_LANE_LANE_36_CFG_PRBS_SETB_SET(x)\ argument
632 FIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x)
633 #define SD10G_LANE_LANE_36_CFG_PRBS_SETB_GET(x)\ argument
634 FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x)
639 1, 4)
642 #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_SET(x)\ argument
643 FIELD_PREP(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x)
644 #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_GET(x)\ argument
645 FIELD_GET(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x)
648 #define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_SET(x)\ argument
649 FIELD_PREP(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x)
650 #define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_GET(x)\ argument
651 FIELD_GET(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x)
654 #define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET(x)\ argument
655 FIELD_PREP(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x)
656 #define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_GET(x)\ argument
657 FIELD_GET(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x)
659 #define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0 GENMASK(5, 4)
660 #define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET(x)\ argument
661 FIELD_PREP(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x)
662 #define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_GET(x)\ argument
663 FIELD_GET(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x)
668 1, 4)
671 #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_SET(x)\ argument
672 FIELD_PREP(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x)
673 #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_GET(x)\ argument
674 FIELD_GET(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x)
676 #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH BIT(4)
677 #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET(x)\ argument
678 FIELD_PREP(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x)
679 #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_GET(x)\ argument
680 FIELD_GET(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x)
685 1, 4)
688 #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_SET(x)\ argument
689 FIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x)
690 #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_GET(x)\ argument
691 FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x)
693 #define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0 GENMASK(7, 4)
694 #define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET(x)\ argument
695 FIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x)
696 #define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_GET(x)\ argument
697 FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x)
702 1, 4)
705 #define SD10G_LANE_LANE_3C_CFG_DIS_ACC_SET(x)\ argument
706 FIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x)
707 #define SD10G_LANE_LANE_3C_CFG_DIS_ACC_GET(x)\ argument
708 FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x)
711 #define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET(x)\ argument
712 FIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x)
713 #define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_GET(x)\ argument
714 FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x)
719 1, 4)
722 #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET(x)\ argument
723 FIELD_PREP(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x)
724 #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_GET(x)\ argument
725 FIELD_GET(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x)
730 1, 4)
733 #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET(x)\ argument
734 FIELD_PREP(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x)
735 #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_GET(x)\ argument
736 FIELD_GET(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x)
741 1, 4)
744 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET(x)\ argument
745 FIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x)
746 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_GET(x)\ argument
747 FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x)
749 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0 GENMASK(6, 4)
750 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_SET(x)\ argument
751 FIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x)
752 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_GET(x)\ argument
753 FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x)
758 1, 4)
761 #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET(x)\ argument
762 FIELD_PREP(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x)
763 #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_GET(x)\ argument
764 FIELD_GET(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x)
766 #define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL BIT(4)
767 #define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_SET(x)\ argument
768 FIELD_PREP(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x)
769 #define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_GET(x)\ argument
770 FIELD_GET(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x)
773 #define SD10G_LANE_LANE_48_CFG_CLK_ENQ_SET(x)\ argument
774 FIELD_PREP(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x)
775 #define SD10G_LANE_LANE_48_CFG_CLK_ENQ_GET(x)\ argument
776 FIELD_GET(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x)
781 1, 4)
784 #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_SET(x)\ argument
785 FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x)
786 #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_GET(x)\ argument
787 FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x)
789 #define SD10G_LANE_LANE_50_CFG_SSC_RESETB BIT(4)
790 #define SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(x)\ argument
791 FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x)
792 #define SD10G_LANE_LANE_50_CFG_SSC_RESETB_GET(x)\ argument
793 FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x)
796 #define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET(x)\ argument
797 FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x)
798 #define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_GET(x)\ argument
799 FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x)
802 #define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_SET(x)\ argument
803 FIELD_PREP(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x)
804 #define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_GET(x)\ argument
805 FIELD_GET(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x)
808 #define SD10G_LANE_LANE_50_CFG_JT_EN_SET(x)\ argument
809 FIELD_PREP(SD10G_LANE_LANE_50_CFG_JT_EN, x)
810 #define SD10G_LANE_LANE_50_CFG_JT_EN_GET(x)\ argument
811 FIELD_GET(SD10G_LANE_LANE_50_CFG_JT_EN, x)
816 1, 4)
819 #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET(x)\ argument
820 FIELD_PREP(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x)
821 #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_GET(x)\ argument
822 FIELD_GET(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x)
827 0, 1, 4)
830 #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_SET(x)\ argument
831 FIELD_PREP(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x)
832 #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_GET(x)\ argument
833 FIELD_GET(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x)
836 #define SD10G_LANE_LANE_83_R_TX_POL_INV_SET(x)\ argument
837 FIELD_PREP(SD10G_LANE_LANE_83_R_TX_POL_INV, x)
838 #define SD10G_LANE_LANE_83_R_TX_POL_INV_GET(x)\ argument
839 FIELD_GET(SD10G_LANE_LANE_83_R_TX_POL_INV, x)
842 #define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_SET(x)\ argument
843 FIELD_PREP(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x)
844 #define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_GET(x)\ argument
845 FIELD_GET(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x)
848 #define SD10G_LANE_LANE_83_R_RX_POL_INV_SET(x)\ argument
849 FIELD_PREP(SD10G_LANE_LANE_83_R_RX_POL_INV, x)
850 #define SD10G_LANE_LANE_83_R_RX_POL_INV_GET(x)\ argument
851 FIELD_GET(SD10G_LANE_LANE_83_R_RX_POL_INV, x)
853 #define SD10G_LANE_LANE_83_R_DFE_RSTN BIT(4)
854 #define SD10G_LANE_LANE_83_R_DFE_RSTN_SET(x)\ argument
855 FIELD_PREP(SD10G_LANE_LANE_83_R_DFE_RSTN, x)
856 #define SD10G_LANE_LANE_83_R_DFE_RSTN_GET(x)\ argument
857 FIELD_GET(SD10G_LANE_LANE_83_R_DFE_RSTN, x)
860 #define SD10G_LANE_LANE_83_R_CDR_RSTN_SET(x)\ argument
861 FIELD_PREP(SD10G_LANE_LANE_83_R_CDR_RSTN, x)
862 #define SD10G_LANE_LANE_83_R_CDR_RSTN_GET(x)\ argument
863 FIELD_GET(SD10G_LANE_LANE_83_R_CDR_RSTN, x)
866 #define SD10G_LANE_LANE_83_R_CTLE_RSTN_SET(x)\ argument
867 FIELD_PREP(SD10G_LANE_LANE_83_R_CTLE_RSTN, x)
868 #define SD10G_LANE_LANE_83_R_CTLE_RSTN_GET(x)\ argument
869 FIELD_GET(SD10G_LANE_LANE_83_R_CTLE_RSTN, x)
874 1, 4)
877 #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_SET(x)\ argument
878 FIELD_PREP(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x)
879 #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_GET(x)\ argument
880 FIELD_GET(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x)
883 #define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(x)\ argument
884 FIELD_PREP(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x)
885 #define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_GET(x)\ argument
886 FIELD_GET(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x)
889 #define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_SET(x)\ argument
890 FIELD_PREP(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x)
891 #define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_GET(x)\ argument
892 FIELD_GET(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x)
895 #define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(x)\ argument
896 FIELD_PREP(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x)
897 #define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_GET(x)\ argument
898 FIELD_GET(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x)
900 #define SD10G_LANE_LANE_93_R_REG_MANUAL BIT(4)
901 #define SD10G_LANE_LANE_93_R_REG_MANUAL_SET(x)\ argument
902 FIELD_PREP(SD10G_LANE_LANE_93_R_REG_MANUAL, x)
903 #define SD10G_LANE_LANE_93_R_REG_MANUAL_GET(x)\ argument
904 FIELD_GET(SD10G_LANE_LANE_93_R_REG_MANUAL, x)
907 #define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(x)\ argument
908 FIELD_PREP(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x)
909 #define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_GET(x)\ argument
910 FIELD_GET(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x)
913 #define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(x)\ argument
914 FIELD_PREP(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x)
915 #define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_GET(x)\ argument
916 FIELD_GET(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x)
919 #define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_SET(x)\ argument
920 FIELD_PREP(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x)
921 #define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_GET(x)\ argument
922 FIELD_GET(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x)
927 1, 4)
930 #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET(x)\ argument
931 FIELD_PREP(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x)
932 #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_GET(x)\ argument
933 FIELD_GET(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x)
935 #define SD10G_LANE_LANE_94_R_ISCAN_REG BIT(4)
936 #define SD10G_LANE_LANE_94_R_ISCAN_REG_SET(x)\ argument
937 FIELD_PREP(SD10G_LANE_LANE_94_R_ISCAN_REG, x)
938 #define SD10G_LANE_LANE_94_R_ISCAN_REG_GET(x)\ argument
939 FIELD_GET(SD10G_LANE_LANE_94_R_ISCAN_REG, x)
942 #define SD10G_LANE_LANE_94_R_TXEQ_REG_SET(x)\ argument
943 FIELD_PREP(SD10G_LANE_LANE_94_R_TXEQ_REG, x)
944 #define SD10G_LANE_LANE_94_R_TXEQ_REG_GET(x)\ argument
945 FIELD_GET(SD10G_LANE_LANE_94_R_TXEQ_REG, x)
948 #define SD10G_LANE_LANE_94_R_MISC_REG_SET(x)\ argument
949 FIELD_PREP(SD10G_LANE_LANE_94_R_MISC_REG, x)
950 #define SD10G_LANE_LANE_94_R_MISC_REG_GET(x)\ argument
951 FIELD_GET(SD10G_LANE_LANE_94_R_MISC_REG, x)
954 #define SD10G_LANE_LANE_94_R_SWING_REG_SET(x)\ argument
955 FIELD_PREP(SD10G_LANE_LANE_94_R_SWING_REG, x)
956 #define SD10G_LANE_LANE_94_R_SWING_REG_GET(x)\ argument
957 FIELD_GET(SD10G_LANE_LANE_94_R_SWING_REG, x)
962 1, 4)
965 #define SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(x)\ argument
966 FIELD_PREP(SD10G_LANE_LANE_9E_R_RXEQ_REG, x)
967 #define SD10G_LANE_LANE_9E_R_RXEQ_REG_GET(x)\ argument
968 FIELD_GET(SD10G_LANE_LANE_9E_R_RXEQ_REG, x)
971 #define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_SET(x)\ argument
972 FIELD_PREP(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x)
973 #define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_GET(x)\ argument
974 FIELD_GET(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x)
977 #define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET(x)\ argument
978 FIELD_PREP(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x)
979 #define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_GET(x)\ argument
980 FIELD_GET(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x)
984 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 640, 0, 1, 128, 4, 0,\
985 1, 4)
988 #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_SET(x)\ argument
989 FIELD_PREP(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x)
990 #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_GET(x)\ argument
991 FIELD_GET(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x)
993 #define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT BIT(4)
994 #define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(x)\ argument
995 FIELD_PREP(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x)
996 #define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_GET(x)\ argument
997 FIELD_GET(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x)
1000 #define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(x)\ argument
1001 FIELD_PREP(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x)
1002 #define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_GET(x)\ argument
1003 FIELD_GET(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x)
1006 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(x)\ argument
1007 FIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x)
1008 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_GET(x)\ argument
1009 FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x)
1012 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_SET(x)\ argument
1013 FIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING, x)
1014 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_GET(x)\ argument
1015 FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING, x)
1020 1, 4)
1022 #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0)
1023 #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET(x)\ argument
1024 FIELD_PREP(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x)
1025 #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_GET(x)\ argument
1026 FIELD_GET(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x)
1031 1, 4)
1034 #define SD10G_LANE_LANE_DF_LOL_UDL_SET(x)\ argument
1035 FIELD_PREP(SD10G_LANE_LANE_DF_LOL_UDL, x)
1036 #define SD10G_LANE_LANE_DF_LOL_UDL_GET(x)\ argument
1037 FIELD_GET(SD10G_LANE_LANE_DF_LOL_UDL, x)
1040 #define SD10G_LANE_LANE_DF_LOL_SET(x)\ argument
1041 FIELD_PREP(SD10G_LANE_LANE_DF_LOL, x)
1042 #define SD10G_LANE_LANE_DF_LOL_GET(x)\ argument
1043 FIELD_GET(SD10G_LANE_LANE_DF_LOL, x)
1046 #define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\ argument
1047 FIELD_PREP(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
1048 #define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\ argument
1049 FIELD_GET(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
1052 #define SD10G_LANE_LANE_DF_SQUELCH_SET(x)\ argument
1053 FIELD_PREP(SD10G_LANE_LANE_DF_SQUELCH, x)
1054 #define SD10G_LANE_LANE_DF_SQUELCH_GET(x)\ argument
1055 FIELD_GET(SD10G_LANE_LANE_DF_SQUELCH, x)
1060 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 36, 0, 1, 4)
1063 #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_SET(x)\ argument
1064 FIELD_PREP(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x)
1065 #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_GET(x)\ argument
1066 FIELD_GET(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x)
1069 #define SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(x)\ argument
1070 FIELD_PREP(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x)
1071 #define SD25G_LANE_CMU_09_CFG_EN_DUMMY_GET(x)\ argument
1072 FIELD_GET(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x)
1075 #define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_SET(x)\ argument
1076 FIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x)
1077 #define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_GET(x)\ argument
1078 FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x)
1081 #define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_SET(x)\ argument
1082 FIELD_PREP(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x)
1083 #define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_GET(x)\ argument
1084 FIELD_GET(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x)
1086 #define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0 GENMASK(5, 4)
1087 #define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_SET(x)\ argument
1088 FIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x)
1089 #define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_GET(x)\ argument
1090 FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x)
1095 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 44, 0, 1, 4)
1098 #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_SET(x)\ argument
1099 FIELD_PREP(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x)
1100 #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_GET(x)\ argument
1101 FIELD_GET(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x)
1104 #define SD25G_LANE_CMU_0B_CFG_DISLOL_SET(x)\ argument
1105 FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DISLOL, x)
1106 #define SD25G_LANE_CMU_0B_CFG_DISLOL_GET(x)\ argument
1107 FIELD_GET(SD25G_LANE_CMU_0B_CFG_DISLOL, x)
1110 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_SET(x)\ argument
1111 FIELD_PREP(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN, x)
1112 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_GET(x)\ argument
1113 FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN, x)
1116 #define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(x)\ argument
1117 FIELD_PREP(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, x)
1118 #define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_GET(x)\ argument
1119 FIELD_GET(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, x)
1121 #define SD25G_LANE_CMU_0B_CFG_VFILT2PAD BIT(4)
1122 #define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_SET(x)\ argument
1123 FIELD_PREP(SD25G_LANE_CMU_0B_CFG_VFILT2PAD, x)
1124 #define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_GET(x)\ argument
1125 FIELD_GET(SD25G_LANE_CMU_0B_CFG_VFILT2PAD, x)
1128 #define SD25G_LANE_CMU_0B_CFG_DISLOS_SET(x)\ argument
1129 FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DISLOS, x)
1130 #define SD25G_LANE_CMU_0B_CFG_DISLOS_GET(x)\ argument
1131 FIELD_GET(SD25G_LANE_CMU_0B_CFG_DISLOS, x)
1134 #define SD25G_LANE_CMU_0B_CFG_DCLOL_SET(x)\ argument
1135 FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DCLOL, x)
1136 #define SD25G_LANE_CMU_0B_CFG_DCLOL_GET(x)\ argument
1137 FIELD_GET(SD25G_LANE_CMU_0B_CFG_DCLOL, x)
1140 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_SET(x)\ argument
1141 FIELD_PREP(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x)
1142 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_GET(x)\ argument
1143 FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x)
1148 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 48, 0, 1, 4)
1151 #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(x)\ argument
1152 FIELD_PREP(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET, x)
1153 #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_GET(x)\ argument
1154 FIELD_GET(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET, x)
1157 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_SET(x)\ argument
1158 FIELD_PREP(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN, x)
1159 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_GET(x)\ argument
1160 FIELD_GET(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN, x)
1163 #define SD25G_LANE_CMU_0C_CFG_VCO_PD_SET(x)\ argument
1164 FIELD_PREP(SD25G_LANE_CMU_0C_CFG_VCO_PD, x)
1165 #define SD25G_LANE_CMU_0C_CFG_VCO_PD_GET(x)\ argument
1166 FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_PD, x)
1169 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_SET(x)\ argument
1170 FIELD_PREP(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP, x)
1171 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_GET(x)\ argument
1172 FIELD_GET(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP, x)
1174 #define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0 GENMASK(5, 4)
1175 #define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_SET(x)\ argument
1176 FIELD_PREP(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x)
1177 #define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_GET(x)\ argument
1178 FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x)
1183 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 52, 0, 1, 4)
1186 #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_SET(x)\ argument
1187 FIELD_PREP(SD25G_LANE_CMU_0D_CFG_CK_TREE_PD, x)
1188 #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_GET(x)\ argument
1189 FIELD_GET(SD25G_LANE_CMU_0D_CFG_CK_TREE_PD, x)
1192 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_SET(x)\ argument
1193 FIELD_PREP(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN, x)
1194 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_GET(x)\ argument
1195 FIELD_GET(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN, x)
1198 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_SET(x)\ argument
1199 FIELD_PREP(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP, x)
1200 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_GET(x)\ argument
1201 FIELD_GET(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP, x)
1204 #define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_SET(x)\ argument
1205 FIELD_PREP(SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP, x)
1206 #define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_GET(x)\ argument
1207 FIELD_GET(SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP, x)
1209 #define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0 GENMASK(5, 4)
1210 #define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET(x)\ argument
1211 FIELD_PREP(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x)
1212 #define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_GET(x)\ argument
1213 FIELD_GET(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x)
1218 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 56, 0, 1, 4)
1221 #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(x)\ argument
1222 FIELD_PREP(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, x)
1223 #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_GET(x)\ argument
1224 FIELD_GET(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, x)
1226 #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD BIT(4)
1227 #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_SET(x)\ argument
1228 FIELD_PREP(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x)
1229 #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_GET(x)\ argument
1230 FIELD_GET(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x)
1235 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 76, 0, 1, 4)
1238 #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET(x)\ argument
1239 FIELD_PREP(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, x)
1240 #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_GET(x)\ argument
1241 FIELD_GET(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, x)
1243 #define SD25G_LANE_CMU_13_CFG_JT_EN BIT(4)
1244 #define SD25G_LANE_CMU_13_CFG_JT_EN_SET(x)\ argument
1245 FIELD_PREP(SD25G_LANE_CMU_13_CFG_JT_EN, x)
1246 #define SD25G_LANE_CMU_13_CFG_JT_EN_GET(x)\ argument
1247 FIELD_GET(SD25G_LANE_CMU_13_CFG_JT_EN, x)
1252 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 96, 0, 1, 4)
1255 #define SD25G_LANE_CMU_18_R_PLL_RSTN_SET(x)\ argument
1256 FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_RSTN, x)
1257 #define SD25G_LANE_CMU_18_R_PLL_RSTN_GET(x)\ argument
1258 FIELD_GET(SD25G_LANE_CMU_18_R_PLL_RSTN, x)
1261 #define SD25G_LANE_CMU_18_R_PLL_LOL_SET_SET(x)\ argument
1262 FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_LOL_SET, x)
1263 #define SD25G_LANE_CMU_18_R_PLL_LOL_SET_GET(x)\ argument
1264 FIELD_GET(SD25G_LANE_CMU_18_R_PLL_LOL_SET, x)
1267 #define SD25G_LANE_CMU_18_R_PLL_LOS_SET_SET(x)\ argument
1268 FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_LOS_SET, x)
1269 #define SD25G_LANE_CMU_18_R_PLL_LOS_SET_GET(x)\ argument
1270 FIELD_GET(SD25G_LANE_CMU_18_R_PLL_LOS_SET, x)
1272 #define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0 GENMASK(5, 4)
1273 #define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_SET(x)\ argument
1274 FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x)
1275 #define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_GET(x)\ argument
1276 FIELD_GET(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x)
1281 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 100, 0, 1, 4)
1284 #define SD25G_LANE_CMU_19_R_CK_RESETB_SET(x)\ argument
1285 FIELD_PREP(SD25G_LANE_CMU_19_R_CK_RESETB, x)
1286 #define SD25G_LANE_CMU_19_R_CK_RESETB_GET(x)\ argument
1287 FIELD_GET(SD25G_LANE_CMU_19_R_CK_RESETB, x)
1290 #define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_SET(x)\ argument
1291 FIELD_PREP(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x)
1292 #define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_GET(x)\ argument
1293 FIELD_GET(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x)
1298 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 104, 0, 1, 4)
1301 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(x)\ argument
1302 FIELD_PREP(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, x)
1303 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_GET(x)\ argument
1304 FIELD_GET(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, x)
1306 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT BIT(4)
1307 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET(x)\ argument
1308 FIELD_PREP(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT, x)
1309 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_GET(x)\ argument
1310 FIELD_GET(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT, x)
1313 #define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_SET(x)\ argument
1314 FIELD_PREP(SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE, x)
1315 #define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_GET(x)\ argument
1316 FIELD_GET(SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE, x)
1319 #define SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(x)\ argument
1320 FIELD_PREP(SD25G_LANE_CMU_1A_R_REG_MANUAL, x)
1321 #define SD25G_LANE_CMU_1A_R_REG_MANUAL_GET(x)\ argument
1322 FIELD_GET(SD25G_LANE_CMU_1A_R_REG_MANUAL, x)
1327 __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 36, 0, 1, 4)
1330 #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_SET(x)\ argument
1331 FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_SEL_1_0, x)
1332 #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_GET(x)\ argument
1333 FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_SEL_1_0, x)
1335 #define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE BIT(4)
1336 #define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_SET(x)\ argument
1337 FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_LINK_LANE, x)
1338 #define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_GET(x)\ argument
1339 FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LINK_LANE, x)
1342 #define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(x)\ argument
1343 FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x)
1344 #define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_GET(x)\ argument
1345 FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x)
1350 __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 60, 0, 1, 4)
1353 #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET(x)\ argument
1354 FIELD_PREP(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0, x)
1355 #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_GET(x)\ argument
1356 FIELD_GET(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0, x)
1358 #define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0 GENMASK(6, 4)
1359 #define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_SET(x)\ argument
1360 FIELD_PREP(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x)
1361 #define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_GET(x)\ argument
1362 FIELD_GET(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x)
1367 __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 64, 0, 1, 4)
1370 #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET(x)\ argument
1371 FIELD_PREP(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x)
1372 #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_GET(x)\ argument
1373 FIELD_GET(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x)
1378 __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 0, 0, 1, 4)
1381 #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_SET(x)\ argument
1382 FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL, x)
1383 #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_GET(x)\ argument
1384 FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL, x)
1387 #define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_SET(x)\ argument
1388 FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD, x)
1389 #define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_GET(x)\ argument
1390 FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD, x)
1393 #define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_SET(x)\ argument
1394 FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_PD_CLK, x)
1395 #define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_GET(x)\ argument
1396 FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_PD_CLK, x)
1399 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(x)\ argument
1400 FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, x)
1401 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_GET(x)\ argument
1402 FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, x)
1404 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN BIT(4)
1405 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_SET(x)\ argument
1406 FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN, x)
1407 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_GET(x)\ argument
1408 FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN, x)
1411 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_SET(x)\ argument
1412 FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x)
1413 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_GET(x)\ argument
1414 FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x)
1419 __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 20, 0, 1, 4)
1422 #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET(x)\ argument
1423 FIELD_PREP(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x)
1424 #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_GET(x)\ argument
1425 FIELD_GET(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x)
1430 __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 24, 0, 1, 4)
1433 #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET(x)\ argument
1434 FIELD_PREP(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x)
1435 #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_GET(x)\ argument
1436 FIELD_GET(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x)
1441 __REG(TARGET_SD25G_LANE, t, 8, 768, 0, 1, 252, 0, 0, 1, 4)
1444 #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_SET(x)\ argument
1445 FIELD_PREP(SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0, x)
1446 #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_GET(x)\ argument
1447 FIELD_GET(SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0, x)
1449 #define SD25G_LANE_CMU_C0_PLL_LOL_UDL BIT(4)
1450 #define SD25G_LANE_CMU_C0_PLL_LOL_UDL_SET(x)\ argument
1451 FIELD_PREP(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x)
1452 #define SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(x)\ argument
1453 FIELD_GET(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x)
1458 __REG(TARGET_SD25G_LANE, t, 8, 1020, 0, 1, 4, 0, 0, 1, 4)
1461 #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(x)\ argument
1462 FIELD_PREP(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x)
1463 #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_GET(x)\ argument
1464 FIELD_GET(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x)
1469 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 0, 0, 1, 4)
1472 #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_SET(x)\ argument
1473 FIELD_PREP(SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0, x)
1474 #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_GET(x)\ argument
1475 FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0, x)
1477 #define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)
1478 #define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET(x)\ argument
1479 FIELD_PREP(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x)
1480 #define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_GET(x)\ argument
1481 FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x)
1486 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 4, 0, 1, 4)
1489 #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\ argument
1490 FIELD_PREP(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, x)
1491 #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\ argument
1492 FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, x)
1494 #define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0 GENMASK(5, 4)
1495 #define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET(x)\ argument
1496 FIELD_PREP(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x)
1497 #define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_GET(x)\ argument
1498 FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x)
1503 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 12, 0, 1, 4)
1505 #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0 GENMASK(4, 0)
1506 #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(x)\ argument
1507 FIELD_PREP(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x)
1508 #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_GET(x)\ argument
1509 FIELD_GET(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x)
1514 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 16, 0, 1, 4)
1517 #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(x)\ argument
1518 FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, x)
1519 #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_GET(x)\ argument
1520 FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, x)
1523 #define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(x)\ argument
1524 FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN, x)
1525 #define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_GET(x)\ argument
1526 FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN, x)
1529 #define SD25G_LANE_LANE_04_LN_CFG_PD_CML_SET(x)\ argument
1530 FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_CML, x)
1531 #define SD25G_LANE_LANE_04_LN_CFG_PD_CML_GET(x)\ argument
1532 FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_CML, x)
1535 #define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_SET(x)\ argument
1536 FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_CLK, x)
1537 #define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_GET(x)\ argument
1538 FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_CLK, x)
1540 #define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER BIT(4)
1541 #define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_SET(x)\ argument
1542 FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, x)
1543 #define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_GET(x)\ argument
1544 FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, x)
1547 #define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_SET(x)\ argument
1548 FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x)
1549 #define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_GET(x)\ argument
1550 FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x)
1555 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 20, 0, 1, 4)
1558 #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_SET(x)\ argument
1559 FIELD_PREP(SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0, x)
1560 #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_GET(x)\ argument
1561 FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0, x)
1563 #define SD25G_LANE_LANE_05_LN_CFG_BW_1_0 GENMASK(5, 4)
1564 #define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(x)\ argument
1565 FIELD_PREP(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x)
1566 #define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_GET(x)\ argument
1567 FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x)
1572 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 24, 0, 1, 4)
1575 #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_SET(x)\ argument
1576 FIELD_PREP(SD25G_LANE_LANE_06_LN_CFG_EN_MAIN, x)
1577 #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_GET(x)\ argument
1578 FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_EN_MAIN, x)
1580 #define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0 GENMASK(7, 4)
1581 #define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(x)\ argument
1582 FIELD_PREP(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x)
1583 #define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_GET(x)\ argument
1584 FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x)
1589 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 28, 0, 1, 4)
1592 #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(x)\ argument
1593 FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_ADV, x)
1594 #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_GET(x)\ argument
1595 FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_ADV, x)
1598 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_SET(x)\ argument
1599 FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_DLY2, x)
1600 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_GET(x)\ argument
1601 FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY2, x)
1604 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(x)\ argument
1605 FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x)
1606 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_GET(x)\ argument
1607 FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x)
1612 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 36, 0, 1, 4)
1615 #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET(x)\ argument
1616 FIELD_PREP(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x)
1617 #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_GET(x)\ argument
1618 FIELD_GET(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x)
1623 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 40, 0, 1, 4)
1626 #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET(x)\ argument
1627 FIELD_PREP(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x)
1628 #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_GET(x)\ argument
1629 FIELD_GET(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x)
1634 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 44, 0, 1, 4)
1637 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET(x)\ argument
1638 FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, x)
1639 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_GET(x)\ argument
1640 FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, x)
1643 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_SET(x)\ argument
1644 FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST, x)
1645 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_GET(x)\ argument
1646 FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST, x)
1648 #define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0 GENMASK(5, 4)
1649 #define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_SET(x)\ argument
1650 FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x)
1651 #define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_GET(x)\ argument
1652 FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x)
1657 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 48, 0, 1, 4)
1660 #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ argument
1661 FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
1662 #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\ argument
1663 FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
1665 #define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN BIT(4)
1666 #define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_SET(x)\ argument
1667 FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN, x)
1668 #define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_GET(x)\ argument
1669 FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN, x)
1672 #define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_SET(x)\ argument
1673 FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x)
1674 #define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_GET(x)\ argument
1675 FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x)
1680 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 52, 0, 1, 4)
1683 #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(x)\ argument
1684 FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, x)
1685 #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_GET(x)\ argument
1686 FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, x)
1688 #define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8 BIT(4)
1689 #define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_SET(x)\ argument
1690 FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8, x)
1691 #define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_GET(x)\ argument
1692 FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8, x)
1695 #define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_SET(x)\ argument
1696 FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN, x)
1697 #define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_GET(x)\ argument
1698 FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN, x)
1701 #define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_SET(x)\ argument
1702 FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD, x)
1703 #define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_GET(x)\ argument
1704 FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD, x)
1707 #define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(x)\ argument
1708 FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x)
1709 #define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_GET(x)\ argument
1710 FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x)
1715 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 56, 0, 1, 4)
1718 #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_SET(x)\ argument
1719 FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN, x)
1720 #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_GET(x)\ argument
1721 FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN, x)
1724 #define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_SET(x)\ argument
1725 FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD, x)
1726 #define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_GET(x)\ argument
1727 FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD, x)
1730 #define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(x)\ argument
1731 FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, x)
1732 #define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_GET(x)\ argument
1733 FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, x)
1735 #define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0 GENMASK(6, 4)
1736 #define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_SET(x)\ argument
1737 FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x)
1738 #define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_GET(x)\ argument
1739 FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x)
1744 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 60, 0, 1, 4)
1746 #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1 GENMASK(4, 0)
1747 #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET(x)\ argument
1748 FIELD_PREP(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x)
1749 #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_GET(x)\ argument
1750 FIELD_GET(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x)
1755 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 96, 0, 1, 4)
1758 #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(x)\ argument
1759 FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, x)
1760 #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_GET(x)\ argument
1761 FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, x)
1764 #define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_SET(x)\ argument
1765 FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT, x)
1766 #define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_GET(x)\ argument
1767 FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT, x)
1770 #define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_SET(x)\ argument
1771 FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN, x)
1772 #define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_GET(x)\ argument
1773 FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN, x)
1776 #define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(x)\ argument
1777 FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, x)
1778 #define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_GET(x)\ argument
1779 FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, x)
1781 #define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0 GENMASK(6, 4)
1782 #define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_SET(x)\ argument
1783 FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x)
1784 #define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_GET(x)\ argument
1785 FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x)
1790 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 100, 0, 1, 4)
1793 #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_SET(x)\ argument
1794 FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_DCDR_PD, x)
1795 #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_GET(x)\ argument
1796 FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_DCDR_PD, x)
1799 #define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(x)\ argument
1800 FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, x)
1801 #define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_GET(x)\ argument
1802 FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, x)
1805 #define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_SET(x)\ argument
1806 FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL, x)
1807 #define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_GET(x)\ argument
1808 FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL, x)
1811 #define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(x)\ argument
1812 FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, x)
1813 #define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_GET(x)\ argument
1814 FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, x)
1816 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU BIT(4)
1817 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_SET(x)\ argument
1818 FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU, x)
1819 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_GET(x)\ argument
1820 FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU, x)
1823 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_SET(x)\ argument
1824 FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP, x)
1825 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_GET(x)\ argument
1826 FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP, x)
1829 #define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_SET(x)\ argument
1830 FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET, x)
1831 #define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_GET(x)\ argument
1832 FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET, x)
1835 #define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_SET(x)\ argument
1836 FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x)
1837 #define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_GET(x)\ argument
1838 FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x)
1843 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 104, 0, 1, 4)
1846 #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_SET(x)\ argument
1847 FIELD_PREP(SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN, x)
1848 #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_GET(x)\ argument
1849 FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN, x)
1851 #define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0 GENMASK(6, 4)
1852 #define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(x)\ argument
1853 FIELD_PREP(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x)
1854 #define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_GET(x)\ argument
1855 FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x)
1860 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 108, 0, 1, 4)
1863 #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(x)\ argument
1864 FIELD_PREP(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x)
1865 #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_GET(x)\ argument
1866 FIELD_GET(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x)
1871 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 112, 0, 1, 4)
1874 #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(x)\ argument
1875 FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, x)
1876 #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_GET(x)\ argument
1877 FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, x)
1880 #define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(x)\ argument
1881 FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, x)
1882 #define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_GET(x)\ argument
1883 FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, x)
1886 #define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_SET(x)\ argument
1887 FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD, x)
1888 #define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_GET(x)\ argument
1889 FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD, x)
1891 #define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0 GENMASK(7, 4)
1892 #define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_SET(x)\ argument
1893 FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x)
1894 #define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_GET(x)\ argument
1895 FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x)
1900 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 116, 0, 1, 4)
1903 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_SET(x)\ argument
1904 FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR, x)
1905 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_GET(x)\ argument
1906 FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR, x)
1909 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_SET(x)\ argument
1910 FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD, x)
1911 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_GET(x)\ argument
1912 FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD, x)
1915 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_SET(x)\ argument
1916 FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN, x)
1917 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_GET(x)\ argument
1918 FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN, x)
1921 #define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_SET(x)\ argument
1922 FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP, x)
1923 #define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_GET(x)\ argument
1924 FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP, x)
1926 #define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T BIT(4)
1927 #define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_SET(x)\ argument
1928 FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PHID_1T, x)
1929 #define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_GET(x)\ argument
1930 FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PHID_1T, x)
1933 #define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(x)\ argument
1934 FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, x)
1935 #define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_GET(x)\ argument
1936 FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, x)
1939 #define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_SET(x)\ argument
1940 FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR, x)
1941 #define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_GET(x)\ argument
1942 FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR, x)
1945 #define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_SET(x)\ argument
1946 FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x)
1947 #define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_GET(x)\ argument
1948 FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x)
1953 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 120, 0, 1, 4)
1956 #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_SET(x)\ argument
1957 FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0, x)
1958 #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_GET(x)\ argument
1959 FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0, x)
1961 #define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN BIT(4)
1962 #define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(x)\ argument
1963 FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, x)
1964 #define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_GET(x)\ argument
1965 FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, x)
1968 #define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_SET(x)\ argument
1969 FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, x)
1970 #define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_GET(x)\ argument
1971 FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, x)
1974 #define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_SET(x)\ argument
1975 FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR, x)
1976 #define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_GET(x)\ argument
1977 FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR, x)
1980 #define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_SET(x)\ argument
1981 FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x)
1982 #define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_GET(x)\ argument
1983 FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x)
1988 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 132, 0, 1, 4)
1990 #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0 GENMASK(4, 0)
1991 #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET(x)\ argument
1992 FIELD_PREP(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x)
1993 #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_GET(x)\ argument
1994 FIELD_GET(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x)
1999 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 136, 0, 1, 4)
2002 #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET(x)\ argument
2003 FIELD_PREP(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x)
2004 #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_GET(x)\ argument
2005 FIELD_GET(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x)
2010 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 148, 0, 1, 4)
2013 #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET(x)\ argument
2014 FIELD_PREP(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x)
2015 #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_GET(x)\ argument
2016 FIELD_GET(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x)
2021 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 152, 0, 1, 4)
2024 #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET(x)\ argument
2025 FIELD_PREP(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x)
2026 #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_GET(x)\ argument
2027 FIELD_GET(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x)
2032 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 160, 0, 1, 4)
2035 #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_SET(x)\ argument
2036 FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN, x)
2037 #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_GET(x)\ argument
2038 FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN, x)
2041 #define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_SET(x)\ argument
2042 FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH, x)
2043 #define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_GET(x)\ argument
2044 FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH, x)
2047 #define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_SET(x)\ argument
2048 FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL, x)
2049 #define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_GET(x)\ argument
2050 FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL, x)
2052 #define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0 GENMASK(6, 4)
2053 #define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_SET(x)\ argument
2054 FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x)
2055 #define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_GET(x)\ argument
2056 FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x)
2061 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 172, 0, 1, 4)
2064 #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(x)\ argument
2065 FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, x)
2066 #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_GET(x)\ argument
2067 FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, x)
2069 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR BIT(4)
2070 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_SET(x)\ argument
2071 FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR, x)
2072 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_GET(x)\ argument
2073 FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR, x)
2076 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_SET(x)\ argument
2077 FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x)
2078 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_GET(x)\ argument
2079 FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x)
2084 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 176, 0, 1, 4)
2087 #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET(x)\ argument
2088 FIELD_PREP(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, x)
2089 #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_GET(x)\ argument
2090 FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, x)
2092 #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER BIT(4)
2093 #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_SET(x)\ argument
2094 FIELD_PREP(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x)
2095 #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_GET(x)\ argument
2096 FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x)
2101 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 180, 0, 1, 4)
2104 #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET(x)\ argument
2105 FIELD_PREP(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, x)
2106 #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_GET(x)\ argument
2107 FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, x)
2109 #define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0 GENMASK(6, 4)
2110 #define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_SET(x)\ argument
2111 FIELD_PREP(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x)
2112 #define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_GET(x)\ argument
2113 FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x)
2118 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 184, 0, 1, 4)
2121 #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_SET(x)\ argument
2122 FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN, x)
2123 #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_GET(x)\ argument
2124 FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN, x)
2127 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(x)\ argument
2128 FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, x)
2129 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_GET(x)\ argument
2130 FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, x)
2133 #define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(x)\ argument
2134 FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, x)
2135 #define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_GET(x)\ argument
2136 FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, x)
2139 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_SET(x)\ argument
2140 FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS, x)
2141 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_GET(x)\ argument
2142 FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS, x)
2144 #define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC BIT(4)
2145 #define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_SET(x)\ argument
2146 FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC, x)
2147 #define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_GET(x)\ argument
2148 FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC, x)
2151 #define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(x)\ argument
2152 FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, x)
2153 #define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_GET(x)\ argument
2154 FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, x)
2157 #define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_SET(x)\ argument
2158 FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN, x)
2159 #define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_GET(x)\ argument
2160 FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN, x)
2163 #define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(x)\ argument
2164 FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x)
2165 #define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_GET(x)\ argument
2166 FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x)
2171 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 256, 0, 1, 4)
2174 #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_SET(x)\ argument
2175 FIELD_PREP(SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE, x)
2176 #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_GET(x)\ argument
2177 FIELD_GET(SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE, x)
2180 #define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(x)\ argument
2181 FIELD_PREP(SD25G_LANE_LANE_40_LN_R_TX_POL_INV, x)
2182 #define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_GET(x)\ argument
2183 FIELD_GET(SD25G_LANE_LANE_40_LN_R_TX_POL_INV, x)
2186 #define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_SET(x)\ argument
2187 FIELD_PREP(SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE, x)
2188 #define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_GET(x)\ argument
2189 FIELD_GET(SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE, x)
2192 #define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(x)\ argument
2193 FIELD_PREP(SD25G_LANE_LANE_40_LN_R_RX_POL_INV, x)
2194 #define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_GET(x)\ argument
2195 FIELD_GET(SD25G_LANE_LANE_40_LN_R_RX_POL_INV, x)
2197 #define SD25G_LANE_LANE_40_LN_R_CDR_RSTN BIT(4)
2198 #define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_SET(x)\ argument
2199 FIELD_PREP(SD25G_LANE_LANE_40_LN_R_CDR_RSTN, x)
2200 #define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_GET(x)\ argument
2201 FIELD_GET(SD25G_LANE_LANE_40_LN_R_CDR_RSTN, x)
2204 #define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_SET(x)\ argument
2205 FIELD_PREP(SD25G_LANE_LANE_40_LN_R_DFE_RSTN, x)
2206 #define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_GET(x)\ argument
2207 FIELD_GET(SD25G_LANE_LANE_40_LN_R_DFE_RSTN, x)
2210 #define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_SET(x)\ argument
2211 FIELD_PREP(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x)
2212 #define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_GET(x)\ argument
2213 FIELD_GET(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x)
2218 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 264, 0, 1, 4)
2221 #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET(x)\ argument
2222 FIELD_PREP(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x)
2223 #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_GET(x)\ argument
2224 FIELD_GET(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x)
2229 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 268, 0, 1, 4)
2232 #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET(x)\ argument
2233 FIELD_PREP(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x)
2234 #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_GET(x)\ argument
2235 FIELD_GET(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x)
2240 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 272, 0, 1, 4)
2243 #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET(x)\ argument
2244 FIELD_PREP(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x)
2245 #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_GET(x)\ argument
2246 FIELD_GET(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x)
2251 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 276, 0, 1, 4)
2254 #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET(x)\ argument
2255 FIELD_PREP(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x)
2256 #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_GET(x)\ argument
2257 FIELD_GET(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x)
2262 __REG(TARGET_SD25G_LANE, t, 8, 1792, 0, 1, 128, 120, 0, 1, 4)
2265 #define SD25G_LANE_LANE_DE_LN_LOL_UDL_SET(x)\ argument
2266 FIELD_PREP(SD25G_LANE_LANE_DE_LN_LOL_UDL, x)
2267 #define SD25G_LANE_LANE_DE_LN_LOL_UDL_GET(x)\ argument
2268 FIELD_GET(SD25G_LANE_LANE_DE_LN_LOL_UDL, x)
2271 #define SD25G_LANE_LANE_DE_LN_LOL_SET(x)\ argument
2272 FIELD_PREP(SD25G_LANE_LANE_DE_LN_LOL, x)
2273 #define SD25G_LANE_LANE_DE_LN_LOL_GET(x)\ argument
2274 FIELD_GET(SD25G_LANE_LANE_DE_LN_LOL, x)
2277 #define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_SET(x)\ argument
2278 FIELD_PREP(SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED, x)
2279 #define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_GET(x)\ argument
2280 FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED, x)
2283 #define SD25G_LANE_LANE_DE_LN_PMA_RXEI_SET(x)\ argument
2284 FIELD_PREP(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x)
2285 #define SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(x)\ argument
2286 FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x)
2291 __REG(TARGET_SD6G_LANE, t, 13, 832, 0, 1, 84, 60, 0, 1, 4)
2294 #define SD6G_LANE_LANE_DF_LOL_UDL_SET(x)\ argument
2295 FIELD_PREP(SD6G_LANE_LANE_DF_LOL_UDL, x)
2296 #define SD6G_LANE_LANE_DF_LOL_UDL_GET(x)\ argument
2297 FIELD_GET(SD6G_LANE_LANE_DF_LOL_UDL, x)
2300 #define SD6G_LANE_LANE_DF_LOL_SET(x)\ argument
2301 FIELD_PREP(SD6G_LANE_LANE_DF_LOL, x)
2302 #define SD6G_LANE_LANE_DF_LOL_GET(x)\ argument
2303 FIELD_GET(SD6G_LANE_LANE_DF_LOL, x)
2306 #define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\ argument
2307 FIELD_PREP(SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
2308 #define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\ argument
2309 FIELD_GET(SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
2312 #define SD6G_LANE_LANE_DF_SQUELCH_SET(x)\ argument
2313 FIELD_PREP(SD6G_LANE_LANE_DF_SQUELCH, x)
2314 #define SD6G_LANE_LANE_DF_SQUELCH_GET(x)\ argument
2315 FIELD_GET(SD6G_LANE_LANE_DF_SQUELCH, x)
2319 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 0, 0, 1, 20, 0, 0, 1, 4)
2322 #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_SET(x)\ argument
2323 FIELD_PREP(SD_CMU_CMU_00_R_HWT_SIMULATION_MODE, x)
2324 #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_GET(x)\ argument
2325 FIELD_GET(SD_CMU_CMU_00_R_HWT_SIMULATION_MODE, x)
2328 #define SD_CMU_CMU_00_CFG_PLL_LOL_SET_SET(x)\ argument
2329 FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_LOL_SET, x)
2330 #define SD_CMU_CMU_00_CFG_PLL_LOL_SET_GET(x)\ argument
2331 FIELD_GET(SD_CMU_CMU_00_CFG_PLL_LOL_SET, x)
2334 #define SD_CMU_CMU_00_CFG_PLL_LOS_SET_SET(x)\ argument
2335 FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_LOS_SET, x)
2336 #define SD_CMU_CMU_00_CFG_PLL_LOS_SET_GET(x)\ argument
2337 FIELD_GET(SD_CMU_CMU_00_CFG_PLL_LOS_SET, x)
2339 #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0 GENMASK(5, 4)
2340 #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(x)\ argument
2341 FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x)
2342 #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_GET(x)\ argument
2343 FIELD_GET(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x)
2347 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 0, 0, 1, 4)
2350 #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(x)\ argument
2351 FIELD_PREP(SD_CMU_CMU_05_CFG_REFCK_TERM_EN, x)
2352 #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_GET(x)\ argument
2353 FIELD_GET(SD_CMU_CMU_05_CFG_REFCK_TERM_EN, x)
2355 #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0 GENMASK(5, 4)
2356 #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(x)\ argument
2357 FIELD_PREP(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x)
2358 #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_GET(x)\ argument
2359 FIELD_GET(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x)
2363 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 4, 0, 1, 4)
2366 #define SD_CMU_CMU_06_CFG_DISLOS_SET(x)\ argument
2367 FIELD_PREP(SD_CMU_CMU_06_CFG_DISLOS, x)
2368 #define SD_CMU_CMU_06_CFG_DISLOS_GET(x)\ argument
2369 FIELD_GET(SD_CMU_CMU_06_CFG_DISLOS, x)
2372 #define SD_CMU_CMU_06_CFG_DISLOL_SET(x)\ argument
2373 FIELD_PREP(SD_CMU_CMU_06_CFG_DISLOL, x)
2374 #define SD_CMU_CMU_06_CFG_DISLOL_GET(x)\ argument
2375 FIELD_GET(SD_CMU_CMU_06_CFG_DISLOL, x)
2378 #define SD_CMU_CMU_06_CFG_DCLOL_SET(x)\ argument
2379 FIELD_PREP(SD_CMU_CMU_06_CFG_DCLOL, x)
2380 #define SD_CMU_CMU_06_CFG_DCLOL_GET(x)\ argument
2381 FIELD_GET(SD_CMU_CMU_06_CFG_DCLOL, x)
2384 #define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_SET(x)\ argument
2385 FIELD_PREP(SD_CMU_CMU_06_CFG_FORCE_RX_FILT, x)
2386 #define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_GET(x)\ argument
2387 FIELD_GET(SD_CMU_CMU_06_CFG_FORCE_RX_FILT, x)
2389 #define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD BIT(4)
2390 #define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_SET(x)\ argument
2391 FIELD_PREP(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, x)
2392 #define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_GET(x)\ argument
2393 FIELD_GET(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, x)
2396 #define SD_CMU_CMU_06_CFG_VCO_PD_SET(x)\ argument
2397 FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_PD, x)
2398 #define SD_CMU_CMU_06_CFG_VCO_PD_GET(x)\ argument
2399 FIELD_GET(SD_CMU_CMU_06_CFG_VCO_PD, x)
2402 #define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_SET(x)\ argument
2403 FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_CAL_RESETN, x)
2404 #define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_GET(x)\ argument
2405 FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_RESETN, x)
2408 #define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_SET(x)\ argument
2409 FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x)
2410 #define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_GET(x)\ argument
2411 FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x)
2415 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 12, 0, 1, 4)
2418 #define SD_CMU_CMU_08_CFG_VFILT2PAD_SET(x)\ argument
2419 FIELD_PREP(SD_CMU_CMU_08_CFG_VFILT2PAD, x)
2420 #define SD_CMU_CMU_08_CFG_VFILT2PAD_GET(x)\ argument
2421 FIELD_GET(SD_CMU_CMU_08_CFG_VFILT2PAD, x)
2424 #define SD_CMU_CMU_08_CFG_EN_DUMMY_SET(x)\ argument
2425 FIELD_PREP(SD_CMU_CMU_08_CFG_EN_DUMMY, x)
2426 #define SD_CMU_CMU_08_CFG_EN_DUMMY_GET(x)\ argument
2427 FIELD_GET(SD_CMU_CMU_08_CFG_EN_DUMMY, x)
2430 #define SD_CMU_CMU_08_CFG_CK_TREE_PD_SET(x)\ argument
2431 FIELD_PREP(SD_CMU_CMU_08_CFG_CK_TREE_PD, x)
2432 #define SD_CMU_CMU_08_CFG_CK_TREE_PD_GET(x)\ argument
2433 FIELD_GET(SD_CMU_CMU_08_CFG_CK_TREE_PD, x)
2436 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_SET(x)\ argument
2437 FIELD_PREP(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN, x)
2438 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_GET(x)\ argument
2439 FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN, x)
2441 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN BIT(4)
2442 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_SET(x)\ argument
2443 FIELD_PREP(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x)
2444 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_GET(x)\ argument
2445 FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x)
2449 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 16, 0, 1, 4)
2452 #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(x)\ argument
2453 FIELD_PREP(SD_CMU_CMU_09_CFG_EN_TX_CK_UP, x)
2454 #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_GET(x)\ argument
2455 FIELD_GET(SD_CMU_CMU_09_CFG_EN_TX_CK_UP, x)
2458 #define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(x)\ argument
2459 FIELD_PREP(SD_CMU_CMU_09_CFG_EN_TX_CK_DN, x)
2460 #define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_GET(x)\ argument
2461 FIELD_GET(SD_CMU_CMU_09_CFG_EN_TX_CK_DN, x)
2463 #define SD_CMU_CMU_09_CFG_SW_8G BIT(4)
2464 #define SD_CMU_CMU_09_CFG_SW_8G_SET(x)\ argument
2465 FIELD_PREP(SD_CMU_CMU_09_CFG_SW_8G, x)
2466 #define SD_CMU_CMU_09_CFG_SW_8G_GET(x)\ argument
2467 FIELD_GET(SD_CMU_CMU_09_CFG_SW_8G, x)
2470 #define SD_CMU_CMU_09_CFG_SW_10G_SET(x)\ argument
2471 FIELD_PREP(SD_CMU_CMU_09_CFG_SW_10G, x)
2472 #define SD_CMU_CMU_09_CFG_SW_10G_GET(x)\ argument
2473 FIELD_GET(SD_CMU_CMU_09_CFG_SW_10G, x)
2477 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 32, 0, 1, 4)
2480 #define SD_CMU_CMU_0D_CFG_PD_DIV64_SET(x)\ argument
2481 FIELD_PREP(SD_CMU_CMU_0D_CFG_PD_DIV64, x)
2482 #define SD_CMU_CMU_0D_CFG_PD_DIV64_GET(x)\ argument
2483 FIELD_GET(SD_CMU_CMU_0D_CFG_PD_DIV64, x)
2486 #define SD_CMU_CMU_0D_CFG_PD_DIV66_SET(x)\ argument
2487 FIELD_PREP(SD_CMU_CMU_0D_CFG_PD_DIV66, x)
2488 #define SD_CMU_CMU_0D_CFG_PD_DIV66_GET(x)\ argument
2489 FIELD_GET(SD_CMU_CMU_0D_CFG_PD_DIV66, x)
2492 #define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(x)\ argument
2493 FIELD_PREP(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, x)
2494 #define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_GET(x)\ argument
2495 FIELD_GET(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, x)
2498 #define SD_CMU_CMU_0D_CFG_JC_BYP_SET(x)\ argument
2499 FIELD_PREP(SD_CMU_CMU_0D_CFG_JC_BYP, x)
2500 #define SD_CMU_CMU_0D_CFG_JC_BYP_GET(x)\ argument
2501 FIELD_GET(SD_CMU_CMU_0D_CFG_JC_BYP, x)
2503 #define SD_CMU_CMU_0D_CFG_REFCK_PD BIT(4)
2504 #define SD_CMU_CMU_0D_CFG_REFCK_PD_SET(x)\ argument
2505 FIELD_PREP(SD_CMU_CMU_0D_CFG_REFCK_PD, x)
2506 #define SD_CMU_CMU_0D_CFG_REFCK_PD_GET(x)\ argument
2507 FIELD_GET(SD_CMU_CMU_0D_CFG_REFCK_PD, x)
2511 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 104, 0, 1, 20, 4, 0, 1, 4)
2514 #define SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(x)\ argument
2515 FIELD_PREP(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x)
2516 #define SD_CMU_CMU_1B_CFG_RESERVE_7_0_GET(x)\ argument
2517 FIELD_GET(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x)
2521 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 124, 0, 1, 68, 0, 0, 1, 4)
2524 #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_SET(x)\ argument
2525 FIELD_PREP(SD_CMU_CMU_1F_CFG_BIAS_DN_EN, x)
2526 #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_GET(x)\ argument
2527 FIELD_GET(SD_CMU_CMU_1F_CFG_BIAS_DN_EN, x)
2530 #define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_SET(x)\ argument
2531 FIELD_PREP(SD_CMU_CMU_1F_CFG_BIAS_UP_EN, x)
2532 #define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_GET(x)\ argument
2533 FIELD_GET(SD_CMU_CMU_1F_CFG_BIAS_UP_EN, x)
2536 #define SD_CMU_CMU_1F_CFG_IC2IP_N_SET(x)\ argument
2537 FIELD_PREP(SD_CMU_CMU_1F_CFG_IC2IP_N, x)
2538 #define SD_CMU_CMU_1F_CFG_IC2IP_N_GET(x)\ argument
2539 FIELD_GET(SD_CMU_CMU_1F_CFG_IC2IP_N, x)
2542 #define SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(x)\ argument
2543 FIELD_PREP(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x)
2544 #define SD_CMU_CMU_1F_CFG_VTUNE_SEL_GET(x)\ argument
2545 FIELD_GET(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x)
2549 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 192, 0, 1, 72, 0, 0, 1, 4)
2552 #define SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(x)\ argument
2553 FIELD_PREP(SD_CMU_CMU_30_R_PLL_DLOL_EN, x)
2554 #define SD_CMU_CMU_30_R_PLL_DLOL_EN_GET(x)\ argument
2555 FIELD_GET(SD_CMU_CMU_30_R_PLL_DLOL_EN, x)
2559 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 8, 0, 1, 4)
2562 #define SD_CMU_CMU_44_R_PLL_RSTN_SET(x)\ argument
2563 FIELD_PREP(SD_CMU_CMU_44_R_PLL_RSTN, x)
2564 #define SD_CMU_CMU_44_R_PLL_RSTN_GET(x)\ argument
2565 FIELD_GET(SD_CMU_CMU_44_R_PLL_RSTN, x)
2568 #define SD_CMU_CMU_44_R_CK_RESETB_SET(x)\ argument
2569 FIELD_PREP(SD_CMU_CMU_44_R_CK_RESETB, x)
2570 #define SD_CMU_CMU_44_R_CK_RESETB_GET(x)\ argument
2571 FIELD_GET(SD_CMU_CMU_44_R_CK_RESETB, x)
2575 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 12, 0, 1, 4)
2578 #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(x)\ argument
2579 FIELD_PREP(SD_CMU_CMU_45_R_EN_RATECHG_CTRL, x)
2580 #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_GET(x)\ argument
2581 FIELD_GET(SD_CMU_CMU_45_R_EN_RATECHG_CTRL, x)
2584 #define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(x)\ argument
2585 FIELD_PREP(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT, x)
2586 #define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_GET(x)\ argument
2587 FIELD_GET(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT, x)
2590 #define SD_CMU_CMU_45_RESERVED_SET(x)\ argument
2591 FIELD_PREP(SD_CMU_CMU_45_RESERVED, x)
2592 #define SD_CMU_CMU_45_RESERVED_GET(x)\ argument
2593 FIELD_GET(SD_CMU_CMU_45_RESERVED, x)
2596 #define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(x)\ argument
2597 FIELD_PREP(SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT, x)
2598 #define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_GET(x)\ argument
2599 FIELD_GET(SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT, x)
2601 #define SD_CMU_CMU_45_RESERVED_2 BIT(4)
2602 #define SD_CMU_CMU_45_RESERVED_2_SET(x)\ argument
2603 FIELD_PREP(SD_CMU_CMU_45_RESERVED_2, x)
2604 #define SD_CMU_CMU_45_RESERVED_2_GET(x)\ argument
2605 FIELD_GET(SD_CMU_CMU_45_RESERVED_2, x)
2608 #define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(x)\ argument
2609 FIELD_PREP(SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT, x)
2610 #define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_GET(x)\ argument
2611 FIELD_GET(SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT, x)
2614 #define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(x)\ argument
2615 FIELD_PREP(SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT, x)
2616 #define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_GET(x)\ argument
2617 FIELD_GET(SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT, x)
2620 #define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_SET(x)\ argument
2621 FIELD_PREP(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x)
2622 #define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_GET(x)\ argument
2623 FIELD_GET(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x)
2627 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 20, 0, 1, 4)
2629 #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0)
2630 #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(x)\ argument
2631 FIELD_PREP(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x)
2632 #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_GET(x)\ argument
2633 FIELD_GET(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x)
2637 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 896, 0, 1, 8, 0, 0, 1, 4)
2640 #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_SET(x)\ argument
2641 FIELD_PREP(SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0, x)
2642 #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_GET(x)\ argument
2643 FIELD_GET(SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0, x)
2645 #define SD_CMU_CMU_E0_PLL_LOL_UDL BIT(4)
2646 #define SD_CMU_CMU_E0_PLL_LOL_UDL_SET(x)\ argument
2647 FIELD_PREP(SD_CMU_CMU_E0_PLL_LOL_UDL, x)
2648 #define SD_CMU_CMU_E0_PLL_LOL_UDL_GET(x)\ argument
2649 FIELD_GET(SD_CMU_CMU_E0_PLL_LOL_UDL, x)
2654 4)
2657 #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(x)\ argument
2658 FIELD_PREP(SD_CMU_CFG_SD_CMU_CFG_CMU_RST, x)
2659 #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_GET(x)\ argument
2660 FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_CMU_RST, x)
2663 #define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(x)\ argument
2664 FIELD_PREP(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x)
2665 #define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_GET(x)\ argument
2666 FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x)
2670 __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 0, 0, 1, 8, 0, 0, 1, 4)
2673 #define SD_LANE_SD_SER_RST_SER_RST_SET(x)\ argument
2674 FIELD_PREP(SD_LANE_SD_SER_RST_SER_RST, x)
2675 #define SD_LANE_SD_SER_RST_SER_RST_GET(x)\ argument
2676 FIELD_GET(SD_LANE_SD_SER_RST_SER_RST, x)
2680 __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 0, 0, 1, 8, 4, 0, 1, 4)
2683 #define SD_LANE_SD_DES_RST_DES_RST_SET(x)\ argument
2684 FIELD_PREP(SD_LANE_SD_DES_RST_DES_RST, x)
2685 #define SD_LANE_SD_DES_RST_DES_RST_GET(x)\ argument
2686 FIELD_GET(SD_LANE_SD_DES_RST_DES_RST, x)
2690 __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 8, 0, 1, 8, 0, 0, 1, 4)
2693 #define SD_LANE_SD_LANE_CFG_MACRO_RST_SET(x)\ argument
2694 FIELD_PREP(SD_LANE_SD_LANE_CFG_MACRO_RST, x)
2695 #define SD_LANE_SD_LANE_CFG_MACRO_RST_GET(x)\ argument
2696 FIELD_GET(SD_LANE_SD_LANE_CFG_MACRO_RST, x)
2699 #define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(x)\ argument
2700 FIELD_PREP(SD_LANE_SD_LANE_CFG_EXT_CFG_RST, x)
2701 #define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_GET(x)\ argument
2702 FIELD_GET(SD_LANE_SD_LANE_CFG_EXT_CFG_RST, x)
2704 #define SD_LANE_SD_LANE_CFG_TX_REF_SEL GENMASK(5, 4)
2705 #define SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(x)\ argument
2706 FIELD_PREP(SD_LANE_SD_LANE_CFG_TX_REF_SEL, x)
2707 #define SD_LANE_SD_LANE_CFG_TX_REF_SEL_GET(x)\ argument
2708 FIELD_GET(SD_LANE_SD_LANE_CFG_TX_REF_SEL, x)
2711 #define SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(x)\ argument
2712 FIELD_PREP(SD_LANE_SD_LANE_CFG_RX_REF_SEL, x)
2713 #define SD_LANE_SD_LANE_CFG_RX_REF_SEL_GET(x)\ argument
2714 FIELD_GET(SD_LANE_SD_LANE_CFG_RX_REF_SEL, x)
2717 #define SD_LANE_SD_LANE_CFG_LANE_RST_SET(x)\ argument
2718 FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_RST, x)
2719 #define SD_LANE_SD_LANE_CFG_LANE_RST_GET(x)\ argument
2720 FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RST, x)
2723 #define SD_LANE_SD_LANE_CFG_LANE_TX_RST_SET(x)\ argument
2724 FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_TX_RST, x)
2725 #define SD_LANE_SD_LANE_CFG_LANE_TX_RST_GET(x)\ argument
2726 FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_TX_RST, x)
2729 #define SD_LANE_SD_LANE_CFG_LANE_RX_RST_SET(x)\ argument
2730 FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x)
2731 #define SD_LANE_SD_LANE_CFG_LANE_RX_RST_GET(x)\ argument
2732 FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x)
2736 __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 8, 0, 1, 8, 4, 0, 1, 4)
2739 #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_SET(x)\ argument
2740 FIELD_PREP(SD_LANE_SD_LANE_STAT_PMA_RST_DONE, x)
2741 #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_GET(x)\ argument
2742 FIELD_GET(SD_LANE_SD_LANE_STAT_PMA_RST_DONE, x)
2745 #define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_SET(x)\ argument
2746 FIELD_PREP(SD_LANE_SD_LANE_STAT_DFE_RST_DONE, x)
2747 #define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_GET(x)\ argument
2748 FIELD_GET(SD_LANE_SD_LANE_STAT_DFE_RST_DONE, x)
2751 #define SD_LANE_SD_LANE_STAT_DBG_OBS_SET(x)\ argument
2752 FIELD_PREP(SD_LANE_SD_LANE_STAT_DBG_OBS, x)
2753 #define SD_LANE_SD_LANE_STAT_DBG_OBS_GET(x)\ argument
2754 FIELD_GET(SD_LANE_SD_LANE_STAT_DBG_OBS, x)
2758 __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 24, 0, 1, 8, 4, 0, 1, 4)
2761 #define SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(x)\ argument
2762 FIELD_PREP(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x)
2763 #define SD_LANE_QUIET_MODE_6G_QUIET_MODE_GET(x)\ argument
2764 FIELD_GET(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x)
2768 __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 56, 0, 1, 56, 0, 0, 1, 4)
2771 #define SD_LANE_MISC_SD_125_RST_DIS_SET(x)\ argument
2772 FIELD_PREP(SD_LANE_MISC_SD_125_RST_DIS, x)
2773 #define SD_LANE_MISC_SD_125_RST_DIS_GET(x)\ argument
2774 FIELD_GET(SD_LANE_MISC_SD_125_RST_DIS, x)
2777 #define SD_LANE_MISC_RX_ENA_SET(x)\ argument
2778 FIELD_PREP(SD_LANE_MISC_RX_ENA, x)
2779 #define SD_LANE_MISC_RX_ENA_GET(x)\ argument
2780 FIELD_GET(SD_LANE_MISC_RX_ENA, x)
2783 #define SD_LANE_MISC_MUX_ENA_SET(x)\ argument
2784 FIELD_PREP(SD_LANE_MISC_MUX_ENA, x)
2785 #define SD_LANE_MISC_MUX_ENA_GET(x)\ argument
2786 FIELD_GET(SD_LANE_MISC_MUX_ENA, x)
2789 #define SD_LANE_MISC_CORE_CLK_FREQ GENMASK(5, 4)
2790 #define SD_LANE_MISC_CORE_CLK_FREQ_SET(x)\ argument
2791 FIELD_PREP(SD_LANE_MISC_CORE_CLK_FREQ, x)
2792 #define SD_LANE_MISC_CORE_CLK_FREQ_GET(x)\ argument
2793 FIELD_GET(SD_LANE_MISC_CORE_CLK_FREQ, x)
2797 __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 56, 0, 1, 56, 36, 0, 1, 4)
2800 #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_SET(x)\ argument
2801 FIELD_PREP(SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM, x)
2802 #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_GET(x)\ argument
2803 FIELD_GET(SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM, x)
2806 #define SD_LANE_M_STAT_MISC_M_LOCK_CNT_SET(x)\ argument
2807 FIELD_PREP(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x)
2808 #define SD_LANE_M_STAT_MISC_M_LOCK_CNT_GET(x)\ argument
2809 FIELD_GET(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x)
2814 __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 0, 0, 1, 4)
2817 #define SD_LANE_25G_SD_SER_RST_SER_RST_SET(x)\ argument
2818 FIELD_PREP(SD_LANE_25G_SD_SER_RST_SER_RST, x)
2819 #define SD_LANE_25G_SD_SER_RST_SER_RST_GET(x)\ argument
2820 FIELD_GET(SD_LANE_25G_SD_SER_RST_SER_RST, x)
2825 __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 4, 0, 1, 4)
2828 #define SD_LANE_25G_SD_DES_RST_DES_RST_SET(x)\ argument
2829 FIELD_PREP(SD_LANE_25G_SD_DES_RST_DES_RST, x)
2830 #define SD_LANE_25G_SD_DES_RST_DES_RST_GET(x)\ argument
2831 FIELD_GET(SD_LANE_25G_SD_DES_RST_DES_RST, x)
2836 __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 0, 0, 1, 4)
2839 #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(x)\ argument
2840 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_MACRO_RST, x)
2841 #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_GET(x)\ argument
2842 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_MACRO_RST, x)
2845 #define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(x)\ argument
2846 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, x)
2847 #define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_GET(x)\ argument
2848 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, x)
2850 #define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE BIT(4)
2851 #define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_SET(x)\ argument
2852 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE, x)
2853 #define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_GET(x)\ argument
2854 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE, x)
2857 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_SET(x)\ argument
2858 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE, x)
2859 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_GET(x)\ argument
2860 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE, x)
2863 #define SD_LANE_25G_SD_LANE_CFG_LANE_RST_SET(x)\ argument
2864 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_LANE_RST, x)
2865 #define SD_LANE_25G_SD_LANE_CFG_LANE_RST_GET(x)\ argument
2866 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_LANE_RST, x)
2869 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_SET(x)\ argument
2870 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV, x)
2871 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_GET(x)\ argument
2872 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV, x)
2875 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_SET(x)\ argument
2876 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN, x)
2877 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_GET(x)\ argument
2878 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN, x)
2881 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_SET(x)\ argument
2882 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY, x)
2883 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_GET(x)\ argument
2884 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY, x)
2887 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_SET(x)\ argument
2888 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV, x)
2889 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_GET(x)\ argument
2890 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV, x)
2893 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_SET(x)\ argument
2894 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN, x)
2895 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_GET(x)\ argument
2896 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN, x)
2899 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_SET(x)\ argument
2900 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY, x)
2901 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_GET(x)\ argument
2902 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY, x)
2905 #define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_SET(x)\ argument
2906 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN, x)
2907 #define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_GET(x)\ argument
2908 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN, x)
2911 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_SET(x)\ argument
2912 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN, x)
2913 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_GET(x)\ argument
2914 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN, x)
2917 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_SET(x)\ argument
2918 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING, x)
2919 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_GET(x)\ argument
2920 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING, x)
2923 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_SET(x)\ argument
2924 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI, x)
2925 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_GET(x)\ argument
2926 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI, x)
2929 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_SET(x)\ argument
2930 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x)
2931 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_GET(x)\ argument
2932 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x)
2937 __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 4, 0, 1, 4)
2940 #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_SET(x)\ argument
2941 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL, x)
2942 #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_GET(x)\ argument
2943 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL, x)
2946 #define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_SET(x)\ argument
2947 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL, x)
2948 #define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_GET(x)\ argument
2949 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL, x)
2952 #define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_SET(x)\ argument
2953 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL, x)
2954 #define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_GET(x)\ argument
2955 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL, x)
2958 #define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_SET(x)\ argument
2959 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED, x)
2960 #define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_GET(x)\ argument
2961 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED, x)
2964 #define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_SET(x)\ argument
2965 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV, x)
2966 #define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_GET(x)\ argument
2967 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV, x)
2970 #define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_SET(x)\ argument
2971 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV, x)
2972 #define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_GET(x)\ argument
2973 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV, x)
2976 #define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_SET(x)\ argument
2977 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL, x)
2978 #define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_GET(x)\ argument
2979 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL, x)
2982 #define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_SET(x)\ argument
2983 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV, x)
2984 #define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_GET(x)\ argument
2985 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV, x)
2988 #define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_SET(x)\ argument
2989 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL, x)
2990 #define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_GET(x)\ argument
2991 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL, x)
2994 #define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_SET(x)\ argument
2995 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL, x)
2996 #define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_GET(x)\ argument
2997 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL, x)
3000 #define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_SET(x)\ argument
3001 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x)
3002 #define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_GET(x)\ argument
3003 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x)
3008 __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 8, 0, 1, 4)
3011 #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_SET(x)\ argument
3012 FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE, x)
3013 #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_GET(x)\ argument
3014 FIELD_GET(SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE, x)
3017 #define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_SET(x)\ argument
3018 FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE, x)
3019 #define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_GET(x)\ argument
3020 FIELD_GET(SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE, x)
3023 #define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_SET(x)\ argument
3024 FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x)
3025 #define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_GET(x)\ argument
3026 FIELD_GET(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x)
3031 __REG(TARGET_SD_LANE_25G, t, 8, 28, 0, 1, 8, 4, 0, 1, 4)
3034 #define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_SET(x)\ argument
3035 FIELD_PREP(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, x)
3036 #define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_GET(x)\ argument
3037 FIELD_GET(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, x)